JP2012191062A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2012191062A JP2012191062A JP2011054534A JP2011054534A JP2012191062A JP 2012191062 A JP2012191062 A JP 2012191062A JP 2011054534 A JP2011054534 A JP 2011054534A JP 2011054534 A JP2011054534 A JP 2011054534A JP 2012191062 A JP2012191062 A JP 2012191062A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- semiconductor
- resin
- semiconductor device
- underfill
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/01—Manufacture or treatment
- H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
- H10W74/121—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/241—Dispositions, e.g. layouts
- H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/241—Dispositions, e.g. layouts
- H10W72/247—Dispositions of multiple bumps
- H10W72/248—Top-view layouts, e.g. mirror arrays
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/251—Materials
- H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
- H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/853—On the same surface
- H10W72/859—Bump connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/20—Configurations of stacked chips
- H10W90/26—Configurations of stacked chips the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/20—Configurations of stacked chips
- H10W90/28—Configurations of stacked chips the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/20—Configurations of stacked chips
- H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
【解決手段】実施形態によれば、半導体装置10は、配線基板1と、この配線基板1上に搭載された半導体チップ積層体2と、半導体チップ積層体の各半導体チップ間に充填されたアンダーフィル4層と、半導体チップ積層体2等の外側に被覆・形成されたモールド樹脂硬化物の封止層8とを備える。アンダーフィル層4は、アミン系の硬化剤を含むアンダーフィル樹脂の硬化物であり、Tgが65℃以上100℃以下の硬化物により構成されている。
【選択図】図1
Description
図1は、第1の実施形態の半導体装置を示す断面図である。
図1に示す半導体装置10は、一方の主面である表面(図1では上面)に配線回路(図示を省略。)を有する配線基板1と、この配線基板1の前記表面に搭載されて電気的に接続された半導体チップ積層体2を備えており、FBGA(Fine pitch Ball Grid Array)パッケージの形態を有する。
また、バンプ3は、Sn−Agはんだ(融点221℃)、Sn−Cuはんだ(融点227℃)等のはんだや、Au、Sn(融点232℃)等の金属材料からなり、バンプ径は5〜50μmで配列のピッチは10〜100μmとなっている。第1および第2の半導体チップ2a、2bと接続するバンプ3の接続には、熱圧着やリフロー等が用いられている。
なお、Tgの測定は、DMA(動的粘弾性測定)により行うことも可能である。
2枚のガラス板を20μmの隙間を作るように固定し、その隙間に実施形態のアンダーフィル樹脂とFC−BGA用樹脂をそれぞれ浸透させ、所定の距離(20mm)だけ浸透するのに要する時間を測定した。なお、ガラス板は110℃に加熱した。
Tg:130〜200℃
Tg未満の温度における熱膨張率(CTE1):0.8〜1.4ppm/℃
Tg以上の温度における熱膨張率(CTE2):3.0〜4.9ppm/℃
弾性率:15〜30GPa
(アンダーフィル樹脂A〜L)
まず、エポキシ系樹脂に、表1に示す粒径(平均粒径および最大粒径)のフィラー(シリカ粉末)を同表に示す配合割合(質量%)となるように混合し、さらに表1に示す硬化剤を添加・混合してなるアンダーフィル樹脂A〜Lを用意した。
次に、第1の半導体チップ2aと第2の半導体チップ2bとの間の隙間に充填する樹脂として、表1に示すA〜Lの各樹脂を使用し、さらに以下に示す物性値を有するaおよびbの2種類のモールド樹脂を使用して封止層8を形成し、図1に示す半導体装置10を製造した。モールド樹脂の物性値は、TMA法により測定された値である。
実施例1〜11および比較例1〜6で得られた半導体装置10の信頼性を、温度サイクル試験(−55℃/125℃)で確認した。これらの半導体装置10に、−55℃/125℃の温度サイクルを500サイクル加えた後、第2の半導体チップ2bの側面とアンダーフィル樹脂との間の剥離の有無を、断面解析して調べた。結果を表2に示す。
図2は、第2の実施形態の半導体装置を示す断面図である。
図2に示す第2の実施形態の半導体装置10は、一方の主面である表面(図2では上面)に配線回路を有し、裏面に金めっき等により形成された外部接続用端子7を有する配線基板1の表面に、第1から第4までの4個の半導体チップ2a、2b、2c、2dが互いに所定の間隔をおいて配置された半導体チップ積層体2が実装された構造を有する。なお、第1の半導体チップ2a、第2の半導体チップ2b、第3の半導体チップ2cおよび第4の半導体チップ2dの厚さは、いずれも50μm以下となっている。
Claims (5)
- 少なくとも一方の主面に配線層を有する配線基板と、
前記配線基板の前記主面に実装された、2つ以上の半導体チップが所定の間隔をおいて重ねて配置され、かつ各半導体チップが互いにバンプを介して電気的に接続された半導体チップ積層体と、
前記半導体チップ積層体の各半導体チップ間に充填された樹脂材料からなるアンダーフィル層と、
前記半導体チップ積層体の外側に被覆・形成されたモールド樹脂の硬化物からなる封止層と
を備えた半導体装置であり、
前記アンダーフィル層は、アミン系の硬化剤を含む樹脂硬化物からなり、かつ前記樹脂硬化物のガラス転移温度(Tg)が65℃以上100℃以下であることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記アンダーフィル層を構成する樹脂材料は、平均粒径が0.5μm未満の無機充填材を含有することを特徴とする半導体装置。 - 請求項1または2記載の半導体装置において、
前記半導体チップ積層体を構成する各半導体チップ間の隙間が40μm以下であることを特徴とする半導体装置。 - 請求項1ないし請求項3のいずれか1項記載の半導体装置において、
前記半導体チップ積層体を構成する2つ以上の半導体チップの厚さが、いずれも350μm以下であることを特徴とする半導体装置。 - 請求項1ないし請求項4のいずれか1項記載の半導体装置において、
前記モールド樹脂の硬化物は、Tgが130〜200℃で、Tg未満の温度における熱膨張率(CTE1)が0.8〜1.4ppm/℃、Tg以上の温度における熱膨張率(CTE2)が3.0〜4.9ppm/℃であり、曲げ弾性率が15〜30GPaであることを特徴とする半導体装置。
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011054534A JP2012191062A (ja) | 2011-03-11 | 2011-03-11 | 半導体装置 |
| TW101104583A TWI484601B (zh) | 2011-03-11 | 2012-02-13 | Semiconductor device and method for manufacturing semiconductor device |
| US13/397,098 US8710653B2 (en) | 2011-03-11 | 2012-02-15 | Chip on chip semiconductor device including an underfill layer having a resin containing an amine-based curing agent |
| CN201210043825.2A CN102683330B (zh) | 2011-03-11 | 2012-02-23 | 半导体装置以及半导体装置的制造方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011054534A JP2012191062A (ja) | 2011-03-11 | 2011-03-11 | 半導体装置 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2014172086A Division JP2014220534A (ja) | 2014-08-26 | 2014-08-26 | 半導体装置の製造方法 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2012191062A true JP2012191062A (ja) | 2012-10-04 |
Family
ID=46794793
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2011054534A Pending JP2012191062A (ja) | 2011-03-11 | 2011-03-11 | 半導体装置 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US8710653B2 (ja) |
| JP (1) | JP2012191062A (ja) |
| CN (1) | CN102683330B (ja) |
| TW (1) | TWI484601B (ja) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20140053598A (ko) * | 2012-10-26 | 2014-05-08 | 삼성전자주식회사 | 반도체 장치 및 이를 제조하는 방법 |
| JP2014127477A (ja) * | 2012-12-25 | 2014-07-07 | Sumitomo Bakelite Co Ltd | 半導体装置の製造方法 |
| JP2014152302A (ja) * | 2013-02-13 | 2014-08-25 | Sumitomo Bakelite Co Ltd | 半導体封止用エポキシ樹脂組成物、半導体装置の製造方法及び半導体装置 |
| JP2015095655A (ja) * | 2013-11-14 | 2015-05-18 | 三星電子株式会社Samsung Electronics Co.,Ltd. | 半導体パッケージ及びその製造方法 |
| KR20170098586A (ko) * | 2016-02-22 | 2017-08-30 | 삼성전자주식회사 | 반도체 패키지 |
| JP2022538567A (ja) * | 2019-06-26 | 2022-09-05 | インヴェンサス ボンディング テクノロジーズ インコーポレイテッド | マイクロエレクトロニクスにおける信頼性向上及び歩留向上のための直接接合型スタック構造 |
| US12266650B2 (en) | 2016-05-19 | 2025-04-01 | Adeia Semiconductor Bonding Technologies Inc. | Stacked dies and methods for forming bonded structures |
| US12266640B2 (en) | 2018-07-06 | 2025-04-01 | Adeia Semiconductor Bonding Technologies Inc. | Molded direct bonded and interconnected stack |
| US12341025B2 (en) | 2018-07-06 | 2025-06-24 | Adeia Semiconductor Bonding Technologies Inc. | Microelectronic assemblies |
| US12347820B2 (en) | 2018-05-15 | 2025-07-01 | Adeia Semiconductor Bonding Technologies Inc. | Stacked devices and methods of fabrication |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101719636B1 (ko) * | 2011-01-28 | 2017-04-05 | 삼성전자 주식회사 | 반도체 장치 및 그 제조 방법 |
| JP2013168577A (ja) * | 2012-02-16 | 2013-08-29 | Elpida Memory Inc | 半導体装置の製造方法 |
| CN103137611A (zh) * | 2013-01-22 | 2013-06-05 | 日月光半导体制造股份有限公司 | 晶片堆迭构造及其制造方法 |
| KR102053349B1 (ko) * | 2013-05-16 | 2019-12-06 | 삼성전자주식회사 | 반도체 패키지 |
| KR102107961B1 (ko) | 2013-11-14 | 2020-05-28 | 삼성전자 주식회사 | 반도체 장치 및 이의 제조 방법 |
| CN104795334B (zh) * | 2015-03-05 | 2018-01-05 | 浙江中控研究院有限公司 | 模块化封装的集成电路芯片及其制作方法 |
| JP2017112325A (ja) * | 2015-12-18 | 2017-06-22 | Towa株式会社 | 半導体装置及びその製造方法 |
| US10321572B2 (en) * | 2016-04-01 | 2019-06-11 | Skyworks Filter Solutions Japan Co., Ltd. | Electronic package including cavity defined by resin and method of forming same |
| US10957672B2 (en) * | 2017-11-13 | 2021-03-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure and method of manufacturing the same |
| US10529637B1 (en) * | 2018-10-31 | 2020-01-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit package and method of forming same |
| CN113330557A (zh) | 2019-01-14 | 2021-08-31 | 伊文萨思粘合技术公司 | 键合结构 |
| KR102685892B1 (ko) * | 2019-08-20 | 2024-07-19 | 에스케이하이닉스 주식회사 | 적층 반도체 칩을 포함하는 반도체 패키지 |
| JP2021129083A (ja) * | 2020-02-17 | 2021-09-02 | キオクシア株式会社 | 半導体装置およびその製造方法 |
| JP2023045675A (ja) * | 2021-09-22 | 2023-04-03 | キオクシア株式会社 | 半導体装置及び半導体装置の製造方法 |
| CN118213328A (zh) * | 2024-05-15 | 2024-06-18 | 荣耀终端有限公司 | 晶圆级封装结构、封装方法、芯片制品及电子设备 |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003297873A (ja) * | 2002-03-29 | 2003-10-17 | Hitachi Ltd | 半導体装置,構造体及び電子装置 |
| WO2008054011A1 (fr) * | 2006-10-31 | 2008-05-08 | Sumitomo Bakelite Co., Ltd. | Équipement électronique semi-conducteur et dispositif à semi-conducteur l'utilisant |
| JP2011029392A (ja) * | 2009-07-24 | 2011-02-10 | Hitachi Chem Co Ltd | 接着剤組成物及びその製造方法、並びに、半導体装置及びその製造方法 |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6670430B1 (en) * | 1999-12-17 | 2003-12-30 | Henkel Loctite Corporation | Thermosetting resin compositions comprising epoxy resins, adhesion promoters, and curatives based on the combination of nitrogen compounds and transition metal complexes |
| CA2483510A1 (en) * | 2002-04-26 | 2003-11-06 | Kaneka Corporation | Hardenable composition, hardening product, process for producing the same and light emitting diode sealed with the hardening product |
| JP2007511101A (ja) * | 2003-11-10 | 2007-04-26 | ヘンケル コーポレイション | Low−k誘電体含有半導体デバイスと共に使用される電子パッケージング材料 |
| US7279359B2 (en) * | 2004-09-23 | 2007-10-09 | Intel Corporation | High performance amine based no-flow underfill materials for flip chip applications |
| JP4757070B2 (ja) * | 2006-03-27 | 2011-08-24 | 富士通株式会社 | 半田付け用フラックス及び半導体素子の接合方法 |
| JP5388341B2 (ja) * | 2009-03-31 | 2014-01-15 | ナミックス株式会社 | アンダーフィル用液状樹脂組成物、フリップチップ実装体およびその製造方法 |
| JP5658436B2 (ja) * | 2009-04-16 | 2015-01-28 | 株式会社東芝 | 半導体装置 |
| TWI492339B (zh) * | 2009-06-01 | 2015-07-11 | 信越化學工業股份有限公司 | A dam material composition for a bottom layer filler material for a multilayer semiconductor device, and a manufacturing method of a multilayer semiconductor device using the dam material composition |
| JP5508802B2 (ja) | 2009-09-30 | 2014-06-04 | 株式会社東芝 | 半導体装置の製造方法 |
| US8536718B2 (en) * | 2010-06-24 | 2013-09-17 | Stats Chippac Ltd. | Integrated circuit packaging system with trenches and method of manufacture thereof |
| JP2012015398A (ja) | 2010-07-02 | 2012-01-19 | Toshiba Corp | 半導体装置 |
-
2011
- 2011-03-11 JP JP2011054534A patent/JP2012191062A/ja active Pending
-
2012
- 2012-02-13 TW TW101104583A patent/TWI484601B/zh active
- 2012-02-15 US US13/397,098 patent/US8710653B2/en active Active
- 2012-02-23 CN CN201210043825.2A patent/CN102683330B/zh active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003297873A (ja) * | 2002-03-29 | 2003-10-17 | Hitachi Ltd | 半導体装置,構造体及び電子装置 |
| WO2008054011A1 (fr) * | 2006-10-31 | 2008-05-08 | Sumitomo Bakelite Co., Ltd. | Équipement électronique semi-conducteur et dispositif à semi-conducteur l'utilisant |
| JP2011029392A (ja) * | 2009-07-24 | 2011-02-10 | Hitachi Chem Co Ltd | 接着剤組成物及びその製造方法、並びに、半導体装置及びその製造方法 |
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102000678B1 (ko) * | 2012-10-26 | 2019-07-16 | 삼성전자주식회사 | 반도체 장치 및 이를 제조하는 방법 |
| KR20140053598A (ko) * | 2012-10-26 | 2014-05-08 | 삼성전자주식회사 | 반도체 장치 및 이를 제조하는 방법 |
| JP2014127477A (ja) * | 2012-12-25 | 2014-07-07 | Sumitomo Bakelite Co Ltd | 半導体装置の製造方法 |
| JP2014152302A (ja) * | 2013-02-13 | 2014-08-25 | Sumitomo Bakelite Co Ltd | 半導体封止用エポキシ樹脂組成物、半導体装置の製造方法及び半導体装置 |
| JP2015095655A (ja) * | 2013-11-14 | 2015-05-18 | 三星電子株式会社Samsung Electronics Co.,Ltd. | 半導体パッケージ及びその製造方法 |
| KR102579876B1 (ko) * | 2016-02-22 | 2023-09-18 | 삼성전자주식회사 | 반도체 패키지 |
| US11664352B2 (en) | 2016-02-22 | 2023-05-30 | Samsung Electronics Co., Ltd. | Semiconductor package having a high reliability |
| KR20170098586A (ko) * | 2016-02-22 | 2017-08-30 | 삼성전자주식회사 | 반도체 패키지 |
| US11894346B2 (en) | 2016-02-22 | 2024-02-06 | Samsung Electronics Co., Ltd. | Semiconductor package having a high reliability |
| US12183718B2 (en) | 2016-02-22 | 2024-12-31 | Samsung Electronics Co., Ltd. | Semiconductor package having a high reliability |
| US12266650B2 (en) | 2016-05-19 | 2025-04-01 | Adeia Semiconductor Bonding Technologies Inc. | Stacked dies and methods for forming bonded structures |
| US12347820B2 (en) | 2018-05-15 | 2025-07-01 | Adeia Semiconductor Bonding Technologies Inc. | Stacked devices and methods of fabrication |
| US12401011B2 (en) | 2018-05-15 | 2025-08-26 | Adeia Semiconductor Bonding Technologies Inc. | Stacked devices and methods of fabrication |
| US12266640B2 (en) | 2018-07-06 | 2025-04-01 | Adeia Semiconductor Bonding Technologies Inc. | Molded direct bonded and interconnected stack |
| US12341025B2 (en) | 2018-07-06 | 2025-06-24 | Adeia Semiconductor Bonding Technologies Inc. | Microelectronic assemblies |
| JP2022538567A (ja) * | 2019-06-26 | 2022-09-05 | インヴェンサス ボンディング テクノロジーズ インコーポレイテッド | マイクロエレクトロニクスにおける信頼性向上及び歩留向上のための直接接合型スタック構造 |
| US12272677B2 (en) | 2019-06-26 | 2025-04-08 | Adeia Semiconductor Bonding Technologies Inc. | Direct bonded stack structures for increased reliability and improved yield in microelectronics |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201304083A (zh) | 2013-01-16 |
| US20120228762A1 (en) | 2012-09-13 |
| CN102683330B (zh) | 2015-06-10 |
| US8710653B2 (en) | 2014-04-29 |
| CN102683330A (zh) | 2012-09-19 |
| TWI484601B (zh) | 2015-05-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2012191062A (ja) | 半導体装置 | |
| JP4534062B2 (ja) | 半導体装置 | |
| US20190123025A1 (en) | Integrated circuit package assembly | |
| US7700414B1 (en) | Method of making flip-chip package with underfill | |
| TWI624016B (zh) | 電子封裝件及其製法 | |
| JP4206631B2 (ja) | 熱硬化性液状封止樹脂組成物、半導体素子の組立方法及び半導体装置 | |
| KR102012789B1 (ko) | 반도체 장치 | |
| JP4569605B2 (ja) | 半導体装置のアンダーフィルの充填方法 | |
| US6646350B2 (en) | Semiconductor device | |
| TW201413903A (zh) | 半導體封裝件及其製法 | |
| JP6123836B2 (ja) | 半導体装置の製造方法 | |
| CN100536096C (zh) | 制造具有降低的湿度灵敏性的半导体封装的方法 | |
| US10854576B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP2014220534A (ja) | 半導体装置の製造方法 | |
| JP2004063936A (ja) | 面実装構造体の形成方法、面実装構造体、および封止樹脂フィルム | |
| JP2013175492A (ja) | 半導体装置およびその製造方法 | |
| JP2011035283A (ja) | 半導体装置およびその製造方法 | |
| CN114068479B (zh) | 半导体封装结构及其制造方法 | |
| CN103579168A (zh) | 基板结构及具该基板结构的封装件 | |
| JP2010232671A (ja) | 半導体装置のアンダーフィル充填方法 | |
| Park et al. | Fine-pitch, cost effective flip chip package development: TAB-BGA | |
| Katsurayama et al. | Reliability evaluation of warpage of flip chip package with some kinds of underfill material | |
| US20120032351A1 (en) | Semiconductor package | |
| Tsai et al. | High performance molding FCBGA packaging development | |
| Cho et al. | Development of chip scale package for DRAM |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20130215 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20130513 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130625 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20140527 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140826 |
|
| A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20140903 |
|
| A912 | Re-examination (zenchi) completed and case transferred to appeal board |
Free format text: JAPANESE INTERMEDIATE CODE: A912 Effective date: 20140926 |
|
| RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20150216 |
|
| RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20150218 |
