JP2014016830A - Power estimation support program, power estimation support device, and power estimation support method - Google Patents

Abstract

An object of the present invention is to support estimation of power consumption of a circuit by enabling extraction of power parameters in a verification environment of a register transfer level.
A power estimation support apparatus (100) refers to mapping information (101) and sequentially traces cells in the previous stage starting from a first cell that outputs an observation signal on a netlist (NL), thereby generating RTL design data (RD). A second cell to which a signal of a netlist NL having a correspondence relationship with the signal is input is detected. The power estimation support apparatus 100 extracts difference circuit information representing the difference between the RTL design data RD and the netlist NL by extracting the partial circuits from the detected second cell to the first cell from the netlist NL. Create The power estimation support apparatus 100 creates signal information in which the signal name of the signal of the RTL design data RD having a correspondence relationship with the signal of the netlist NL input to the second cell is associated with the second cell. To do.
[Selection] Figure 1

Description

  The present invention relates to a power estimation support program, a power estimation support apparatus, and a power estimation support method.

  Conventionally, when estimating the power consumption of a circuit to be evaluated for the gate level, for example, a netlist after logic synthesis or a netlist after layout has been used to extract a power parameter necessary for estimating the power consumption. Functional verification is performed.

  As a related prior art, for example, there is a technique of extracting observation point data for power using an emulator or an FPGA (Field Programmable Gate Array) board. In addition, there is a technology that employs a measurement circuit that groups signals to be observed in a target circuit and calculates the number of operations of a plurality of observation targets.

JP 2007-102337 A JP 2009-53747 A

  However, in the prior art, when function verification using the net list of the circuit to be evaluated is performed in order to extract a power parameter necessary for estimating power consumption, it operates normally in an RTL (Register Transfer Level) verification environment. May not. Further, when a new verification environment for performing functional verification at the gate level of the circuit to be evaluated is constructed, there is a problem that the workload of the verifier increases.

  The present invention eliminates the problems caused by the prior art described above, and enables the estimation of power consumption of a circuit by enabling extraction of power parameters in a register transfer level verification environment. An object of the present invention is to provide a power estimation support apparatus and a power estimation support method.

  In order to solve the above-described problems and achieve the object, according to one aspect of the present invention, the design of the target circuit described by the netlist signal name and the register transfer level of the target circuit whose power consumption is to be estimated Obtaining mapping information representing a correspondence relationship with signal names of information, selecting an observation signal to be observed for a change in signal value from the net list, referring to the obtained mapping information, and The second cell to which the netlist signal having the correspondence with the design information signal is input by sequentially tracing the preceding cell starting from the first cell that outputs the observed signal selected above. And detecting a difference between the design information and the netlist by extracting a partial circuit from the second cell to the first cell detected from the netlist. Signal information that creates difference circuit information and associates the signal name of the design information signal that has a corresponding relationship with the netlist signal input to the second cell and the second cell. A power estimation support program, a power estimation support device, and a power estimation support method are proposed in which the generated difference circuit information and the signal information are output in association with each other.

  According to one aspect of the present invention, it is possible to support estimation of power consumption of a circuit by enabling extraction of power parameters in a register transfer level verification environment.

FIG. 1 is an explanatory diagram of an example of a power estimation support method according to the embodiment. FIG. 2 is a block diagram illustrating a hardware configuration example of the power estimation apparatus 200. FIG. 3 is a block diagram illustrating a functional configuration example of the power estimation apparatus 200. FIG. 4 is an explanatory diagram showing a specific example of the mapping data MD. FIG. 5 is an explanatory diagram showing a specific example of the power estimation setting data ST. FIG. 6 is an explanatory diagram showing a specific example of the clock starting point data CKD. FIG. 7 is an explanatory diagram showing a specific example of the clock start parent-child relationship data FD. FIG. 8 is an explanatory diagram showing a specific example of the calculation range ID map data ED. FIG. 9 is an explanatory diagram showing an example of assigning a calculation range ID and a partial clock tree ID. FIG. 10 is an explanatory diagram showing a specific example of the memory terminal data MD. FIG. 11 is an explanatory diagram showing a specific example of the non-clock tree observation point data OD. FIG. 12 is an explanatory diagram showing a specific example of the power coefficient (unit cell) data PU. FIG. 13 is an explanatory diagram showing a specific example of the power coefficient (memory) data PM. FIG. 14 is an explanatory diagram (part 1) of a creation example of the difference circuit data DF. FIG. 15 is an explanatory diagram (part 2) of an example of creating the difference circuit data DF. FIG. 16 is an explanatory diagram (part 3) of an example of creating the difference circuit data DF. FIG. 17 is an explanatory diagram of a specific example of the circuit description of the difference circuit. FIG. 18 is an explanatory diagram of a specific example of the instance description of the difference circuit. FIG. 19 is an explanatory diagram of a description example of an RTL test bench. FIG. 20 is an explanatory diagram showing a specific example of the RTL reference signal / port number relation table RP. FIG. 21 is an explanatory diagram of a specific example of the observation signal / port number relation table SP. FIG. 22 is an explanatory diagram of a specific example of the measurement circuit plan MP. FIG. 23 is an explanatory diagram showing an example of the data structure of the measurement circuit data KD. FIG. 24 is an explanatory diagram of a specific example of the measurement circuit instance data MI. FIG. 25 is an explanatory diagram of a specific example of the top-level description MH. FIG. 26 is an explanatory diagram of an example of updating the measurement circuit plan MP. FIG. 27 is an explanatory diagram (part 1) of a circuit configuration example of the measurement circuit. FIG. 28 is an explanatory diagram (part 2) of the circuit configuration example of the measurement circuit. FIG. 29 is an explanatory diagram of a specific example of the dynamic statistical data ER. FIG. 30 is an explanatory diagram illustrating an example of estimating the power consumption of the target circuit based on the dynamic statistical data ER. FIG. 31 is an explanatory diagram (part 1) of an output example of the power estimation data PE. FIG. 32 is an explanatory diagram (part 2) of an output example of the power estimation data PE. FIG. 33 is an explanatory diagram (part 3) of an output example of the power estimation data PE. FIG. 34 is a flowchart illustrating an example of a power estimation processing procedure of the power estimation apparatus 200. FIG. 35 is a flowchart illustrating an example of a specific processing procedure of basic data creation processing.

  Exemplary embodiments of a power estimation support program, a power estimation support apparatus, and a power estimation support method according to the present invention will be described below in detail with reference to the accompanying drawings.

(One example of power estimation support method)
FIG. 1 is an explanatory diagram of an example of a power estimation support method according to the embodiment. In FIG. 1, a power estimation support apparatus 100 is a computer that supports estimation of power consumption of a target circuit.

  The target circuit is a circuit whose power consumption is to be estimated, and is, for example, an LSI (Large Scale Integrated circuit). The circuit information of the target circuit tends to increase in detail as the design proceeds with RTL design data, a netlist after logic synthesis, and a netlist after layout. The circuit information of the target circuit may change due to a new function added to the target circuit.

  Here, the RTL design data (hereinafter referred to as “RTL design data RD”) is circuit information of a target circuit described in RTL. In an emulation or HDL (Hardware Description Language) software simulator, for example, simulation is performed using a set of data that can be logically synthesized. That is, the RTL design data RD is circuit information that can be emulated or HDL simulated and can be logically synthesized.

  The net list is information representing the connection relationship between cells in the target circuit. The cell is, for example, a circuit element such as a NOT gate, an AND gate, a wiring, a buffer, INV (inverter), and FF (flip-flop). Specifically, for example, the netlist is converted design data obtained by logically synthesizing and converting RTL design data RD, or design data obtained by processing the converted design data in a layout process. In the following description, the notation “net list NL” represents the net list after the layout of the target circuit.

  The waveform data of the signal of the RTL design data RD becomes data to be verified in emulation. On the other hand, when the power consumption of the target circuit is estimated with high accuracy, the waveform data used for the power consumption estimation is desirably the waveform data of the netlist after logic synthesis or the netlist signal after layout.

  Further, in either simulation or emulation, the creation of the verification environment is often limited to the RTL. For this reason, when performing a gate level simulation for power estimation, the construction of a gate level verification environment is an additional man-hour for power estimation.

  Therefore, in the present embodiment, power estimation support apparatus 100 has a path from a cell to which a signal on netlist NL corresponding to a signal on RTL design data RD is input to a cell that outputs a signal to be observed. Is extracted as a difference circuit from the RTL. As a result, it is possible to extract power parameters necessary for power estimation in the verification environment for RTL. Hereinafter, an example of the processing procedure of the power estimation support process of the power estimation support apparatus 100 will be described.

  (1) The power estimation support apparatus 100 acquires the RTL design data RD and the netlist NL of the target circuit. Specifically, for example, the power estimation support apparatus 100 may acquire the RTL design data RD and the netlist NL of the target circuit by a user operation input.

  (2) The power estimation support apparatus 100 creates the mapping information 101 based on the acquired RTL design data RD and the netlist NL. The mapping information 101 is information representing the correspondence between the signal name of the netlist NL and the signal name of the RTL design data RD. Specifically, for example, the mapping information 101 represents a correspondence relationship between signals indicating the same signal line between the RTL design data RD and the netlist NL.

  In the example of FIG. 1, the mapping information 101 represents the correspondence between the signal name “A” of the netlist NL and the signal name “a” of the RTL design data RD. Further, the correspondence relationship between the signal name “B” of the netlist NL and the signal name “b” of the RTL design data RD is shown. The correspondence between the signal name “C” of the netlist NL and the signal name “c” of the RTL design data RD is shown.

  (3) The power estimation support apparatus 100 selects an observation signal that is an observation target of a change in signal value from the netlist NL. The observation signal is, for example, a clock signal or a data signal output from a cell that causes power consumption of the target circuit. Specifically, for example, the observation signal is a signal output from a CGIC (clock gating integrated cell), a signal output from a cell whose toggle rate changes, or the like.

  The CGIC is a cell that temporarily stops the supply of the clock signal to the supply destination. According to CGIC, for example, when the input of the FF that is the supply destination of the clock signal does not change, the power consumption of the target circuit can be reduced by temporarily stopping the supply of the clock signal to the FF. it can. The toggle rate represents the number of times per unit time that the signal value of the signal has changed.

  That is, the waveform data of the signal output from the CGIC and the signal output from the cell whose toggle rate changes is an important index when estimating the power consumption of the target circuit. For this reason, the power estimation support apparatus 100 may select a signal output from the CGIC or a signal output from a cell whose toggle rate changes as an observation signal.

  In the example of FIG. 1, cells C1 to C6 included in the target circuit based on the netlist NL are displayed. Then, the signal sig output from the cell C6 in the target circuit is selected as the observation signal. However, in the drawing, a part of the target circuit is extracted and displayed.

  (4) The power estimation support apparatus 100 refers to the created mapping information 101, and sequentially follows the preceding cells starting from the first cell that outputs the selected observation signal on the netlist NL. As a result, the power estimation support apparatus 100 detects the second cell to which the signal of the netlist NL having a correspondence relationship with the signal of the RTL design data RD is input.

  In the example of FIG. 1, the signal name “A” of the signal input to the cell C1 of the netlist NL corresponds to the signal name “a” of the RTL design data RD. The signal name “B” of the signal input to the cell C2 of the netlist NL corresponds to the signal name “b” of the RTL design data RD. The signal name “C” of the signal input to the cell C3 of the netlist NL corresponds to the signal name “c” of the RTL design data RD. In addition, since the signal sig output from the cell C6 is selected as the observation signal, the cell C6 becomes the first cell. For this reason, the cell C1, the cell C2, and the cell C3 are detected as the second cell by sequentially tracing the preceding cells starting from the cell C6.

  (5) The power estimation support apparatus 100 represents the difference between the RTL design data RD and the netlist NL by extracting the partial circuit from the detected second cell to the first cell from the netlist NL. Create difference circuit information. In the example of FIG. 1, difference circuit information 103 representing the partial circuit 102 including the cells C1 to C6 is created.

  (6) The power estimation support apparatus 100 associates the signal name of the signal of the RTL design data RD having a correspondence with the signal of the netlist NL input to the second cell, and the signal indicating the second cell in association with each other. Create information. Specifically, for example, the signal information is a signal of RTL design data RD having a corresponding relationship with an input terminal of a partial circuit representing a difference between the RTL design data RD and the netlist NL and a signal input to the input terminal. The signal name is associated with the signal name. In the example of FIG. 1, signal information 104 is created.

  Here, the signal name of the signal of the RTL design data RD having a correspondence relationship with the signal (signal name “A”) of the netlist NL input to the cell C1 is “a”. Further, the signal name of the signal of the RTL design data RD having a correspondence relation with the signal (signal name “B”) of the netlist NL input to the cell C2 is “b”. Further, the signal name of the signal of the RTL design data RD that has a corresponding relationship with the signal (signal name “C”) of the netlist NL input to the cell C3 is “c”.

  For this reason, the signal information 104 includes signal information that represents the signal name “a” of the signal of the RTL design data RD in association with the cell C1. Further, the signal information 104 includes signal information representing the signal name “b” of the signal of the RTL design data RD in association with the cell C2. Further, the signal information 104 includes signal information that represents the signal name “c” of the signal of the RTL design data RD in association with the cell C3.

  (7) The power estimation support apparatus 100 outputs the generated difference circuit information and signal information in association with each other. In the example of FIG. 1, the difference circuit information 103 and the signal information 104 are output in association with each other.

  According to the power estimation support apparatus 100 according to the present embodiment described above, difference circuit information representing a difference between the RTL design data RD and the netlist NL can be created. Further, according to the power estimation support apparatus 100, the signal name of the signal of the RTL design data RD having a correspondence relationship with the signal of the netlist NL input to the second cell is associated with the second cell. Signal information can be created.

  Thereby, for example, the signal name “a, b, c” of the signal of the RTL design data RD having a correspondence relationship with the signal input to each input terminal of the partial circuit 102 can be specified. Therefore, the RTL design data RD and the partial circuit 102 can be appropriately connected in the RTL test bench.

  That is, by giving the RTL design data RD and the difference circuit information 103 to the RTL test bench, the logic simulation of the target circuit can be executed. As a result, it is possible to acquire a signal that is an important index when estimating the power consumption of the target circuit, for example, waveform data of a signal that is difficult to estimate from the RTL design data RD, and can support power estimation of the target circuit. .

  In the following description, the case where the power estimation support apparatus 100 shown in FIG. 1 is applied to the power estimation apparatus 200 that estimates the power consumption of the target circuit will be described.

(Hardware configuration example of power estimation apparatus 200)
FIG. 2 is a block diagram illustrating a hardware configuration example of the power estimation apparatus 200. In FIG. 2, a power estimation apparatus 200 includes a CPU (Central Processing Unit) 201, a ROM (Read-Only Memory) 202, a RAM (Random Access Memory) 203, a magnetic disk drive 204, a magnetic disk 205, and an optical disk. A drive 206, an optical disk 207, a display 208, an I / F (Interface) 209, a keyboard 210, a mouse 211, a scanner 212, and a printer 213 are included. Each component is connected by a bus 200.

  Here, the CPU 201 governs overall control of the power estimation apparatus 200. The ROM 202 stores a program such as a boot program. The RAM 203 is used as a work area for the CPU 201. The magnetic disk drive 204 controls reading / writing of data with respect to the magnetic disk 205 according to the control of the CPU 201. The magnetic disk 205 stores data written under the control of the magnetic disk drive 204.

  The optical disk drive 206 controls reading / writing of data with respect to the optical disk 207 according to the control of the CPU 201. The optical disk 207 stores data written under the control of the optical disk drive 206, or causes the computer to read data stored on the optical disk 207.

  The display 208 displays data such as a document, an image, and function information as well as a cursor, an icon, or a tool box. As the display 208, for example, a CRT, a TFT liquid crystal display, a plasma display, or the like can be adopted.

  The I / F 209 is connected to a network 214 such as a LAN (Local Area Network), a WAN (Wide Area Network), and the Internet through a communication line, and is connected to other devices via the network 214. The I / F 209 controls an internal interface with the network 214 and controls data input / output from an external device. For example, a modem or a LAN adapter may be employed as the I / F 209.

  The keyboard 210 includes keys for inputting characters, numbers, various instructions, and the like, and inputs data. Moreover, a touch panel type input pad or a numeric keypad may be used. The mouse 211 performs cursor movement, range selection, window movement, size change, and the like. A trackball or a joystick may be used as long as they have the same function as a pointing device.

  The scanner 212 optically reads an image and takes in the image data into the power estimation apparatus 200. The scanner 212 may have an OCR (Optical Character Reader) function. The printer 213 prints image data and document data. As the printer 213, for example, a laser printer or an ink jet printer can be adopted.

  Note that the power estimation apparatus 200 may not include the optical disk drive 206, the optical disk 207, the scanner 212, the printer 213, and the like among the above-described components.

(Functional configuration example of power estimation apparatus 200)
Next, a functional configuration example of the power estimation apparatus 200 will be described. FIG. 3 is a block diagram illustrating a functional configuration example of the power estimation apparatus 200. In FIG. 3, the power estimation apparatus 200 includes an acquisition unit 301, a mapping data creation unit 302, a difference circuit creation unit 303, a measurement circuit creation unit 304, an execution unit 305, a power calculation unit 306, and an output unit 307. It is the structure containing these. The acquisition unit 301 to the output unit 307 are functions as a control unit. Specifically, for example, a program stored in a storage device such as the ROM 202, the RAM 203, the magnetic disk 205, and the optical disk 207 illustrated in FIG. The function is realized by executing or by the I / F 209. Further, the processing results of each functional unit are stored in a storage device such as the RAM 203, the magnetic disk 205, and the optical disk 207, for example.

  The acquisition unit 301 has a function of acquiring RTL design data RD of the target circuit. The acquisition unit 301 has a function of acquiring the netlist NL of the target circuit. Specifically, for example, the acquisition unit 301 acquires the RTL design data RD and the netlist NL by a user operation input using the keyboard 210 and the mouse 211 illustrated in FIG.

  The acquisition unit 301 may acquire the RTL design data RD and the netlist NL from an external computer via the network 214, for example. Note that the acquisition unit 301 may acquire the netlist NL by logically synthesizing the acquired RTL design data RD, for example. However, in this case, the netlist NL is a netlist before layout.

  The mapping data creation unit 302 has a function of creating mapping data MD representing a correspondence relationship between signals indicating the same signal line between the RTL design data RD of the target circuit and the netlist NL. Specifically, for example, the mapping data creation unit 302 supplies the RTL design data RD and the netlist NT to the equivalence checking tool, and detects the signal name of the RTL design data RD that matches the signal name of the netlist NL. Thus, mapping data MD is created. The mapping data MD corresponds to the mapping information 101 shown in FIG.

  Further, the mapping data creation unit 302 may create the mapping data MD based on a logic synthesis tool and a user-defined design rule. For example, if there is a rule that the signal line name that becomes the FF of the RTL design data RD corresponds to the output terminal of the FF with the signal line name “+ _reg” in the netlist NL, information indicating this correspondence is created. . Here, a specific example of the mapping data MD will be described.

  FIG. 4 is an explanatory diagram showing a specific example of the mapping data MD. In FIG. 4, the mapping data MD is correspondence information (for example, correspondence information 400-1 to 400-3) indicating a correspondence relationship between signals indicating the same signal line between the RTL design data RD of the target circuit and the netlist NL. )have. In each correspondence information, the signal name of the RTL design data RD corresponding to the signal name of the netlist NL is described in CSV (Comma Separated Values) format.

  For example, according to the correspondence information 400-1, the correspondence between the signal name “MBAAA.a_register_req_0_.Q” of the netlist NL of the target circuit and the signal name “MBAAAA.a_register [0]” of the RTL design data RD is specified. be able to.

  Returning to the description of FIG. 3, the difference circuit creation unit 303 has a function of creating a difference circuit based on the netlist NL and the mapping data MD. Here, the difference circuit is a partial circuit representing a difference between the RTL design data RD and the netlist NL.

  Specifically, for example, the difference circuit creation unit 303 creates basic data of the target circuit. Here, the basic data is information used for logic simulation and power estimation of the target circuit. The basic data includes, for example, configuration data CG and difference circuit data DF, which will be described later.

  The configuration data CG includes clock start data CKD, calculation range ID map data ED, clock start parent-child relationship data FD, memory terminal data MD, non-clock tree observation point data OD, and power coefficient (unit cell) data. A file group including a PU, power coefficient (memory) data PM, and difference circuit configuration data DCG. An example of creating basic data will be described later with reference to FIGS.

  The measurement circuit creation unit 304 has a function of creating a measurement circuit that measures a change in the signal value of the observation signal. Here, as described above, the observation signal is a signal output from the cell that causes the power consumption of the target circuit. The measurement circuit is, for example, a circuit that measures the number of times the signal value of the observation signal has changed. That is, the measurement circuit is a circuit for measuring the toggle rate of the observation signal.

  Specifically, for example, the measurement circuit creation unit 304 creates a measurement circuit based on the measurement circuit plan MP. The measurement circuit plan MP is information that determines what measurement circuit is to be created. An example of creating a measurement circuit will be described later with reference to FIGS.

  The execution unit 305 has a function of executing a logic simulation of the target circuit based on the RTL design data RD. Specifically, for example, the execution unit 305 performs logic simulation of the target circuit based on the RTL design data RD as a result of mounting the difference circuit and the measurement circuit on the RTL test bench as shown in FIG. Run.

  The execution result of the logic simulation includes information regarding the waveform data of the observation signal. Specifically, for example, the execution result of the logic simulation includes a toggle rate representing the number of times per unit time that the signal value of the observation signal has changed. The dynamic statistical data ER representing the execution result of the logic simulation will be described later with reference to FIG.

  The logic simulation may be executed using an emulator, or may be executed using a software logic simulator. An emulator is hardware dedicated to simulation using an FPGA or a processor.

  The power calculation unit 306 has a function of calculating power consumption of the target circuit. Specifically, for example, the power calculation unit 306 estimates the power consumption of the target circuit based on the dynamic statistical data ER representing the execution result of the logic simulation. An example of estimating the power consumption of the target circuit based on the dynamic statistical data ER will be described later with reference to FIG.

  The output unit 307 has a function of outputting the calculated power consumption of the target circuit. Specifically, for example, the output unit 307 may output power estimation data PE as shown in FIGS. The output format includes, for example, display on the display 208, print output to the printer 213, transmission to an external device through the I / F 209, and storage in a storage device such as the RAM 203, the magnetic disk 205, and the optical disk 207.

  The output unit 307 may output the created difference circuit (for example, difference circuit data DF, difference circuit configuration data DCG, etc.). The output unit 307 may output the created measurement circuit (for example, measurement circuit plan MP, measurement circuit instance data MI, measurement circuit data KD, etc.). Thereby, a logic simulation based on the RTL design data RD and the difference circuit data DF can be performed at an arbitrary timing.

(Example of basic data creation)
Next, an example of creating basic data will be described with reference to FIGS. First, a script for performing power estimation settings will be described.

  FIG. 5 is an explanatory diagram showing a specific example of the power estimation setting data ST. In FIG. 5, power estimation setting data ST is a script for performing settings for power estimation for estimating the power consumption of the target circuit. The power estimation setting data ST is stored in a storage device such as the ROM 202, the RAM 203, the magnetic disk 205, and the optical disk 207, for example.

  First, the power estimation apparatus 200 reads a processing script (second line) of the power estimation setting data ST, for example. Next, the power estimation apparatus 200 sets the top module name of the target circuit that is the target of power estimation, and reads the technology library TLB corresponding to the netlist NL.

  Here, the technology library TLB is, for example, information including information on power characteristics for each cell, a wire load model, and the like. The information on the power characteristics of the cell includes, for example, the amount of power consumed by one toggle inside the cell. The technology library TLB is stored in a storage device such as the RAM 203, the magnetic disk 205, and the optical disk 207, for example.

  Then, the power estimation apparatus 200 reads the netlist NL, reads the clock source starting point data CS, reads the wiring capacitance data WD, and writes the capacitance value to the signal line. Here, the clock source starting point data CS is an SDC (Synopsys Design Constraint) file indicating the starting point of the clock source in the target circuit.

  The wiring capacitance data WD is information indicating the capacitance value of the wiring between cells in the target circuit after layout. As a result, data necessary for the power estimation process for estimating the power consumption of the target circuit is developed on the memory (for example, the RAM 203), and the power estimation process can be executed. The power estimation apparatus 200 acquires the clock source start point data CS and the wiring capacity data WD, for example, by a user operation input.

  Note that the capacitance value of each wiring may be calculated from, for example, an area called a wire load model and fanout, or may be calculated using a PLE (Physical Layout Estimator) technique. The wire load model is described in, for example, the technology library TLB.

  Next, the power estimation apparatus 200 designates the instance name and the depth (fpa2 :: calc_inst :: setup). This is a process in which an instance having an area larger than a specified value in an instance from a specified instance name to a specified depth is set as a calculation range. Thereby, the granularity for estimating the power consumption can be specified. The instance is, for example, a cell or a macro in the target circuit.

  Further, when it is necessary to create a difference circuit, the power estimation apparatus 200 calls “setup_mapping_data” and reads the mapping data MD. Then, the power estimation apparatus 200 executes “fpa2 :: std :: run”. As a result, basic data creation processing for creating basic data is executed to create basic data.

  Hereinafter, specific processing contents of the basic data creation processing will be described.

  First, the power estimation apparatus 200 adds a data field to the target circuit DB. Thereby, various types of information can be set in the cells and input / output terminals of the target circuit. Further, when a numerical value is set for a cell, an input / output terminal, or the like, a default value (for example, “−1”) can be set in advance.

  Next, the power estimation apparatus 200 creates clock start point data CKD by performing a clock tree analysis of the target circuit based on the netlist NL and the clock source start point data CS. Here, the clock tree is a set of cells having output terminals that can be traced from the clock source of the target circuit. By the clock tree analysis, the output terminal group in the target circuit can be classified into an output terminal group that can be traced from the clock source and a remaining output terminal group that is different from the output terminal group.

  The clock starting point data CKD is information that represents a partial clock tree and a signal name in association with each other. The partial clock tree is a portion including a group of cells that are guaranteed to have the same toggle rate in the clock tree. The clock origin parent-child relationship data FD is a file related to the parent-child relationship of the partial clock tree in the target circuit.

  Specifically, for example, the power estimating apparatus 200 sequentially follows the cell from the start point of the clock source specified by the clock source start point data CS, and assigns an ID number to the terminal of the cell. More specifically, for example, the power estimation apparatus 200 follows the cells in order from the starting point of the clock source, and when a cell other than the inverter and the buffer is detected, the ID number is changed, and the changed ID number is changed to the cell number. It is given to the output terminal.

  In addition, when the cell is an FF, CGIC, or RAM / ROM, the power estimation apparatus 200 assigns the same ID number to the input terminal of the cell. Note that the power estimation apparatus 200 can determine whether or not a cell is a CGIC based on, for example, whether or not the cell has a data field specific to CGIC.

  Thereby, the same ID number can be assigned to the output terminal of the cell on the clock tree having the same toggle rate and the input terminal of the FF, CGIC, and RAM / ROM. For example, an ID number “−1” is assigned to a portion different from the clock tree, that is, a cell terminal of the non-clock tree.

  In the following description, the identifier of the partial clock tree may be expressed as “partial clock tree ID” or “clock area ID”.

  Next, the power estimation apparatus 200 sets the clock area ID of the instance with reference to the ID number assigned to each terminal of the cell. Specifically, for example, the power estimation apparatus 200 takes out a list of terminals having ID numbers assigned to output terminals, assigns them to instances, and if an ID number is assigned to input terminals, Give the instance a number. Here, specific examples of the clock starting point data CKD and the clock starting point parent-child relationship data FD will be described.

  FIG. 6 is an explanatory diagram showing a specific example of the clock starting point data CKD. In FIG. 6, the clock starting point data CKD has clock starting point information (for example, clock starting point information 600-1 to 600-10) in which the partial clock tree IDs and the signal names are associated with each other in a comma-separated format in CSV format. ing.

  Here, the signal name is a signal name of a representative signal among signals included in the partial clock tree. The representative signal is, for example, a signal output from the output terminal of the cell whose ID number is changed, that is, the output terminal name of the cell whose toggle rate is changed. For example, according to the clock start point information 600-1, the correspondence between the partial clock tree ID “0” and the signal name “MB8AC0120QU8L...” Can be specified.

  FIG. 7 is an explanatory diagram showing a specific example of the clock start parent-child relationship data FD. In FIG. 7, the clock starting parent-child relationship data FD includes parent-child relationship information (for example, parent-child relationship information 700-1) in which a partial clock tree ID serving as a parent and a partial clock tree ID serving as a child are associated in a CSV format. )have.

  In the example of FIG. 7, the delimiter of the partial clock tree ID that is a child is blank. For example, according to the parent-child relationship information 700-1, the partial clock tree ID “1, 2, 3,... 81” that is a child of the partial clock tree ID “0” can be specified.

  Returning to the description of the basic data creation process, the power estimation apparatus 200 designates a calculation range on the target circuit. The calculation range is a region that is a power estimation target in a region on the target circuit. Specifically, for example, the power estimation apparatus 200 assigns a calculation range ID by designating a calculation range on the target circuit by a user operation input using the keyboard 210 or the mouse 211.

  More specifically, for example, the power estimation apparatus 200 designates a path to an instance that is a power estimation target by a user operation input. When the depth is greater than “0”, the power estimation apparatus 200 assigns a calculation range ID by designating an instance having an area larger than a predetermined value up to that depth as viewed from the specified instance. To do.

  As a result, calculation range ID map data ED representing the calculation range ID and the instance name in association with each other is created. Here, a specific example of the calculation range ID map data will be described.

  FIG. 8 is an explanatory diagram showing a specific example of the calculation range ID map data ED. In FIG. 8, calculation range ID map data ED is calculated range information (for example, calculation range information 800-) in which the calculation range ID, the instance name, and the debugging data (two pieces) are associated with each other by commas in CSV format. 1 to 800-8).

  The instance name is, for example, an instance name of a cell or macro or an instance name of a hierarchical instance. For example, according to the calculation range information 800-1, the correspondence relationship between the calculation range ID “0”, the instance name “MB8AC0120QU8L”, the debug data “7261599993.0”, and “48223392.0” can be specified. Here, an example of assigning the calculation range ID and the partial clock tree ID will be described.

  FIG. 9 is an explanatory diagram showing an example of assigning a calculation range ID and a partial clock tree ID. In FIG. 9, a thick square box represents an instance corresponding to the calculation range. In the example of FIG. 9, the calculation range from No. 0 to No. 3 is designated. A thin framed box represents a FF.

  Circles represent clock starting points. In the example of FIG. 9, the first to fourth clock starting points are shown. A triangle connected from a circle represents a partial clock tree. In FIG. 9, the notation (N, M) represents (calculation range ID, partial clock tree ID).

  Returning to the description of the basic data creation processing, the power estimation apparatus 200 extracts RAM / ROM from the target circuit. Then, the power estimation apparatus 200 designates a set of signals indicating the number of accesses to the RAM / ROM. As a result, memory terminal data MD is created. The memory terminal data MD is a file in which an instance name of a memory in the target circuit and an expression for counting the number of accesses of each port are described. Here, a specific example of the memory terminal data MD will be described.

  FIG. 10 is an explanatory diagram showing a specific example of the memory terminal data MD. In FIG. 10, the memory terminal data MD has memory information (for example, memory information 1000-1 and 1000-2) of each memory in the target circuit in an XML (Extensible Markup Language) format.

  Each memory information indicates a collection of information related to one instance. Here, memID is the ID of the memory. calcInstId is a calculation range ID to which the instance belongs. name is the name of the instance.

  Each memory information has port information (for example, port information 1000-1-1 and 1000-1-2) of each memory. Here, memID is the ID of the memory. calcInstId is a calculation range ID to which the instance belongs. signal is a signal indicating the number of accesses to the port. According to the memory terminal data MD, an expression for counting the number of accesses of each port of the memory in the target circuit can be specified.

  Returning to the description of the basic data creation process, the power estimation apparatus 200 extracts the observation signal of the non-clock tree from the target circuit. Specifically, for example, the power estimation apparatus 200 extracts a non-clock tree observation signal by randomly selecting a signal having a ratio r among non-clock tree signals with reference to the netlist NL.

  Specifically, for example, the power estimation apparatus 200 randomly selects one of the output terminals from the non-clock tree. This output terminal is an output terminal that cannot be traced from the clock source. The power estimation apparatus 200 determines whether the number of output terminals selected from the non-clock tree is less than a threshold value.

  The threshold is, for example, a value obtained by multiplying the total number of output terminals included in the non-clock tree, that is, the total number of output terminals that cannot be traced from the clock source by the ratio r. Here, when the number of selected output terminals is less than the threshold value, the power estimation apparatus 200 randomly selects an unselected output terminal from the non-clock tree. Thereby, the signal of the ratio r among the signals included in the non-clock tree can be selected at random, and the signals of the non-clock tree can be thinned out.

  The ratio r is set in advance and stored in a storage device such as the ROM 202, the RAM 203, the magnetic disk 205, and the optical disk 207. The ratio r is 2 [%], for example. Note that the power estimation apparatus 200 may randomly select a signal having a ratio r among non-clock tree signals for each designated calculation range in the target circuit.

  As a result, non-clock tree observation point data OD is created. The non-clock tree observation point data OD is a file that lists signals to be observed in each calculation range. Here, a specific example of the non-clock tree observation point data OD will be described.

  FIG. 11 is an explanatory diagram showing a specific example of the non-clock tree observation point data OD. In FIG. 11, the non-clock tree observation point data OD includes observation point information (for example, observation point information 1100-1 to 1100-10) that represents a calculation range ID and a signal name to be observed in a CSV format. Have.

  For example, according to the observation point information 1100-1, the signal name “MB8AC0120QUA8L...” Of the observation signal to be observed in the calculation range of the calculation range ID “0” can be specified.

  Returning to the description of the basic data creation processing, the power estimation apparatus 200 calculates the power coefficient of the unit cell and the memory in the target circuit. Here, the unit cell is a cell such as an AND gate or FF. Specifically, for example, the power estimation apparatus 200 calculates the power coefficient of the unit cell and the memory by giving a fixed value to each of the clock tree toggle rate and the non-clock tree toggle rate to obtain a power value. You may decide to do it. For example, the fixed value of the clock tree toggle rate is “0.2”, and the fixed value of the non-clock tree toggle rate is “0.1”.

  As a result, power coefficient (unit cell) data PU and power coefficient (memory) data PM are created. The power coefficient (unit cell) data PU is a file in which the value of the power coefficient of the unit cell in the target circuit is described. The power coefficient (memory) data PM is a file in which the value of the power coefficient of the memory in the target circuit is described. Here, specific examples of the power coefficient (unit cell) data PU and the power coefficient (memory) data PM will be described.

  FIG. 12 is an explanatory diagram showing a specific example of the power coefficient (unit cell) data PU. In FIG. 12, power coefficient (unit cell) data PU is power coefficient information (for example, power coefficient information 1200-1 to 1200-10) that represents a circuit range, a power coefficient value, and supplementary information in a CSV format. have.

  Of the power coefficient information, the first and second information separated by a comma represents a circuit range. Specifically, the first information represents the calculation range ID, and the second information represents the partial clock tree ID. In addition, among the power coefficient information, the third to sixth information separated by commas are power coefficient values.

  Specifically, the third information is a power coefficient value of a cell that is not an FF in the cell group included in the clock tree. The fourth information is a power coefficient value of a cell that is not an FF in the cell group included in the non-clock tree. The fifth information is the power coefficient value of the FF in the cell group included in the non-clock tree. The sixth information is the power coefficient value of the FF in the cell group included in the non-clock tree. Further, among the power coefficient information, the seventh to eleventh information separated by commas is supplementary information for debugging.

  For example, according to the power coefficient information 1200-1, the power coefficient values of various cells in the circuit range specified from the calculation range ID “0” and the partial clock tree ID “−1” can be specified. The partial clock tree ID “−1” represents a non-clock tree system.

  FIG. 13 is an explanatory diagram showing a specific example of the power coefficient (memory) data PM. In FIG. 13, power coefficient (memory) data PM is expressed in CSV format in correspondence with power coefficient information (for example, power coefficient information 1300-1 to 1300-) in which memory names (for example, RAM names) are associated with power coefficient values. 10).

  The power coefficient value is a power value per port, for example, and is an average value of read and write. For example, according to the power coefficient information 1300-1, the power coefficient value “2294333.000000” of the RAM name “MB8AC0120QUA8L /...” Can be specified.

  Returning to the description of the basic data creation processing, the power estimation apparatus 200 creates difference circuit data DF representing a difference circuit between the RTL design data RD and the netlist NL. Here, an example of creating the difference circuit data DF will be described with reference to FIGS.

  14 to 16 are explanatory diagrams showing examples of creating the difference circuit data DF. In (i) of FIG. 14, cells C1 to C11 in the target circuit based on the netlist NL, wirings w1 to w10 representing connection relationships between the cells, and output terminals p1 to p11 of the cells C1 to C11 are provided. It is shown. In the drawing, a part of the target circuit is extracted and displayed.

  In (ii) of FIG. 14, the power estimation apparatus 200 assigns a wire ID (“wire_id” in the drawing) to the output terminals p1 to p11 of the cells C1 to C11. The wire ID is an identifier for identifying a wiring between cells. In the example of (ii) of FIG. 14, the default value “−1” of the wire ID is assigned to the output terminals p1 to p11 of the cells C1 to C11.

  In (iii) of FIG. 15, the power estimation apparatus 200 refers to the mapping data MD, and among the signal names of the signals on the netlist NL, the signal names of the signals corresponding to the signal names of the signals on the RTL design data RD. Is identified. Then, the power estimation apparatus 200 gives the signal name of the corresponding RTL design data RD to the wiring on the netlist NL whose end point is the output terminal that outputs the signal of the specified signal name.

  In the example of (iii) of FIG. 15, the signal name “A [0]” of the RTL design data RD is assigned to the wiring w1, and the signal name “A [1]” of the RTL design data RD is assigned to the wiring w2. Yes. Further, the signal name “B [0]” of the RTL design data RD is assigned to the wiring w3, the signal name “B [1]” of the RTL design data RD is assigned to the wiring w4, and the RTL design data RD of the wiring w5 is assigned. The signal name “B [2]” is assigned.

  In (iv) of FIG. 15, the power estimation apparatus 200 refers to the clock start point data CKD and the non-clock tree observation point data OD and selects an observation signal to be observed. The observation signal is, for example, a signal selected at random from the representative signal of the signals included in the partial clock tree and the non-clock tree.

  In the example of (iv) of FIG. 15, the observation signal s1 output from the output terminal p9 of the cell C9 is selected (thick line in FIG. 15 (iv)). In this case, for example, the power estimation apparatus 200 drives the output terminal p9 (or the wiring w9) that outputs the observation signal s1, and assigns an ID number to the wire ID of the output terminal p9. In the example of (iv) in FIG. 15, the ID number “0” is assigned to the wire ID of the output terminal p9.

  In FIG. 16 (v), the power estimation apparatus 200 sequentially traces the cells in the subsequent stage from the cell that outputs the observation signal on the netlist NL, so that the signal name corresponding to the signal name of the signal on the RTL design data RD. The cell which outputs the signal of is detected.

  Specifically, for example, the power estimation apparatus 200 refers to the netlist NL and identifies a fan-in terminal list having a depth of “1” from the driven output terminal p9 (or the wiring w9). Next, the power estimation apparatus 200 selects an output terminal from the specified terminal list, and assigns an ID number to the wire ID of the selected output terminal.

  Then, the power estimation apparatus 200 determines whether or not the signal name of the RTL design data RD is given to the wiring having the selected output terminal as an end point. For example, the power estimation apparatus 200 identifies and outputs an output terminal list of a fan-in terminal having a depth “1” starting from the selected output terminal until a wiring to which the signal name of the RTL design data RD is assigned is detected. The assignment of the ID number to the wire ID is repeated.

  In the example of (v) in FIG. 16, the ID number “1” is assigned to the wire ID of the output terminal p6. The ID number “2” is assigned to the wire ID of the output terminal p7. At this time, the wiring to which the signal name of the RTL design data RD is assigned is not detected.

  In the example of (vi) of FIG. 16, the ID number “3” is assigned to the wire ID of the output terminal p1. The ID number “4” is assigned to the wire ID of the output terminal p2. The ID number “5” is assigned to the wire ID of the output terminal p3. In addition, the wirings w1, w2, and w3 to which the signal names of the RTL design data RD are assigned are detected.

  Then, the power estimation apparatus 200 creates difference circuit data DF representing the difference circuit between the RTL design data RD and the netlist NL corresponding to the selected observation signal. Specifically, for example, first, the power estimation apparatus 200 extracts an output terminal in which an ID number (an ID number other than the default value) is assigned to the wire ID from the target circuit. More specifically, for example, the power estimation apparatus 200 extracts an output terminal having a non-negative wire ID from the target circuit. In the example of (iv) in FIG. 16, output terminals p1, p2, p3, p6, p7, and p9 are extracted.

  Here, the observation signal s1 is a signal having a signal name that is not included in the RTL design data RD. The output terminals p1, p2, and p3 are end points of the wirings w1, w2, and w3 to which the signal names of the RTL design data RD are assigned. Therefore, the difference circuit corresponding to the observation signal s1 is a partial circuit including cells C6, C7, and C9 having output terminals p6, p7, and p9.

  Here, a specific example of the difference circuit data DF will be described. The difference circuit data DF includes a circuit description and an instance description of the difference circuit.

  FIG. 17 is an explanatory diagram of a specific example of the circuit description of the difference circuit. In FIG. 17, a circuit description 1700 includes a logic cone representing a difference circuit between the RTL design data RD and the netlist NL. For example, the logic cone is a partial circuit including cells C6, C7, and C9 in the case where the observation signal s1 shown in (vi) of FIG. 16 is selected.

  Specifically, for example, the circuit description 1700 includes a description representing the wire ID of the wiring connected to the output terminal of the difference circuit. The example shown in (vi) of FIG. 16 includes a description representing the wire ID “0” of the wiring connected to the output terminal p9 of the difference circuit. The circuit description 1700 includes a description representing the wire ID of each wiring connected to each input terminal of the difference circuit. The example shown in (vi) of FIG. 16 includes a description representing the wire IDs “3”, “4”, and “5” of each wiring connected to each input terminal of the difference circuit.

  The circuit description 1700 includes a description representing the wire ID of the wiring connected to each cell included in the difference circuit. The example shown in (vi) of FIG. 16 includes a description representing the wire IDs “0”, “1”, and “2” of the wiring connected to the cell C9 included in the difference circuit. In addition, a description representing the wire IDs “1” and “3” of the wiring connected to the cell C6 included in the difference circuit is included. In addition, a description representing the wire IDs “2”, “4”, and “5” of the wiring connected to the cell C7 included in the difference circuit is included.

  For example, in the case of FIG. 16, since the number of input ports of the difference circuit is 3 and the number of output ports is 1, input / output terminals are input [2: 0] in_data, output [0: 0] out_data. Further, since there are a total of six wire_ids from 0 to 5, wires corresponding to these are declared. For example, wire [0: 5] internal_wire; When ports p1, p2, and p3 corresponding to in_data indexes 0, 1, and 2 are assigned, assign internal_wire [3] = in_data [0]; assign internal_wire [4] = in_data [1]; assign internal_wire [5] = in_data [2]; Similarly, for the output, a description of assign_out_data [0] = internal_wire [0]; is described.

  The instance of the cell is described in the original description as, for example, BUF U3 (.A (w1), .Y (w6)) for C3. Therefore, a unique name of the instance name is generated and generated as BUF inst — 0000 (.A (.internal_wire [3]), .Y (internal_wire_ [1])) as a description corresponding to C3. The same applies to other instances. In this way, a flattened circuit can be generated, a logic cone portion can be cut out, and a cut out logic cone description of 1700 can be generated.

  FIG. 18 is an explanatory diagram of a specific example of the instance description of the difference circuit. In FIG. 18, an instance description 1800 represents a code in which a difference circuit is instantiated. Specifically, for example, in the instance description 1800, an instance name given to the module that instantiated the difference circuit is given by an absolute path.

  For example, when a difference circuit is placed under the name “diff_circuit” on an RTL test bench, an absolute path (for example, testbench.target) to the top module of the circuit to be evaluated (target circuit) in the simulation environment is specified. At this time, the instance description 1800 is created by rewriting the signal so that it can be hierarchically referenced in the simulation environment.

  According to the circuit description 1700 and the instance description 1800, the output signal of the difference circuit is output to the output (for example, out_data) of the difference circuit. Here, a description example of the RTL test bench will be described. The RTL test bench is stored in a storage device such as the RAM 203, the magnetic disk 205, and the optical disk 207, for example.

  FIG. 19 is an explanatory diagram of a description example of an RTL test bench. In FIG. 19, a description 1900 is a description included in the RTL test bench, and is used for instantiating a measurement circuit and a difference circuit, which will be described later, in the RTL test bench. In the drawing, a part of an RTL test bench is extracted and displayed. If there is no difference circuit, only a description relating to the measurement circuit is sufficient.

  For example, the power estimation apparatus 200 repeatedly performs a process of selecting an observation signal and creating a difference circuit until there is no unselected observation signal selected from the clock start point data CKD and the non-clock tree observation point data OD. Do. At this time, the power estimation apparatus 200 may create difference circuit data DF for each observation signal. However, when the signal name corresponding to the signal name of the selected observation signal is included in the RTL design data RD, the difference circuit data DF is not created.

  In addition, the power estimation apparatus 200 performs the processes shown in FIGS. 15 and 16 until there is no unselected observation signal that is not selected from the clock starting point data CKD and the non-clock tree observation point data OD. Thereafter, the difference circuit data DF may be created. In this case, one difference circuit data DF is created for the target circuit. Thereby, compared with the case where the difference circuit data DF for each observation signal is created, the overlapping portion between the difference circuits can be eliminated, and the circuit amount of the difference circuit can be reduced.

  In addition, the power estimation apparatus 200 creates difference circuit configuration data DCG corresponding to the created difference circuit data DF. Here, the differential circuit configuration data DCG includes a clock tree observation signal / port number relation table CP, a non-clock tree observation signal / port number relation table NCP, and an RTL reference signal / port number relation table RP.

  Here, a case where the difference circuit is one module and the clock tree observation signal / port number relation table CP and the non-clock tree observation signal / port number relation table NCP are not distinguished will be described as an example. Specifically, a relation table in which observation signals of either a clock tree or a non-clock tree and port numbers are associated is referred to as an “observation signal / port number relation table SP”. Note that the observation signal of the clock tree is a representative signal among the signals included in the partial clock tree as described above.

  Specifically, for example, the power estimation apparatus 200 includes an RTL reference signal / represented in association with an input terminal serving as an end point of a wiring to which a signal name of the RTL design data RD is assigned, and a signal name of the RTL design data RD. A port number relation table RP is created. Here, a specific example of the RTL reference signal / port number relation table RP will be described.

  FIG. 20 is an explanatory diagram showing a specific example of the RTL reference signal / port number relation table RP. In FIG. 20, the RTL reference signal / port number relationship table RP is information indicating the relationship between the port number of the input terminal of the difference circuit and the signal name of the signal on the RTL design data RD. The RTL reference signal / port number relationship table RP corresponds to the signal information 104 shown in FIG.

  According to the RTL reference signal / port number relationship table RP, the port number “0” of the input terminal of the difference circuit and the signal name “TOP.AB.C [0]” of the signal on the RTL design data RD. Relationships can be identified. Further, the relationship between the port number “1” of the input terminal of the difference circuit and the signal name “TOP.A.B.EN_A” of the signal on the RTL design data RD can be specified.

  In addition, the power estimation apparatus 200 creates an observation signal / port number relationship table SP in which the selected observation signal is associated with an output terminal that outputs the observation signal. Here, a specific example of the observation signal / port number relation table SP will be described.

  FIG. 21 is an explanatory diagram of a specific example of the observation signal / port number relation table SP. In FIG. 21, the observation signal / port number relationship table SP is information indicating the relationship between the port number of the output terminal of the difference circuit and the signal name of the observation signal on the netlist NL.

  According to the observation signal / port number relationship table SP, the relationship between the port number “0” of the output terminal of the difference circuit and the signal name “TOP.AB.s0” of the observation signal can be specified. Further, the relationship between the port number “1” of the output terminal of the difference circuit and the signal name “TOP.A.B.s10” of the observation signal can be specified.

  That is, according to the observation signal / port number relationship table SP and the RTL reference signal / port number relationship table RP, it is possible to specify which port number of the difference circuit and which signal should be connected.

(Example of creating a measurement circuit)
Next, an example of creating a measurement circuit will be described. First, the measurement circuit creation unit 304 creates a measurement circuit plan MP for the measurement circuit. Specifically, for example, the measurement circuit creation unit 304 is based on the calculation range ID map data ED, clock starting point data CKD, non-clock tree observation point data OD, memory terminal data MD, and power coefficient (unit cell) data PU. Then, the measurement circuit plan MP is created.

  FIG. 22 is an explanatory diagram of a specific example of the measurement circuit plan MP. In FIG. 22, the measurement circuit plan MP is information that determines what measurement circuit is to be created. In the measurement circuit plan MP, for example, an upper limit of the number of signals that can be connected per core element, an upper limit value of core elements that can be included in the core, and grouping conditions are described.

  The grouping condition is, for example, a condition in which an observation signal included in the clock tree is a grouping target. In addition, a partial clock tree in which a signal to be grouped is a representative signal has one calculation range ID, and the power coefficient of the partial clock tree is less than bound_ratio with respect to the total value of the power coefficients of all clock trees. It is. In addition, it is a condition that addresses are assigned to cells included in the same core in the order of declaration and the head is 0. As a result, the address map can be determined at the same time.

  Next, the measurement circuit creation unit 304 creates measurement circuit data KD of the measurement circuit. Here, the data structure of the measurement circuit data KD will be described.

  FIG. 23 is an explanatory diagram showing an example of the data structure of the measurement circuit data KD. In FIG. 23, the measurement circuit data KD includes measurement circuit instance data MI, a core description CA, and a top-level description MH. The top-level description MH is, for example, a description for instantiating a measurement circuit in a simulation environment.

  The measurement circuit instance data MI is, for example, a description for instantiating a core included in the measurement circuit in the simulation environment. In the measurement circuit instance data MI, the signal of hierarchical reference is resolved. The core description CA is a description related to the core included in the measurement circuit. Here, specific examples of the measurement circuit instance data MI and the top-level description MH will be described.

  FIG. 24 is an explanatory diagram of a specific example of the measurement circuit instance data MI. In FIG. 24, the measurement circuit instance data MI describes, for example, the maximum value of the section to be sampled and the number of cycles that should be allowed by specifying the sampling period. Also included is a description in which the module name at the head of the signal name of the measurement point determined by the measurement circuit plan MP is replaced with a path to the top module, and a value corresponding to the set value is assigned to the measurement component.

  FIG. 25 is an explanatory diagram of a specific example of the top-level description MH. In FIG. 25, a top-level description MH is a description for instantiating a measurement circuit that is instantiated by an RTL test bench.

  Thus, based on the measurement circuit plan MP, the connection between the cell instance and the hierarchy reference is performed, and the parameter values of the bundle_position_counter, RAM, BUS, and controller are determined by the set values.

  In addition, when the difference circuit is created, the measurement circuit creation unit 304 adds the created difference circuit to the created difference circuit based on the clock tree observation signal / port number relation table CP and the non-clock tree observation signal / port number relation table NCP. At the same time, the measurement circuit data KD is corrected.

  For example, the reference destination of the measurement circuit data KD is a signal of the net list NL for power estimation. Therefore, for example, the measurement circuit creation unit 304 converts “TOP.A.B.s0” into “testbench.target.A.B.s0”, and “testbench.target.A” in the measurement circuit data KD. .B.s0 ”is replaced with“ testbench.diff_circuit.inst.out_data [0] ”.

  Similarly, the measurement circuit creation unit 304 obtains “testbench.target.AB.s10”, which is a replacement character string, from “TOP.A.B.s10”, and “testbench.target” in the measurement circuit data KD. .A.B.s10 ”is replaced with“ testbench.diff_circuit.inst.out_data [1] ”. Thereby, measurement circuit data KD can be corrected according to a difference circuit.

  Finally, the measurement circuit creation unit 304 updates the measurement circuit plan MP by adding information about the measurement circuit to the measurement circuit plan MP. Here, an example of updating the measurement circuit plan MP will be described.

  FIG. 26 is an explanatory diagram of an example of updating the measurement circuit plan MP. In FIG. 26, the measurement circuit plan MP is the updated measurement circuit plan MP to which information on the measurement circuit (the underlined portion in FIG. 26) is added. In the drawing, a part of the measurement circuit plan MP is extracted and displayed.

  For the creation of the measurement circuit, for example, JP-A-2007-102337 can be referred to. Further, when the logic simulation is executed by the software simulator, the bus and the RAM in the measurement circuit are not necessary. In addition, the measurement circuit creation unit 304 may reduce the circuit amount of the measurement circuit by using a grouping circuit. For the reduction of the measurement circuit amount using the grouping circuit, for example, JP-A-2009-053747 can be referred to. Here, a specific example of the measurement circuit will be described.

  27 and 28 are explanatory diagrams illustrating circuit configuration examples of the measurement circuit. In FIG. 27, a measurement circuit 2701 is a circuit that measures the number of times the signal value of the observation signal has changed when a difference circuit between the RTL design data RD and the netlist NL is not created. The circuit to be evaluated 2702 represents a target circuit for which power consumption is to be estimated.

  The measurement circuit 2701 has a common controller for controlling each core, and each core has a RAM for holding data and a bus for writing data to the RAM. The Counter sends the address of the measurement value Max value −1 that can be connected to the bus from 0 and the time. As a result, the value of the register that holds the data to be written to the bus in the bundle_position_counter is transferred.

  The core and the core element in the measurement circuit plan MP indicate a collection of signals connected to the bundle_position_counter in the measurement circuit 2701.

  In FIG. 28, a measurement circuit 2801 is a circuit that measures the number of times the signal value of the observation signal has changed when a difference circuit between the RTL design data RD and the netlist NL is created. The difference circuit instance circuit 2802 is a circuit in which the difference circuit is instantiated. The circuit to be evaluated 2803 represents a target circuit for which power consumption is to be estimated.

(Specific examples of dynamic statistical data ER)
FIG. 29 is an explanatory diagram of a specific example of the dynamic statistical data ER. In FIG. 29, the dynamic statistical data ER is dump data of a certain core that represents the execution result of the logic simulation. When the maximum number of core elements (CE) is set to “1024”, statistical data is stored for each memory address by 0 × 400 (= 1024).

  In the address, the result of the (address & (1024-1)) th CE is stored (address >> 10). In addition, 0x0 to 0x399 are invalid data because the initial value is written while the CE is calculating. In this way, the output value of any CE with any sampling can be extracted.

(Estimated power consumption)
FIG. 30 is an explanatory diagram illustrating an example of estimating the power consumption of the target circuit based on the dynamic statistical data ER. The power calculation unit 306 reads the power coefficient (unit cell) data PU, the memory terminal data MD, and the power coefficient (memory) data PM and converts them into a computer-processable data structure.

  Next, the power calculation unit 306 degenerates the power coefficient based on the power coefficient (unit cell) data PU, the memory terminal data MD, and the power coefficient (memory) data PM. Here, the degeneration is a process for obtaining a power coefficient for calculating power corresponding to the measurement range of the measurement circuit, using the total value of the power coefficients of the cells in the measurement circuit. Specifically, for example, the power calculation unit 306 degenerates a power coefficient for a clock tree, a power coefficient for a non-clock tree, and a power coefficient for a memory.

  Next, the power calculation unit 306 calculates the power consumption of the target circuit based on the calculation range ID map data ED, the measurement circuit plan MP, the power coefficient in the current calculation, and the dynamic statistical data ER. The power coefficient in the current calculation is a power coefficient after degeneration, for example, a power coefficient for a clock tree, a power coefficient for a non-clock tree, and a power coefficient for a memory.

  Then, the power calculation unit 306 dumps data via the power calculation result output I / F. At this time, the power calculation unit 306 drops two types of results for each calculation range ID, that is, a result obtained by exclusive aggregation in the calculation range and a result obtained by cumulative addition in the calculation range. As a result, it is possible to perform power calculation in accordance with the reduction in the number of measurement objects and reduce the number of calculations.

(Example of output of power estimation data PE)
Next, an output example of the power estimation data PE will be described with reference to FIGS. 31 to 33.

  FIG. 31 is an explanatory diagram (part 1) of an output example of the power estimation data PE. In FIG. 31, for each calculation range in the target circuit, the power estimation data PE is the sum of the power value of each calculation range, the power value of each calculation range, and the power value of the calculation range that is a descendant of the calculation range. This is information indicating the power value.

  Specifically, the first numerical value among the numerical values separated by commas in the power estimation data PE represents a power value of a combination cell, a CGIC, or the like constituting the clock tree. The second numerical value represents the power value of a non-flip-flop such as a combination cell. The third numerical value represents the power value of the clock terminal component of the flip-flop whose clock tree is connected to the clock terminal.

  The fourth numerical value represents the power value of the non-clock terminal component of the flip-flop whose clock tree is connected to the clock terminal. The fifth numerical value represents the power value of the flip-flop whose clock tree is not connected to the clock terminal. The sixth numerical value represents the power value of the RAM / ROM.

  FIG. 32 is an explanatory diagram (part 2) of an output example of the power estimation data PE. In FIG. 32, a waveform graph WG is a graph of the power estimation data PE shown in FIG. In FIG. 32, the vertical axis represents the power value, and the horizontal axis represents the sample ID. The sample ID is, for example, an identifier of a result at a predetermined interval (for example, 10 [μs]). The waveform graph WG is a graph in which the first to sixth numerical values of the power estimation data PE are stacked in order from the bottom to the top.

  FIG. 33 is an explanatory diagram (part 3) of an output example of the power estimation data PE. In FIG. 33, an estimation result list LT is a table showing power estimation results of commercially available tools A, B, C, and D that estimate gate-level power consumption. In FIG. 33, the waveform graph WG is an enlarged view of the vicinity of the waveform graph WG shown in FIG. 32 that is considered to be close to the power estimation (9.26 [μs]) based on the waveform data of the estimation result list LT. is there.

  According to the waveform graph WG, it can be seen that the clock tree power and the clock tree partial power of the flip-flop power are relatively in good agreement with the power estimation results of other tools. It can also be seen that the RAM / ROM has an error of about 5 [%] with other tools that perform calculations that reduce the accuracy because the calculation is broken. In addition, regarding the non-clock tree part, the average is 68 [mW] for the non-flip flop and 23.5 [mW] for the non-flip flop, which is about 92 [mW] in total. It is close to the value.

(Power estimation processing procedure of power estimation apparatus 200)
Next, the power estimation processing procedure of the power estimation apparatus 200 will be described.

  FIG. 34 is a flowchart illustrating an example of a power estimation processing procedure of the power estimation apparatus 200. In the flowchart of FIG. 34, first, the power estimation apparatus 200 determines whether or not the RTL design data RD and the netlist NL of the target circuit have been acquired (step S3401).

  Here, the power estimation apparatus 200 waits to acquire the RTL design data RD and the netlist NL (step S3401: No). When the power estimation apparatus 200 acquires the RTL design data RD and the netlist NL (step S3401: Yes), the power estimation apparatus 200 sets the correspondence relationship between the signals indicating the same signal line between the RTL design data RD and the netlist NL. The mapping data MD to represent is created (step S3402).

  Next, the power estimation apparatus 200 executes basic data generation processing for generating basic data based on the mapping data MD, the power estimation setting data ST, the technology library TLB, the clock source starting point data CS, and the wiring capacity data WD. (Step S3403). A specific processing procedure of the basic data creation processing will be described later with reference to FIG.

  Then, the power estimation apparatus 200 creates a measurement circuit that measures the number of times the signal value of the observation signal has changed based on the measurement circuit plan MP (step S3404). Next, the power estimation apparatus 200 mounts the created difference circuit and measurement circuit on an RTL test bench, and executes a logic simulation of the target circuit based on the RTL design data RD (step S3405). As a result, it is possible to extract a power parameter necessary for estimating the power consumption of the target circuit.

  Next, the power estimation apparatus 200 calculates the power consumption of the target circuit based on the dynamic statistical data ER representing the execution result of the logic simulation including the measurement result obtained by measuring the change in the signal value of the observation signal (step S3406). ). Then, the power estimation apparatus 200 outputs the power estimation data PE that represents the calculation result of the calculated power consumption of the target circuit (step S3407), and ends the series of processes according to this flowchart. Thereby, the power consumption of the target circuit can be estimated.

  Next, a specific processing procedure of the basic data creation processing in step S3403 shown in FIG. 34 will be described.

  FIG. 35 is a flowchart illustrating an example of a specific processing procedure of basic data creation processing. In the flowchart of FIG. 35, first, the power estimation apparatus 200 creates the clock starting point data CKD and the clock starting point parent-child relationship data FD by performing a clock tree analysis based on the netlist NL and the clock source starting point data CS (step) S3501).

  Next, the power estimation apparatus 200 creates calculation range ID map data ED by designating the calculation range on the target circuit (step S3502). Then, the power estimation apparatus 200 creates memory terminal data MD by extracting RAM / ROM from the netlist NL (step S3503).

  Next, the power estimation apparatus 200 creates non-clock tree observation point data OD by randomly selecting a signal having a ratio r among non-clock tree signals from the netlist NL (step S3504). Then, the power estimation apparatus 200 creates the power coefficient (unit cell) data PU and the power coefficient (memory) data PM by calculating the power coefficient of the unit cell and the memory in the target circuit (step S3505).

  Next, the power estimation apparatus 200 refers to the mapping data MD and identifies the signal name of the signal corresponding to the signal name of the signal on the RTL design data RD among the signal names of the signals on the netlist NL ( Step S3506). Then, the power estimation apparatus 200 selects a signal to be an observation signal from the clock start point data CKD or the non-clock tree observation point data OD (step S3507).

  Next, the power estimation apparatus 200 outputs a signal having a signal name corresponding to the signal name of the signal on the RTL design data RD by sequentially following the subsequent cells from the cell outputting the observation signal on the netlist NL. A cell is detected (step S3508). Then, the power estimation apparatus 200 determines whether there is an unselected signal that is not selected from the clock starting point data CKD or the non-clock tree observation point data OD (step S3509).

  Here, when there is an unselected signal (step S3509: Yes), the power estimation apparatus 200 returns to step S3507 and has not yet been selected as an observation signal from the clock start point data CKD or the non-clock tree observation point data OD. Is selected (step S3507).

  On the other hand, when there is no unselected signal (step S3509: No), the power estimation apparatus 200 creates difference circuit data DF representing a difference circuit between the RTL design data RD and the netlist NL (step S3510). The power estimation apparatus 200 creates difference circuit configuration data DCG corresponding to the created difference circuit data DF (step S3511), and proceeds to step S3404 illustrated in FIG.

  Thereby, it is possible to create a differential circuit for extracting a power parameter necessary for estimating the power consumption of the target circuit.

  In the above description, the signal to be the observation signal is selected from the clock start point data CKD or the non-clock tree observation point data OD. However, the present invention is not limited to this. For example, the power estimation apparatus 200 may select a signal designated by a user operation input as an observation signal.

  As described above, according to the power estimation apparatus 200 according to the embodiment, the signal of the RTL design data RD is obtained by sequentially tracing the preceding cell from the first cell that outputs the observation signal on the netlist NL. A second cell to which a signal having a correspondence relationship is input can be detected. Further, according to the power estimation apparatus 200, the difference circuit representing the difference circuit between the RTL design data RD and the netlist NL is extracted by extracting the partial circuits from the second cell to the first cell from the netlist NL. Circuit data DF can be created.

  As a result, the waveform data of the observation signal output from the cells in the target circuit that have been detailed through logic synthesis and layout processes, that is, the difference for extracting the power parameters necessary for estimating the power consumption of the target circuit A circuit can be created.

  Further, according to the power estimation apparatus 200, the RTL is expressed by associating the signal name of the signal of the RTL design data RD having a correspondence relationship with the signal of the netlist NL input to the second cell and the second cell. A reference signal / port number relation table RP can be created. Thereby, it is possible to specify the correspondence between the port number of the input terminal of the difference circuit and the signal name of the signal on the RTL design data RD.

  Further, according to the power estimation apparatus 200, the observation signal / port number relationship table SP can be created in which the signal name of the selected observation signal is associated with the first cell that outputs the observation signal. Thereby, it is possible to specify the correspondence between the port number of the output terminal of the difference circuit and the signal name of the observation signal on the netlist NL.

  Further, according to the power estimation apparatus 200, a signal output from a cell that temporarily stops the supply of a clock signal to a supply destination can be selected as an observation signal from the netlist NL. This makes it possible to create a difference circuit for extracting waveform data of a signal output from a CGIC that is automatically inserted during logic synthesis or the like.

  Also, according to the power estimation apparatus 200, from the output terminals that can be traced from the clock source of the target circuit, the output terminals whose values per unit time at which the signal value of the output signal changes are different from each other. The output signal can be selected as an observation signal. As a result, a differential circuit for extracting the waveform data of the signal at the change point of the toggle rate necessary for estimating the power consumption can be created.

  Further, according to the power estimation apparatus 200, a signal output from any output terminal in the output terminal group that cannot be traced from the clock source of the target circuit can be selected as an observation signal. Specifically, for example, according to the power estimation apparatus 200, a signal having a ratio r can be randomly selected from non-clock tree signals. As a result, the non-clock tree signals can be thinned out, and the circuit amount of the difference circuit can be suppressed.

  Further, according to the power estimation apparatus 200, the RTL design data RD, the difference circuit data DF, and the measurement circuit data KD can be given to the RTL test bench to execute the logic simulation of the target circuit. For example, the power estimation apparatus 200 uses the RTL reference signal / port number relation table RP and the observation signal / port number relation table SP as the test bench with the RTL design data RD, the difference circuit data DF, and the measurement circuit data KD. Implement and run logic simulation. And the power estimation apparatus 200 can acquire the execution result of the logic simulation containing the measurement result which measured the change of the signal value of an observation signal.

  Thereby, the waveform data of the observation signal output from the difference circuit between the RTL design data RD and the netlist NL, that is, the power parameter necessary for estimating the power consumption of the target circuit can be extracted.

  Moreover, according to the power estimation apparatus 200, the power consumption of the target circuit can be estimated based on the execution result of the logic simulation including the measurement result obtained by measuring the change in the signal value of the observation signal. As a result, the power consumption of the target circuit can be estimated using the waveform data of the signal output from the cell added in the logic synthesis or layout process, which is difficult to estimate from the conventional RTL design data, and the estimation accuracy is improved. be able to.

  Thus, according to the power estimation apparatus 200, it is possible to estimate the power consumption with the same accuracy as the gate level using the RTL verification environment. Further, according to the power estimation apparatus 200, it is not necessary to construct a gate-level verification environment for performing functional verification of the target circuit, so that the workload of the verifier can be reduced and the verification period can be shortened. Can do.

  The power estimation support method described in this embodiment can be realized by executing a program prepared in advance on a computer such as a personal computer or a workstation. The power estimation support method program is recorded on a computer-readable recording medium such as a hard disk, a flexible disk, a CD-ROM, an MO, and a DVD, and is executed by being read from the recording medium by the computer. The power estimation support method program may be distributed via a network such as the Internet.

  The following additional notes are disclosed with respect to the embodiment described above.

(Supplementary note 1)
Obtain mapping information indicating the correspondence between the signal name of the net list of the target circuit to be estimated for power consumption and the signal name of the design information of the target circuit described in the register transfer level,
From the netlist, select an observation signal to be observed for signal value changes,
With reference to the acquired mapping information, the first cell that outputs the selected observation signal on the netlist is sequentially traced to the preceding cell as a starting point, thereby having a correspondence with the design information signal. Detect the second cell to which the netlist signal is input,
By extracting a partial circuit from the detected second cell to the first cell from the net list, difference circuit information representing a difference between the design information and the net list is created,
Creating signal information in which the signal name of the design information signal having a correspondence relationship with the signal of the net list input to the second cell is associated with the second cell;
The generated difference circuit information and the signal information are output in association with each other.
A power estimation support program characterized by causing processing to be executed.

(Supplementary note 2)
Executing a process of creating observation signal information representing the signal name of the observation signal and the first cell that outputs the observation signal in association with each other;
The output process is as follows:
The power estimation support program according to appendix 1, wherein the generated observation signal information, the difference circuit information, and the signal information are output in association with each other.

(Supplementary note 3) The process to be selected is
The power estimation support program according to appendix 2, wherein a signal output from a cell that temporarily stops supply of a clock signal to a supply destination is selected from the netlist as the observation signal.

(Supplementary note 4)
From the output terminal group in the netlist, to execute the process of extracting the output terminal group that can be traced from the clock source of the target circuit,
The process to select is
Note that, among the extracted output terminal groups, signals output from output terminals whose values per unit time at which the signal value of the output signal changes are different from each other are selected as the observation signals. The power estimation support program according to 2 or 3.

(Supplementary Note 5) The process to select is
(Supplementary note 4) wherein a signal output from any one of the remaining output terminal groups excluding the extracted output terminal group is selected as the observation signal among the output terminal groups in the netlist. The power estimation support program described.

(Appendix 6)
Determining whether the number of signals output from any output terminal of the remaining output terminal group selected as the observation signal is less than a threshold;
When the number of signals is determined to be less than the threshold, a signal output from any output terminal of the remaining output terminal group is selected as the observation signal.
The power estimation support program according to appendix 5, wherein the program is executed.

(Appendix 7)
Based on the signal information and the observed signal information, the design information and the difference circuit information are given to a test bench to perform a logic simulation of the target circuit, thereby changing the signal value of the observed signal. The execution result of the logic simulation including the measurement result obtained by measuring
Outputting the obtained execution result;
The power estimation support program according to any one of appendices 2 to 6, wherein the program is executed.

(Supplementary Note 8) An acquisition unit that acquires mapping information indicating a correspondence relationship between a signal name of a net list of a target circuit to be estimated for power consumption and a signal name of design information of the target circuit described in a register transfer level; ,
A selection unit for selecting an observation signal to be observed for a change in signal value from the netlist;
With reference to the mapping information acquired by the acquisition unit, by sequentially tracing the preceding cell starting from the first cell that outputs the selected observation signal on the netlist, the design information signal and A detection unit for detecting a second cell to which a signal of the netlist having a correspondence relationship is input;
By extracting a partial circuit from the second cell to the first cell detected by the detection unit from the net list, difference circuit information representing a difference between the design information and the net list is obtained. A first creation unit to be created;
A second creation unit that creates signal information in which the signal name of the design information signal having a correspondence relationship with the signal of the net list input to the second cell is associated with the second cell. When,
An output unit that associates and outputs the difference circuit information created by the first creation unit and the signal information created by the second creation unit;
A power estimation support apparatus comprising:

(Supplementary note 9)
Obtain mapping information indicating the correspondence between the signal name of the net list of the target circuit to be estimated for power consumption and the signal name of the design information of the target circuit described in the register transfer level,
From the netlist, select an observation signal to be observed for signal value changes,
With reference to the acquired mapping information, the first cell that outputs the selected observation signal on the netlist is sequentially traced to the preceding cell as a starting point, thereby having a correspondence with the design information signal. Detect the second cell to which the netlist signal is input,
By extracting a partial circuit from the detected second cell to the first cell from the net list, difference circuit information representing a difference between the design information and the net list is created,
Creating signal information in which the signal name of the design information signal having a correspondence relationship with the signal of the net list input to the second cell is associated with the second cell;
The generated difference circuit information and the signal information are output in association with each other.
A power estimation support method characterized by executing processing.

DESCRIPTION OF SYMBOLS 100 Power estimation support apparatus 200 Power estimation apparatus 301 Acquisition part 302 Mapping data creation part 303 Difference circuit creation part 304 Measurement circuit creation part 305 Execution part 306 Power calculation part 307 Output part

Claims (8)

On the computer,
Obtain mapping information indicating the correspondence between the signal name of the net list of the target circuit to be estimated for power consumption and the signal name of the design information of the target circuit described in the register transfer level,
From the netlist, select an observation signal to be observed for signal value changes,
With reference to the acquired mapping information, the first cell that outputs the selected observation signal on the netlist is sequentially traced to the preceding cell as a starting point, thereby having a correspondence with the design information signal. Detect the second cell to which the netlist signal is input,
By extracting a partial circuit from the detected second cell to the first cell from the net list, difference circuit information representing a difference between the design information and the net list is created,
Creating signal information in which the signal name of the design information signal having a correspondence relationship with the signal of the net list input to the second cell is associated with the second cell;
The generated difference circuit information and the signal information are output in association with each other.
A power estimation support program characterized by causing processing to be executed. In the computer,
Executing a process of creating observation signal information representing the signal name of the observation signal and the first cell that outputs the observation signal in association with each other;
The output process is as follows:
The power estimation support program according to claim 1, wherein the generated observation signal information, the difference circuit information, and the signal information are output in association with each other. The process to select is
The power estimation support program according to claim 2, wherein a signal output from a cell that temporarily stops supply of a clock signal to a supply destination is selected from the netlist as the observation signal. In the computer,
From the output terminal group in the netlist, to execute the process of extracting the output terminal group that can be traced from the clock source of the target circuit,
The process to select is
The signal output from the output terminal having a different number of times per unit time at which the signal value of the output signal changes is selected as the observation signal from the extracted output terminal group. Item 4. The power estimation support program according to Item 2 or 3. The process to select is
5. The signal output from any one of the remaining output terminal groups excluding the extracted output terminal group among the output terminal groups in the netlist is selected as the observation signal. Power estimation support program described in 1. In the computer,
Based on the signal information and the observed signal information, the design information and the difference circuit information are given to a test bench to perform a logic simulation of the target circuit, thereby changing the signal value of the observed signal. The execution result of the logic simulation including the measurement result obtained by measuring
Outputting the obtained execution result;
The power estimation support program according to any one of claims 2 to 5, wherein a process is executed. An acquisition unit for acquiring mapping information representing a correspondence relationship between a signal name of a net list of a target circuit to be estimated for power consumption and a signal name of design information of the target circuit described in a register transfer level;
A selection unit for selecting an observation signal to be observed for a change in signal value from the netlist;
With reference to the mapping information acquired by the acquisition unit, by sequentially tracing the preceding cell starting from the first cell that outputs the selected observation signal on the netlist, the design information signal and A detection unit for detecting a second cell to which a signal of the netlist having a correspondence relationship is input;
By extracting a partial circuit from the second cell to the first cell detected by the detection unit from the net list, difference circuit information representing a difference between the design information and the net list is obtained. A first creation unit to be created;
A second creation unit that creates signal information in which the signal name of the design information signal having a correspondence relationship with the signal of the net list input to the second cell is associated with the second cell. When,
An output unit that associates and outputs the difference circuit information created by the first creation unit and the signal information created by the second creation unit;
A power estimation support apparatus comprising: Computer
Obtain mapping information indicating the correspondence between the signal name of the net list of the target circuit to be estimated for power consumption and the signal name of the design information of the target circuit described in the register transfer level,
From the netlist, select an observation signal to be observed for signal value changes,
With reference to the acquired mapping information, the first cell that outputs the selected observation signal on the netlist is sequentially traced to the preceding cell as a starting point, thereby having a correspondence with the design information signal. Detect the second cell to which the netlist signal is input,
By extracting a partial circuit from the detected second cell to the first cell from the net list, difference circuit information representing a difference between the design information and the net list is created,
Creating signal information in which the signal name of the design information signal having a correspondence relationship with the signal of the net list input to the second cell is associated with the second cell;
The generated difference circuit information and the signal information are output in association with each other.
A power estimation support method characterized by executing processing.

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