JP2017135657A - Level shift circuit - Google Patents

Abstract

A level shift circuit for a crystal oscillator capable of achieving both low phase noise and low current consumption is provided. A level shifter unit 21 having a connection node between a first PMOS transistor P1 and a first NMOS transistor N1 as an output terminal, and a connection node between a first resistance element R1 and a second resistance element R2 as a bias voltage terminal. The gate of the transistor P1 and the gate of the second PMOS transistor P2 are connected based on the drain voltage of the transistor P2, and the gate of the transistor N1 and the second NMOS transistor N2 The gate is connected based on the drain voltage of the transistor N2, the output terminal is biased by the voltage of the bias voltage terminal, and an output oscillation signal level-shifted with respect to the input oscillation signal is obtained from the output terminal. [Selection] Figure 1

Description

  The present invention relates to a level shift circuit of a crystal oscillator that can achieve both low phase noise and low current consumption.

2. Description of the Related Art Conventionally, there are devices such as a digital temperature compensated crystal oscillator that have a plurality of constant voltage generation circuits and are effectively multi-power sources. In such a multi-power supply device, in order to transmit a signal from the low voltage side to the high voltage side, a level shifter is required unless the voltage difference is slight.
FIG. 4 shows an example of a conventional AC signal level shifter described in Patent Document 1. In FIG. This is because an AC signal on the low voltage side is input to one terminal of the DC cut capacitor 100, a DC component is removed, and the other terminal of the DC cut capacitor 100 is input to an inverter 300 that is operated by a power source on the high voltage side. In this configuration, the amplitude of the signal is raised to the level on the high voltage side by the amplification action of the inverter 300. In order to efficiently amplify a signal, an operating point as an amplifier must be located at a large amplification factor, that is, at the midpoint of the inverting operation region of the inverter 300. The output of the inverter 300 and the input of the inverter 300 Are connected by a feedback resistor 200 to ensure an operating point near the midpoint of the inversion operating region of the inverter 300.
Patent Document 1 is an improvement of the conventional example of FIG. 4 and discloses an AC signal level shifter that has no self-excited oscillation and has low power consumption by making the amplification factor of the inverter the minimum necessary margin. Yes.

JP-A-7-170167

In an MHz band one-chip crystal oscillation circuit, the oscillation unit is generally driven by a regulator of about 1 V lower than the power supply voltage for the purpose of reducing crystal current and current consumption. In the case of an oscillator with a CMOS clock output, it is necessary to level shift the crystal oscillation waveform to the waveform of the power supply voltage, and generally a level shifter using AC coupling is used (see FIG. 4).
However, the 1 / f noise near the inversion of the level shifter is superimposed on the output of the crystal oscillation, and the phase noise is deteriorated. In order to improve this, it is necessary to increase the size of the level shifter. However, as the level shifter is increased, the through current increases, so that there is a problem that it is difficult to achieve both low phase noise and low current consumption.
The present invention has been made under such circumstances, and provides a level shift circuit for a crystal oscillator that can achieve both low phase noise and low current consumption.

  The level shift circuit of the present invention has a first PMOS transistor and a first NMOS transistor in which current paths are connected in series between power supplies, and an input oscillation signal is supplied to the gate of the first PMOS transistor. The input oscillation signal is input to the gate of the first NMOS transistor via the second DC cut capacitor, and the first PMOS transistor and the first NMOS transistor are connected to each other. A level shifter unit having a connection node Z as an output terminal, and a second PMOS transistor, a first resistance element, a second resistance element, and a second NMOS transistor, in which current paths are connected in series between the power sources in order. A bias voltage generation circuit having a bias voltage terminal as a connection node between the first resistance element and the second resistance element. The gate of the first PMOS transistor and the gate of the second PMOS transistor are connected based on the drain voltage of the second PMOS transistor, and the gate of the first NMOS transistor and the gate of the second NMOS transistor are connected. The gate is connected based on the drain voltage of the second NMOS transistor, and the output terminal of the level shifter unit is biased by the voltage of the bias voltage terminal and level-shifted with respect to the input oscillation signal An output oscillation signal is obtained from the output terminal.

  The level shift circuit of the present invention can achieve both low phase noise and low current consumption by adding a circuit for limiting the through current. Therefore, the through current is reduced to the phase noise while maintaining the low phase noise. Superimposed 1 / f noise can be reduced.

FIG. 3 is a circuit diagram illustrating a level shift circuit according to the first embodiment. FIG. 2 is a waveform diagram illustrating changes in a signal flowing through the level shift circuit of FIG. 1. FIG. 6 is a circuit diagram illustrating a level shift circuit according to a second embodiment. The circuit diagram which shows the conventional level shift circuit.

The present invention is characterized by a level shift circuit of a crystal oscillator that can achieve both low phase noise and low current consumption by adding a circuit for limiting a through current.
Hereinafter, embodiments of the invention will be described with reference to examples.

A first embodiment will be described with reference to FIGS. 1 and 2.
FIG. 1 shows a crystal oscillator provided with a level shift circuit described in this embodiment. This crystal oscillator has an oscillating portion 1 and a level shift circuit 2 and is formed on a semiconductor substrate (not shown), and a crystal resonator 13 is externally attached to the semiconductor substrate.
The oscillating unit 1 includes an externally attached crystal resonator 13 and a resonator driving unit. The oscillator driving unit drives the crystal resonator 13 to output an oscillation signal to the level shift circuit 2. The vibrator driving unit includes an inverter 11 used as a vibrator driving circuit and a feedback resistor 12. For example, a constant voltage of 1 V, for example, is supplied to the inverter 11 from a regulator (REG) 14. A feedback resistor 12 is connected in parallel to both ends of the inverter 11 and a crystal resonator 13 is also connected in parallel. Then, both ends of the inverter 11, the feedback resistor 12 and the crystal resonator 13 are connected to the ground power supply terminal, and the ground voltage Vss is supplied to each of them. A predetermined voltage is supplied from the regulator 14 to the power supply terminal of the inverter 11, and the ground voltage Vss is supplied to the ground power supply terminal. The oscillation signal in the oscillating unit 1 is extracted from the output side of the inverter 11 and input to the level shift circuit 2. The level shift circuit 2 is supplied with a power supply voltage Vdd and a ground voltage Vss. The level shift circuit 2 converts the amplitude level of the oscillation signal from the oscillation unit 1 and outputs a pulse signal corresponding to the oscillation signal from the output terminal OUT as an output signal.

In the crystal oscillator having the above-described configuration, when a predetermined voltage is applied to the inverter 11 in the oscillation unit 1, the crystal resonator 13 is driven by the oscillation signal amplified by the inverter 11. At this time, the amplified oscillation signal is fed back to the input of the inverter 11 by the feedback resistor 12, and the oscillation is continued at a desired oscillation frequency. The level shift circuit 2 converts the oscillation signal into a pulse signal having an amplitude level corresponding to a voltage between the power supply voltage Vdd and the ground voltage Vss that is higher than the voltage supplied from the regulator 14, for example.

    The level shift circuit 2 includes a level shifter unit 21 and a bias voltage generation circuit 22. The level shifter unit 21 includes a first DC cut connected between the CMOS inverter including the first PMOS transistor P1 and the first NMOS transistor N1, and the output terminal of the oscillation unit 1 and the gate of the first PMOS transistor. The capacitor C1 includes a second DC cut capacitor C2 connected between the output terminal of the oscillation unit 1 and the gate of the first NMOS transistor. The bias generation circuit 22 includes a second PMOS transistor P2, a second NMOS transistor N2, a first resistance element R1, and a second resistance element R2.

  As shown in FIG. 1, in the level shifter unit 21, the source of the first PMOS transistor P1 is connected to the first power supply voltage Vdd, and the drain is connected to the drain of the first NMOS transistor N1. The source of the first NMOS transistor N1 is connected to the second power supply voltage (ground voltage) Vss. The first DC cut capacitor C1 has one electrode connected to the gate of the first PMOS transistor P1, and the other electrode connected to the input terminal (node a) IN of the level shift circuit 2. The second DC cut capacitor C2 has one electrode connected to the gate of the first NMOS transistor N1, and the other electrode connected to the input terminal (node a) IN of the level shift circuit 2. The input oscillation signal generated in the oscillating unit 1 is input to the level shift circuit 2 via the node a.

  The input oscillation signal input from the oscillating unit 1 is input to the gate of the first PMOS transistor P1 via the first DC cut capacitor C1, and the second DC cut is input to the gate of the first NMOS transistor N1. It is input via the capacitor C2. An output oscillation signal is output using the connection node between the first PMOS transistor P1 and the first NMOS transistor N1 as the output terminal OUT of the CMOS inverter constituting the level shifter section.

    In the bias voltage generation circuit 22, the source of the second PMOS transistor P2 is connected to the first power supply voltage Vdd, the drain is connected to one end of the first resistance element R1, and the other end of the first resistance element R1 is connected to the other end. The second resistance element R2 is connected to one end, and the other end of the second resistance element R2 is connected to the drain of the second NMOS transistor N2. The source of the second NMOS transistor N2 is connected to the second power supply voltage (ground voltage) Vss. The gates and drains of the second PMOS transistor P2 and the second NMOS transistor are connected to each other. The gate of the second PMOS transistor P2 is connected to the gate of the first PMOS transistor P1 through the resistance element R3. The gate of the second NMOS transistor N2 is connected to the gate of the first NMOS transistor N1 through the resistance element R4.

The output terminal of the CMOS inverter constituting the level shifter unit 21 is biased by the voltage of the bias voltage terminal of the bias voltage generation circuit 22, and the output oscillation signal level-shifted with respect to the input oscillation signal is output to the output terminal. It can be obtained from OUT.
FIG. 2 is a waveform diagram showing waveforms at the respective nodes of the level shift circuit constituting the crystal oscillator described in FIG.
When an oscillation signal having an amplitude level of 1.0 V generated and output from the oscillation unit is input to the input terminal (node a) IN of the level shift circuit 2, the alternating current of the oscillation signal is passed through the DC cut capacitor C1. The component flows to the gate node b of the PMOS transistor P1, and the AC component of the oscillation signal flows to the gate node c of the NMOS transistor N1 via the DC cut capacitor C2.

At the same time, a bias voltage based on the drain voltage is added from the PMOS transistor P2 of the bias voltage generating circuit 22 to the node b of the PMOS transistor P1, and an oscillation signal centered on this bias voltage is generated (FIG. 2B). ) Solid line waveform). A bias voltage based on the drain voltage is added to the node c of the NMOS transistor N1 from the NMOS transistor N2 of the bias voltage generation circuit 22, and an oscillation signal centered on the bias voltage is generated (FIG. 2B). ) Dashed waveform). Therefore, at the node b, for example, a signal having an amplitude of 0.6V centered at about 2.7V appears, and at the node c, a signal having an amplitude of 0.6V centered at about 0.6V appears.
The output terminal OUT is a connection node between the first PMOS transistor P1 and the first NMOS transistor N1 in the level shifter unit 21, and is connected to a voltage at a connection point between the first resistance element R1 and the second resistance element R2. Based on this bias, an output signal centered on this bias voltage is obtained (waveform in FIG. 2C). In this embodiment, for example, since the power supply voltage Vdd is 3.3 V, a signal having an amplitude of 3.3 V is output from the output terminal OUT.

In this embodiment, the transistor size of the second PMOS transistor P2 is smaller than the transistor size of the first PMOS transistor P1, and the transistor size of the second NMOS transistor N2 is the transistor size of the first NMOS transistor N1. It is made smaller.
In a level shift circuit incorporated in a conventional crystal oscillator, 1 / f noise in the vicinity of inversion is superimposed on the output of the crystal oscillation and phase noise is deteriorated. In order to improve this, it is necessary to increase the size of the level shifter. However, as the level shifter increases, the through current increases, and it is difficult to achieve both low phase noise and low current consumption. Therefore, in this embodiment, the transistor size (area) of the bias voltage generating circuit constituting the level shift circuit is made smaller than the transistor size of the level shifter section.
The level shifter unit is configured to have a current mirror relationship with the bias voltage generation circuit. A bias voltage that restricts a through current in the level shifter unit is applied to the gate of each transistor of the level shifter unit from the bias voltage generation circuit. Is given. With such a configuration, the through current can be reduced even if the buffer size is increased. Further, feedback is applied from the output node of the bias voltage generating circuit so that the output node (output OUT) of the level shifter unit is biased to around 50% of the power supply voltage Vdd as in the case of normal AC coupling. As a result, an oscillation signal centered on the amplitude of this bias voltage can always be obtained from the output node (output OUT) of the level shifter section. In other words, in the absence of the bias, due to transistor size manufacturing error, the duty of the oscillation signal appearing at the output OUT may be shifted, or the oscillation signal may not be obtained and the power supply voltage or the ground voltage may be stuck. In the present invention, this can be prevented.
In this embodiment, the voltage generated at the bias voltage terminal, which is the connection node between the first resistance element R1 and the second resistance element R2, is the same voltage as the intermediate voltage of the input oscillation signal (see FIG. 2).

As described above, the first embodiment can achieve both low phase noise and low current consumption by adding a circuit for limiting the through current. Therefore, the through current is reduced and superimposed on the phase noise while maintaining the low phase noise. 1 / f noise can be reduced.

Next, Embodiment 2 will be described with reference to FIG. In this embodiment, the connection node (output terminal) between the first PMOS transistor P1 and the first NMOS transistor N1 and the connection between the first resistance element R1 and the second resistance element R2 are compared with the form of the first embodiment. It is characterized in that a resistor is inserted between the node (bias voltage terminal).
Also in the circuit of the first embodiment, the voltage at the connection node (output terminal) of the first PMOS transistor P1 and the first NMOS transistor N1 which are output terminals is applied to the node b and the node c which are inputs of the level shift circuit 2. Although there is a return path, the resistance element R5 is inserted into the return path. Then, by adjusting the size of the resistance element R5, that is, the gain (reducing the feedback amount), the change of the input bias becomes insensitive to the voltage change of the output (OUT), and the circuit prevents unnecessary oscillation. Can be stabilized.
As described above, in the second embodiment, in addition to the above-described effects, low phase noise and low current consumption can be made compatible by adding a circuit that limits the through current. The 1 / f noise superimposed on the phase noise can be reduced by reducing the current.

DESCRIPTION OF SYMBOLS 1 ... Oscillation part 2 ... Level shift circuit 11 ... Inverter 12 ... Feedback resistor 13 ... Crystal oscillator 14 ... Regulator 21 ... Level shifter part 22 ... Bias voltage generation circuit

Claims (2)

A first PMOS transistor and a first NMOS transistor, each having a current path connected in series between power supplies, have an input oscillation signal input to the gate of the first PMOS transistor via a first DC cut capacitor. The input oscillation signal is inputted to the gate of the first NMOS transistor via a second DC cut capacitor, and a level shifter having a connection node between the first PMOS transistor and the first NMOS transistor as an output terminal. And a second PMOS transistor, a first resistance element, a second resistance element, and a second NMOS transistor, in which current paths are connected in series between the power supplies in order, the first resistance element, A bias voltage generation circuit having a connection node of the second resistance element as a bias voltage terminal, and the first PMOS transistor And the gate of the second PMOS transistor are biased based on the drain voltage of the second PMOS transistor, and the gate of the first NMOS transistor and the gate of the second NMOS transistor are The output terminal is biased based on a drain voltage of an NMOS transistor, and the output terminal is biased by the voltage of the bias voltage terminal, and an output oscillation signal level-shifted with respect to the input oscillation signal is obtained from the output terminal. A level shift circuit characterized by the above. A resistor is inserted between the connection node of the first PMOS transistor and the first NMOS transistor and between the connection node of the first resistance element and the second resistance element. Item 2. The level shift circuit according to Item 1.

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