JP2020519324A - Analog-to-analog current/voltage conversion electronics for biomedical optical imaging systems - Google Patents

Abstract

The present invention relates to the electronics of analog current/voltage converters used in biomedical optical imaging systems. The present invention is particularly applicable to biomedical optical coupling of electro-optical cable fibers to voltage values of the amount of current flowing through a pn-type semiconductor photodiode connected to the optical fiber cable for the biomedical optical imaging system to read light intensity information from the optical fiber cable. It relates to the whole circuit with an electronic analog current/voltage converter in terms of converting the amount of pn-type semiconductor electron current of the image system.
[Selection diagram] Fig. 3

Description

Technical field and background technology

Biomedical DOT devices continue to propagate in tissue after entering a light source position in any type of tissue, and laser photons that cause the formation of trajectories in the tissue during progression are detected at specific detector positions. A circuit for collecting from and electrically measuring the collected photons, and a medical imaging device that also allows the circuit to be converted to an image by an imaging algorithm or method after being used appropriately.

In diffuse optical tomography (DOT) systems, electronic circuits are used that convert the photodiode current measured based on the input photodiode into a voltage value. In addition to general use, this electronic circuit may also be found in the electronic components of the DOT system data acquisition component for special purposes. The electronic circuit is used to convert the photons falling on the input photodiode into a current immediately after being converted into a current via the semiconductor electronic photodiode. Accordingly, the electronic circuit described above has a depletion space charge zone between p-type (hole density) and n-type (electron density) zones at a pn-type junction in a semiconductor photodiode, and p-type and n-type. It converts the currents carried by the minority and majority current carriers in the body zone of the to a voltage value.

In the state of the art, there are all circuits with analog current inputs and voltage outputs used in this field. Burr Brown and Texas Instruments DDC232 "32 channels, current input, whole analog-digital conversion circuit", DDC101 "20 bits, whole analog-digital conversion circuit", DDC112 "Double current input 20 bits, whole analog-digital conversion circuit" DDC114 "quad current input 20-bit analog-digital conversion circuit", DDC118 "oct current input 20-bit analog-digital conversion circuit" and DDC316 "16 channels, current input, analog-digital conversion circuit" are all circuits. Can be given as an example.

The following patents also relate to prior art in the art.
US Pat. No. 5,841,310 entitled "Current-voltage integrator to analog-to-digital converter and method relating thereto". US Pat. Patent publication entitled "Control system" WO19980457798 "Current-voltage integrator for analog-digital converter" Patent publication US5841310 "Current-voltage integrator for analog-digital converter and method thereof" Patent publication EP 0974119 entitled "Current-voltage integrator for analog-to-digital converter" Patent publication US 5103230 "Precision digitized current integration and measurement circuit" Patent publication US 5703589 "Delta sigma modulation" CAPACITOR INPUT SAMPLING CIRCUIT AND METHOD FOR EQUIPMENT"

In the DDC series described above, the switching mode of the input current is not taken into consideration in both products of the built-in receiver and the analog-digital converter (ADC). Although the input current is said to come from the control circuit, there is no detailed information on how the input current switches. The technique states that the current/voltage cycle timing is at least 330 microseconds. On the other hand, no research has been conducted to shorten the integration timing. There is only a temporal pulse diagram in this regard. In the normal state, the pulse is supplied from the pulse generating circuit. The generation of pulses and the transmission to the analog circuit block according to a certain synchronization can be performed using digitally controlled timing circuits. It is necessary to incorporate a kind of virtual microcontroller into the digital block, control the timing at the same time, and generate a rectangular pulse signal. The subject of timing generation is not mentioned in the prior art.

State-of-the-art is able to realize phase timing delays of the switching transistors, which are specific to this task and integrate in a very complex digital/time (“digital to time converter”-DTC) circuit. However, in this case, the circuit becomes even more complex, and with it the noise from the capacitor switching (“switching capacitance”) increases. Active electronic filter circuits need to be placed to prevent them.

Minimum Timing of DTC Circuit "A High-Linearity Digital-to-Time Converter Technique: Constant-Slope Charging", IEEE Journal of Solid-State 6th Volume, No. 6, Vol. 20, No. 6, Vol. 20, pp. 50. Has been done. Using the method in this study, it may be possible to design and implement a switching circuit that can integrate over a 100 femtosecond timing range. However, for example, a low noise buffer (“Low Noise Buffer”-LNB), a ramp generator (“ramp generator”), and a digital/analog converter (“Digital to Analog Converter”-DAC) may be used just to make a timing circuit. , A phase-locked loop (“Phased Lock Loop”-PLL) and other complicated circuits need to be designed, a schematic diagram and drawn in series. This criterion is used as the origin, design of the DTC circuit, switch CMOS transistor to perform the switching operation of the integrating capacitance of the standard integrating receiver, through proper use of the DTC timing circuit through imming marks coming from the DTC timing circuit. obtain. However, this also increases both circuit complexity and electrical noise. Another point of view is that the current timing cannot be lowered to a value that can distinguish the tissue type.

As mentioned above, in the prior art solution, the digital control signal value of the switching transistor, which enables the charging of a predetermined voltage value and the discharging of the current through the photodiode current, is performed by switching the integrating capacitance. Design of the digital floor of a digital/time (“digital-to-time converter-DTC” building block that is brought from a microcontroller to provide the timing of digitally controlled electronics and a large integrated circuit (“Very Large Scale Integration”). It becomes possible by embedding it in "Circuits"-VLSI).

In summary, when designing and analyzing new digital timing circuit blocks, they must be implemented within existing integrating receiver circuits to ensure electrical integrity between the circuit blocks. As described above, designing these circuit blocks and arranging them in the entire circuit imposes an even greater burden. These structurally increase the circuit complexity, increase the electrical noise of the circuit, and it is necessary to design and arrange electrical active filters in the circuit to prevent the increase of this electrical noise. The largest contributor to electrical noise is the noise associated with switching the capacitance of the integration through the transistor (“capacitive switching”).

After all, the timing circuit of the present technology is very expensive, no less than 100 femtoseconds. Therefore, whether a DTC circuit has been designed and manufactured, current/voltage conversion integration performed, or used for successive measurements during this period, tissue types with different absorption and scattering coefficients can be distinguished by existing techniques. It is impossible to do.

Therefore, the need for new methods in existing technology is gradually increasing.

Based on the above, it is an object of the present invention to achieve tissue type discrimination in a diffuse optical tomography (DOT) system, which is one of the biomedical optical imaging system methods.

Another object of the invention is to reduce the timing of the current/voltage integration cycle in all circuits of analog current-voltage converters far below the existing values.

Another object of the invention is to eliminate digital control circuits such as DTCs in analog current-voltage converter circuits.

The novelty of the present invention can be explained as follows. Timing delay, that is, the time of the process that flows through the photodiode whose input is a reference voltage generated above the capacity for performing the integration process, is the time when the integration process is switched. Type metal oxide silicon) MOSFET (“Metal-Oxide Silicon Field Effect Transistor”) and the gate (“gate”) of the transistor are caused by different metal or polysilicon connection lengths. It is realized by

For example, a difference in length of a 20 micrometer metal or polysilicon line leads to a timing difference of about 100 femtoseconds. A 1 micrometer length difference results in a timing delay of approximately 5 femtoseconds. Microcontroller control circuit of two CMOS transistors in charge of circuit integration process The voltage delay signal introduced at the same time is introduced to the gate (“gate”) port due to the difference in the length of the control circuit to obtain a desired time delay. Is obtained.

Fig. 7 shows a probability function of collecting photons sent from a light source position into a tissue from a tissue surface at a detector position. 1 illustrates a representative diagram for a diffuse optical tomography (TRDOT) system operating in the time zone. A transmission line delay circuit and a switch are shown. The figure of a switch is shown. It is an integrating receiver circuit diagram. The transistor-level internal structure of an operational amplifier is shown. FIG. 6 is a circuit diagram for an embodiment that includes a low pass filter of an operational amplifier.

In this detailed description, the invention is illustrated by the embodiments which do not constitute any limiting effect on a better understanding of the subject matter.

Thus, the present invention allows for tissue type discrimination, especially in diffuse optical tomography (DOT) systems, which is one of the biomedical optical imaging methods. The entire circuit described in the present invention and intended for use in the electronic data acquisition portion of the DOT system can be integrated in femtoseconds and lower timing.

Therefore, for example, even if a line difference having a length of 1 μm is created by a transmission line delay circuit, a timing of about 5 femtoseconds can be realized by the difference in the transmission line. A 1 micrometer metal transmission line has a channel length of 100 times the value of 10 nanometers, assuming that the current technology has a channel length of 10 nanometers. That is, even a 1-micron transmission line can be designed and easily inserted into the layout drawing chip to make it even longer. That is, it is possible to draw a smaller transmission line, and therefore, the integration timing can fall below the femtosecond value.

In FIG. 1, a function of the probability of collecting photons transmitted from the light source surface (20) into the surface of the tissue (10) at the detector location (30) is shown. Depending on the optical properties of the tissue, the number of photons collected at the detector location at different integration timings, ie the light intensity values when measured with a photodiode, will be different. For one tissue type, the light intensity value measured at the t1 integration time was 11, and for another tissue type it was I2. When the values of the photodiode current measured one after another with very short integration time delays for different tissue types are formulated, the tissue type characteristics can be estimated.

One of the questions that comes to mind is why we want to move to a very small integration timing. A large number of very small integral timing measurements made in series characteristically give an idea about tissue type, but measurements with larger timing periods do not provide detailed information.

When a laser photon is transmitted as a rectangular pulse signal for (20) picoseconds from the light source position over a period of time, as shown in FIG. 2, the physical of the voltage signal generated by the photon collected by the detector (30). The image is also a sudden high signal, as shown in FIG. 2, and immediately in the form of an exponentially decreasing image. High levels are formed first by surface photons, then by deeper photons, and then by deeper photons, thus providing an exponentially decreasing image.

This system is named in the literature as time domain diffuse optical tomography ("Time Resolved Diffuse Optical Tomography"-TRDOT). TRDOT devices operating in the time domain are expensive to build and test. Laboratory conditions such as a dark room are required for photon multiplexer tubes, optical mirrors, polarizers, lenses, and optical tables that are sensitive to even a single photon. In addition to being very expensive to implement, it is also difficult to implement and use.

The present invention provides an electronic circuit that enables the same operation of an expensive TRDOT system in a single chip that requires a photomultiplier tube that is sensitive to a dark room and a single photon under laboratory conditions. introduce. Therefore, the switching of the input photodiode current to the circuit can be done in a very short period of time and the work of TRDOT is accomplished. It also plots an exponentially decreasing photovoltage graph when it is collected at the detector position after rectangular pulsed photovoltage photons transmitted from the source position into the tissue continue to propagate through the tissue, and generate this graph. The measurements can be made by the microelectronic switching system according to the invention which is fast enough to Otherwise, if the input current switching system is not fast enough, the exponentially decreasing signal at the detector position cannot be measured. For this reason, the present invention focuses on switching the input current across the analog integrating receiver circuit and attempts to increase the speed to the maximum speed possible.

Given the behavior of the circuit, increasing the switching speed is also independent of the technology used, and the time delay circuit was thought to utilize different lengths of metal or polysilicon lines, and was implemented accordingly. is there.

3 and 4 explain the operating principle of the designed circuit. In a general sense, in the designed circuit, the integration with the integrating receiver circuit (80) provided at the circuit output is achieved by the transmission line delay circuit (40) activating and deactivating the switching transistors. Has been done. The transmission line delay circuit (40) includes a switching circuit (50) and metal lines L1 and L2. While the switching circuit (50) is generating the pulse voltage to the trigger used to open and close the switch, the transmission lines L1, L2 are the time difference due to the difference in length of the transmission lines L1 and L2. Due to the difference in the lengths of the L1 and L2 metal wires, as soon as a voltage pulse reaches the normally open (NA) switch (60) at the end of the L1 wire in FIG. There is no pulse signal at and therefore the switch (70), which is normally closed (NK), remains closed. The integration process is performed until the pulse input reaching the end of L2 caused by the delay in the transmission line opens the NK switch (70). The pulse input NK switch (70) then opens the circuit and the integration process ends.

In the embodiment of FIG. 5, the overall electronic circuit for the present invention includes the entire circuit (90) of the n-channel and p-channel MOSFET transistors, the integrating capacitance (Cint) and the OPAMP operational amplifier. Referring to FIG. 6, six MOSFETs (2p channel MOSFET and 4n channel MOSFET transistor) and one passive resistance element are arranged in the entire operational amplification circuit (90), and the entire operational amplification circuit (90) is a system of all systems. At the core, and in the center, there is a differential amplifier circuit (100). The differential amplifier circuit (100) is composed of four transistors (M7, M8, M9, M10), and is arranged inside the circuit. The MOSFET transistors of M7, M8, M9, M10 are part of amplifying the small voltage difference at the input of the amplifier (100) and transferring them to the output. The current source (110) of the differential amplifier is composed of M11 and M12 n-channel MOSFET transistors connected by a current mirror (“current mirror”) method. The body of all n-channel MOSFET transistors (“substrate”) has the lowest voltage level of “ground” in the whole circuit, and the body of all p-channel MOSFET transistors (“substrate”) has the highest voltage level of Of VDD (DC voltage of 1 volt DC).

The rightmost transistor M1 of the circuit of FIG. 5 supplies the 1 volt DC voltage required for the circuit. The M1 p-channel MOSFET transistor M1 is now synchronous circuit switched so that the 1VDC, Vref reference voltage values match the operating system. The φref pulse signal provides the gate (“gate”) end trigger of the M1 transistor switch. The P-channel M1 transistor source terminal (“source”) is connected to the Vref port, and the pulse signal input of Φref is connected to the gate terminal. Normally, when the high voltage level Φref voltage of logic 1 is triggered down to logic 0, it closes the circuit of the normally open (NA) M1 transistor. For this purpose, the Vref reference voltage of 1 VDC connected to the source terminal of the M1 transistor at the right end of FIG. 5 is provided at the + terminal of the integral capacitance (capacitor) of Cinti. The gate ends of the M5 and M6 p-channel MOSFET transistors are also represented by the Φwait1 and Φwait2 pulse signals. When the M2 p-channel MOSFET transistor also closes its circuit, the Cint capacitance fills the Cint integral capacitance via the current path taken through the M1, M5, and M2 transistors, and reaches a 1 VDC voltage value.

The satisfaction of the Cint integral capacity can be summarized as follows. The normally open (NA) M1 transistor is turned off, the NA M6 transistor remains NA, and the positive end of the Cint capacitor reaches the positive Vref voltage value of 1 VDC. At the same time, the M5 p-channel MOSFET transistor with NA is also turned off, the -M2 transistor of NA is turned off, and the negative end of the Cint capacitance also reaches ground ("ground") level. Immediately afterwards, continue with the M6 transistor NA, which was already NA, and turn on the closed M5 transistor in the previous step, thus flushing both the + and-terminals of the Cint capacitor to this new state (" floating point) At that point the Cint capacitor is set to a reference voltage of 1 VDC.

The next step in the integration, or current/voltage conversion process, is to close the MS transistor and trigger it by turning the ΦINT2 gate (“gate”) input logic 1 high on the n-channel M4 transistor that is NA, turning it off. Set to ON (set to ON). While ΦINT1 is at the voltage value of logic 0 at the gate (“gate”) end and the voltage value of the source gate (“source-gate”) is 0 volt at the beginning, that is, in the normally closed (NK) weak inversion mode. In the M3 transistor reversely connected to the circuit, the voltage pulse of -1 is given only for a short time after the M4 transistor is immediately turned off at the gate end of ΦINT1. Thus, in weak inversion mode, the current through the p-channel M3 transistor, which is reverse connected to the circuit, is cut off and the circuit suddenly opens.

Then, during this period, that is, the period from when the M4 transistor closes the circuit until when the M3 transistor opens, the Cint integral capacitance is derived from the input due to the difference in the period when the current starts to flow from the photodiode at the left end and is immediately interrupted. The integrated photodiode current is integrated into a voltage value. Summarizing the integral current/voltage conversion process, the M1, M2, and M6 transistors remain open. First, in the transistor of M5 and M4, the Cint capacitance integrates the current drawn by the photodiode from the circuit into a voltage value during a very short period before opening the circuit, and the voltage equivalent to the integrated voltage value is converted. ..

In FIG. 7 one can see the switching transistor, a 6 Ghz low pass RC filter placed at the input of the switch to eliminate the integrating capacitance and switching noise.

10... Organization, 20... Light source position, 30... Detector position, 40... Transmission line delay circuit, 50... Switching circuit, 60... Normally open (NA) switch, 70... Normally closed (NK) switch, 80... Integral receiver Blocks, 90... Overall operational amplifier circuit, 100... Differential amplifier circuit, 110... Current source.

Claims (4)

A current source as described above for a biomedical optical imaging system including a current source (110) that produces a current for a photon transmitted from a light source location (20) to a tissue surface (10) and collected at a detector location (30). An electronic circuit of an analog current to voltage converter including an integrating receiver circuit (80) for making electrical contact with (110),
A normally open (NA) switch (60) for supplying a current from the current source (110) to the integrating receiver circuit (80) when closed, and a receiver circuit (80) from the current source (110) when opened. ) To transmit a trigger signal of the normally closed (NK) switch (70), the normally open (NA) switch (60) and the normally closed (NK) switch (70) for interrupting the current flow to If the configured switching circuit (50) secures signal transmission between the normally open (NA) switch (60) and the switching circuit (50), the L1 line and the normally closed (NC) switch (60) and the switching circuit In order to ensure signal transmission during (50), the normally open (NA) switch (60) of the signal coming from the switching circuit (50) is included in the L2 line rather than the normally closed (NK) switch (70). Electronic circuit of an analog current-to-voltage converter, characterized in that said line L1 is longer than said L2 in order to ensure early arrival. The analog current/voltage converter electronic circuit according to claim 1, wherein the L1 line and the L2 line include a metal or a polysilicon material. The analog current/voltage converter electronic circuit according to claim 1, wherein the normally closed (NK) switch (70) and the normally open (NA) switch (60) are CMOS MOSFETs. A biomedical optical imaging system comprising the analog current/voltage converter of claim 1.