JP2568024Y2 - Twin tuner radio data system receiver - Google Patents

Description

[Detailed description of the invention]

[0001]

The present invention relates to a radio data system (hereinafter, radio data system is referred to as RDS) which is suitable for automatic memory of RDS data output from a broadcasting station.
The present invention relates to a twin tuner RDS receiver having two receiving systems.

[0002]

2. Description of the Related Art RDS is a system described in the European Broadcasting Union Technical Specification (EBU document 3244), which allows a listener to easily search for a desired radio program. Among the functions of this system is a function to notify the RDS receiver that the frequency is allocated to another broadcasting station broadcasting the same program as the program currently being received. If a signal having a stronger frequency can be obtained from the station, it is possible to switch the RDS receiver to the reception there. For this reason, the RDS receiver receives the instruction to automatically store the RDS data and receives the data of the alternative frequency (A in this specification).
F data), and a search of a list of stored AF data (hereinafter referred to as a stored AF list) is performed.

In order to search the AF list by the RDS receiver and always select the strongest signal, a program recognition code (hereinafter, referred to as a PI code in this specification) is transmitted from the RDS broadcast station. The RDS receiver searches for a PI code, detects a match of the PI code, and changes the receiving station to a broadcasting station broadcasting the same program.

[0004] Further, in this system, in order to enable the RDS receiver to display the name of a broadcast station being received by the receiver, program service data (P in this specification).
S data) is transmitted. R after receiving PS data
The DS receiver performs display based on PS data such as a broadcast station name.

A conventional twin tuner RDS receiver has a preset memory function and an auto memory function. A plurality of memory channels for storing received broadcast station information such as frequency division ratio data, PI code and PS data for the preset memory function are provided. It is configured to store reception broadcast station information. Further, the memory channel is provided commonly to the first tuner and the second tuner.

[0006]

However, the memory channel is provided with the dividing ratio data and the PI code together with the PS.
If it is necessary to store the data in the auto memory at the same time, it takes time to input the PS data.
There is a problem that it takes a considerable time until the end of the auto memory. For this reason, there is a problem that the user has to wait for a considerable time until the end of the auto memory.

SUMMARY OF THE INVENTION An object of the present invention is to provide a twin tuner RDS receiver in which the time required to detect PS data during auto memory is substantially reduced.

[0008]

The twin tuner RDS receiver of the present invention has two reception systems and a mutual reception system common to the two reception systems and for storing reception frequency information, a PI code, and PS data. A twin tuner radio data system receiver comprising storage means substantially partitioned into an associated memory channel, first detection means for detecting a PI code by one of the tuners based on an auto-memory instruction; First storage control means for storing the received PI code in the memory channel associated with the memory channel storing the reception frequency information related to the PI code, and detecting the PS data by the other tuner independently of the one tuner Second detecting means for storing the detected PS data in the reception frequency information related to the PS data; Characterized by comprising the a second storage control means for storing in a memory the channel associated with the memory channel.

[0009]

According to the twin tuner RDS receiver of the present invention, a PI code is detected by one of the tuners by the first detecting means in response to an auto memory instruction, and the detected PI code is stored by the first storing means by the first storing means. It is stored in a memory channel associated with the received frequency information associated with the code. On the other hand, in the other tuner, the PS data is detected by the second detection means independently of the one tuner, and the detected PS data is stored by the second storage control means in the reception frequency information relating to the PS data. It is stored in the memory channel associated with the memory channel. Therefore, the auto memory of the PI code is completed by one of the tuners quickly, and the next reception by one of the tuners can be performed.
Even if it takes time to input the PS data, the PS data is independently detected by the other tuner and stored in the memory channel, which is equivalent to speeding up the input of the PS data. Thus, the time required for storing the PS data is substantially reduced.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to embodiments. FIG.
FIG. 2 is a block diagram showing a configuration of an embodiment of the present invention.

The twin tuner RDS receiver of this embodiment is a front end 1 and a PLL which operates as a local oscillator for converting to an intermediate frequency in cooperation with the front end 1.
A tuner A including a frequency synthesizer 2 having a configuration, an intermediate frequency amplification circuit 3 for amplifying an intermediate frequency signal output from the front end 1, and a detection circuit 4 for detecting an output of the intermediate frequency amplification circuit 3, a front end 5, and a front end. A frequency synthesizer 6 having a PLL structure acting as a local oscillator for converting to an intermediate frequency in cooperation with the end 5, an intermediate frequency amplifying circuit 7 for amplifying the intermediate frequency signal output from the front end 5, and an intermediate frequency amplifying circuit 7 And a composite signal switching circuit 9 comprising an analog switch for selecting and outputting one of the outputs of the detection circuits 4 and 8.

Further, the twin tuner RDS receiver has a stereo demodulation circuit 10 for receiving the output from the composite signal switching circuit 9 and performing stereo demodulation, a volume control / speech mute circuit 11 for receiving and controlling the stereo demodulated output, An amplifier 12 amplifies the output of the volume control / audio mute circuit 11 and drives the speaker 13. The amplifier 12 performs a receiving operation of stereo-demodulating the composite signal selected by the composite signal switching circuit 9 and reproducing it as audio.

Further, in the tuner A, the electric field intensity detection circuit 14 for detecting electric field intensity information from the output of the intermediate frequency amplifier circuit 3 and the detection output from the detection circuit 4 are within a predetermined range with respect to the output at the time of tuning. And a RDS demodulation circuit 16 for demodulating the RDS information from the detection output from the detection circuit 4 in synchronization with the RDS information. An electric field intensity detection circuit 17 for detecting electric field intensity information, a level detection circuit 18 for detecting that a detection output from the detection circuit 8 is within a predetermined range with respect to an output at the time of tuning, and a detection output from the detection circuit 8 An RDS demodulation circuit 19 for demodulating the RDS information in synchronization with the RDS information is provided.

Further, the twin-tuner RDS receiver is substantially divided into memory channels common to tuners A and B and associated with each other for storing reception frequency information, PI code and PS data. It is determined whether the signal can be received by the tuner A from the electric field intensity information detected by the electric field intensity detection circuit 14 and the output of the level detection circuit 15.
It is determined from the electric field strength information detected from 7 and the output of the level detecting circuit 18 whether the tuner B can be received, and a mute signal is transmitted during the search for the receivable station and the RDS broadcast station, and the volume control / voice mute circuit 11 In addition to the mute operation, the RDS information demodulated by the RDS demodulation circuits 16 and 19 is input to detect the PI code and the PS data. Is provided with a microcomputer 20 to be stored in the microcomputer.

Here, the address of the memory channel is common to the tuners A and B, but the addresses can be specified independently from the tuners A and B. The microcomputer 20 functionally comprises a detecting means 20-1 for detecting the dividing ratio data and the PI code of the receiving broadcast station on the tuner A side when the automatic memory is instructed, and the detected receiving broadcast station Control means 20-2 for storing the frequency division ratio data and the PI code in successive memory channels of the RAM 21, a detecting means 20-3 for detecting the PS data of the receiving broadcast station on the tuner B side, There is provided a storage control means 20-4 for storing data in a memory channel corresponding to a corresponding frequency division ratio data storage memory channel of the RAM 21, for example, a memory channel of a next successive address.

The operation of the embodiment constructed as described above will be described with reference to the flowchart of FIG.

When an auto memory instruction is given by the auto memory instruction switch 22, the address ADa of the RAM 21 specified by the tuner A of the memory channel is set to {0}, and the address ADa is reset by the tuner B of the memory channel. Initialization of an address for setting the designated address ADb of the RAM 21 to {2} is performed (step S).
1). When the address is initialized, it is checked whether or not one round has been made in the band (step S2). Addresses ADa and ADb are updated by +3.

It is checked whether the band has made one round. For example, there are cases where the number of receivable broadcasting stations in the band is less than 1/3 of the number of memory channels, and when the number of re-circulated broadcast stations is once again turned to the same division ratio data. The auto memory of the tuner A ends even if the storage is not completed in all of the memory channels, and step S9 described later is executed.

If it is determined in step S2 that one round in the band has not been completed, it is checked after step S2 whether storage in all of the memory channels has been completed (step S3). The execution of step S3 is opposite to the case of step S2. In some cases, the number of receivable broadcast stations in the band is larger than 1/3 of the number of memory channels. The memory ends, and step S9 described below is executed.

If it is determined in step S3 that the storage has not been completed in all of the memory channels, the next frequency division ratio data is set in tuner A, that is, in frequency synthesizer 2 (step S4). It is checked whether the reception state of the broadcast of the reception frequency based on the frequency division ratio data is good (step S5). The output of the electric field intensity detection circuit 14 of the tuner A detects that the electric field intensity due to the radio wave of the receiving broadcast station is equal to or higher than a predetermined level, and the level detection circuit 15 detects that the detection output is within a predetermined range across the output at the time of tuning. Is determined to be good. If the electric field strength is lower than a predetermined level or the detection output is not within a predetermined range with respect to the output at the time of tuning, it is determined that the reception state is not good.

If it is determined in step S5 that the reception condition is good, the RDS demodulation circuit 1 is executed following step S5.
The process waits until a PI code is detected from the output of step 6 (step S6). When the PI code is detected in step S6, it is checked whether or not the same PI code is already stored in the memory channel (step S7).

If it is determined that the same PI code is not stored, the frequency division ratio data set in step S4 and the PI code determined not to be stored in step S7 are stored in the address following step S7. ADa is stored in the memory channel of the two following addresses, and +3 is added to the address ADa, and the address A
Da is updated (step S8). Address AD
The reason why the address ADa is updated by adding +3 to a is to store PS data at the next address ADb (= DAa + 2).

Following step S8, the address ADa is compared with the address (ADb-2), and ADa> (ADb
-2) is checked (step S9). If it is determined in step S9 that ADa> (ADb-2) is not satisfied, the process ends.

If it is determined in step S7 that the same PI code has already been stored, step S8 is skipped and step S9 is executed following step S7. If it is determined in step S5 that the reception state is not good, step S9 is executed following step S5.

In step S9, ADa> (ADb-
When it is determined to be 2), the frequency division ratio data stored in the memory channel at the address ADa is set in the tuner B after step S9 (step S1).
0). Subsequent to step S10, it is checked whether a PS code is detected from the PS data being output from the RDS demodulation circuit 19 (step S11).

In step S11, when the PS data is detected, the address ADb obtained by adding +2 to the address ADa in which the frequency division ratio data set in step S10 is stored, that is, reception by the frequency division ratio data set in step S10. The PS data is stored in the memory channel of the next address ADb in which the PI code detected by the above is stored, and the address ADb is updated by +3 to the address ADb (step S12).

After step S12, the process is executed again from step S2. If no PS data is detected in step S11, step S12 is skipped and step S2 is executed again. In this case, when step S10 is executed, the address A
The addresses two and one before the memory channel of Db are already stored in the frequency division ratio data having a good reception state and the Ps detected by the reception of the reception frequency based on the frequency division ratio data.
The memory channel in which the I code is stored, the PS data detected later by the reception of the reception frequency based on the frequency division ratio data is detected in step S11, and the frequency division ratio data corresponding to the PS data is stored. The PS data will be stored at the address after the second.

Therefore, even if the detection of the PS data is delayed in time, the storage of the frequency division ratio data and the PI code and the storage of the PS data are performed independently. There is no delay in the storage of the PI code, and even after the end of the auto memory in the tuner A, the storage of the PS data is performed, which has the same effect as the storage of the PS data is substantially accelerated.

In the above-described embodiment, the case where the related frequency division ratio data, PI code and PS data are stored in continuous memory channels has been exemplified. However, a separate table is provided, and the tables are related to each other based on the table. The division ratio data, the PI code, and the PS data may be stored in discontinuous and related addresses, and the related division ratio data, the PI code, and the PS data may be searched with reference to the table.

[0030]

As described above, according to the present invention, in a twin tuner radio data system receiver, a PI code is detected in one of the tuners according to an auto memory instruction, and the detected PI code is received in association with the PI code. The frequency information is stored in a memory channel associated with the stored memory channel, the other tuner detects PS data related to the reception frequency independently of one tuner, and stores the detected PS data in the P channel.
Since the reception frequency information related to the S data is stored in the memory channel associated with the memory channel storing the PI data, the auto memory of the PI code ends in one tuner first, and the next reception by one tuner can be performed. During this time, even if it takes time to input the PS data, the PS data is detected independently in the other tuner and stored in the memory channel, and the input of the PS data is substantially accelerated. This has the effect of substantially reducing the time required to store PS data.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a flowchart for explaining the operation of the embodiment of the present invention;

[Explanation of symbols]

 1 and 5 Front end 2 and 6 Frequency synthesizer 3 and 7 Intermediate frequency amplifier circuit 4 and 8 Detection circuit 9 Composite signal switching circuit 10 Stereo demodulation circuit 14 and 17 Electric field strength detection circuit 15 and 18 Level detection circuit 16 and 19 RDS demodulation circuit Reference Signs List 20 microcomputer 20-1 and 20-3 detecting means 20-2 and 20-4 storage controlling means 21 RAM

Claims (1)

(57) [Scope of request for utility model registration] A storage means common to two reception systems and memory channels common to the two reception systems and substantially associated with each other for storing reception frequency information, a PI code, and PS data. A twin tuner radio data system receiver comprising: a first detecting means for detecting a PI code by one of the tuners based on an auto memory instruction;
First storage control means for storing the received frequency information related to the I code in a memory channel associated with the memory channel, and second detection means for detecting PS data by the other tuner independently of one tuner. And a second storage control means for storing the detected PS data in a memory channel associated with a memory channel storing reception frequency information related to the PS data. Machine.