JP2616618B2 - Data receiving device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data receiving apparatus used for a digital car telephone or the like.

[0002]

2. Description of the Related Art FIG. 3 shows a configuration of a conventional data receiving apparatus. In FIG. 3, reference numeral 31 denotes a detector for converting a received signal into a baseband signal. A change point detector 32 extracts a change point of the converted baseband signal, and is connected to the detector 31. A phase comparator 33 detects a phase difference between the extracted change point and a clock signal used for identification, and is connected to the change point detector 32.
Numeral 34 denotes a variable frequency divider which calculates the difference between the number of times when the clock signal used for discrimination is the phase lead and the case where the phase lag is used for the change point extracted as a result of the phase comparison, and when a certain difference occurs, the variable frequency divider 37 Is a phase difference state counter for instructing a change in the frequency division number, and is connected to the phase comparator 33. Reference numeral 35 denotes a reception state controller which determines the next time to be received from the received data, and permits a change in the frequency division number only when reception is to be performed, and instructs fixed frequency division when reception is not performed. An oscillator 36 is a source of a clock signal used for identification. 3
Reference numeral 7 denotes a variable frequency divider that changes the frequency division number of the signal from the oscillator 36 based on the result of the phase difference state counting, and includes a phase comparator 33, a phase difference state counter 34, a reception state controller 35, and an oscillator 36. It is connected to the. Reference numeral 38 denotes a decoder for decoding data received from the baseband signal and the clock reproduced by the variable frequency divider so as to be optimal for identification,
The detector 31, the reception state controller 35, and the variable frequency divider 37 are connected.

Next, the operation of the above conventional example will be described.
Upon receiving the signal, the detector 31 converts the signal into a baseband signal. The change point detector 32 connected to the detector 31
A change point of the converted baseband signal is extracted, and a phase difference between the extracted change point and a clock signal used for identification is detected by a phase comparator 33, and a difference between the number of phase advance and the number of phase delay is determined in advance. When the value reaches a certain value, the frequency dividing number of the variable frequency divider 37 is changed so as to eliminate the phase difference. However, the variable frequency divider 37 prohibits the change of the frequency division number during the time when the reception state controller knows the non-reception time zone from the previously decoded data, and operates with fixed frequency division. The decoder 38 decodes data received from the baseband signal and the clock reproduced by the variable frequency divider 37 so as to be optimal for identification.

As described above, the conventional data receiving apparatus operates in synchronization with the transmitter while receiving a signal, reproduces an optimal clock for identification, and can decode data without error.

[0005]

However, in the above-mentioned conventional data receiving apparatus, when the signal is no longer received, the frequency dividing number of the variable frequency divider is fixed to a constant value to generate the identification clock. Due to the relative error between the oscillator and the receiving oscillator, the discrimination clock deviates from the optimal point,
When the reception is started again, it takes a long time to reproduce the clock, and there is a problem that the clock is easily affected by the fluctuation of the identification clock.

The present invention solves such a conventional problem, and takes advantage of the characteristics of the received data, so that the frequency of changing the frequency of the clock for establishing the synchronization is increased by the variable frequency divider in the variable frequency divider. It is an object of the present invention to provide a data receiving apparatus that reproduces an identification clock promptly, reduces the frequency of changing the frequency division number for information bits, and decodes data with a stable identification clock.

[0007]

According to the present invention, there is provided a detector for converting a received signal into a baseband signal, and a change point detector for extracting a change point of the converted baseband signal. A phase comparator that detects the phase difference between the extracted change point and the clock signal used for identification, and counts the number of phase advance and phase delay as a result of the phase comparison, and the difference between the number of phase advance and phase delay is constant. A phase difference state counter that instructs the variable frequency divider to change the frequency division number when the number of times reaches, and a reception state controller that identifies the time at which the receiving device receives data based on information obtained from the received data. A counting controller that switches the frequency of changing the frequency division number of the variable frequency divider between the synchronization establishment bit and the information bit when the reception state controller instructs data reception, and a clock signal used for identification. A source of Oscillator, a variable frequency divider that changes the frequency of the signal from the oscillator based on the instruction of the phase difference state counter, and a clock and baseband reproduced by the variable frequency divider to be optimal for identification. And a decoder for decoding data received from the signal.

[0008]

According to the present invention, when the receiving operation is started for a slot to be received from the absence of a received signal, the frequency of change in the synchronization establishment bit is increased and the clock of the transmitter is quickly transmitted. Then, the identification clock synchronized with the above is reproduced, and the frequency of changing the information bits is reduced, and the data is decoded with the stable identification clock.

[0009]

FIG. 1 shows an embodiment of a data receiving apparatus according to the present invention. In FIG. 1, reference numeral 1 denotes a detector for converting a received signal into a baseband signal. 2 is a change point detector for extracting a change point of the converted baseband signal;
It is connected to the detector 1. A phase comparator 3 detects a phase difference between the extracted change point and a clock signal used for identification, and is connected to the change point detector 2. 4 calculates the difference between the number of times when the clock signal used for identification is the phase advance and the case where the phase lag occurs for the change point extracted as a result of the phase comparison, and calculates a certain difference designated by the counting controller 6. Occurs, the phase difference state counter instructs the variable frequency divider 8 to change the frequency division number, and is connected to the phase comparator 3. 5
Receiving obtains the next time to be received from the received data output from the decoder 9, to allow the variation frequency division number of the variable frequency divider only when to be received, which instructs the fixed frequency division when not received It is a state controller. 6 so that the received signal is shown in FIG. 2, the optionally <br/> Rutoki divided into bits for synchronization establishment bit information, variable frequency to the synchronization establishment bits seen in the reception state controller 5 times the frequency division number such that the change frequency increases in vessel 8, also the variable frequency divider 8 dividing number of the change frequency so decreases the phase difference state counting the time for the bit information
It is a counting controller for instructing a threshold value of the unit 4 and is connected to the phase difference state controller 4 and the reception state controller 5. Reference numeral 7 denotes an oscillator serving as a source of a clock signal used for identification. 8 is received
A variable frequency divider that changes the frequency division number of the signal from the oscillator 7 based on the results of the transmission state controller 5 and the phase difference state counter 4, and includes a phase comparator 3, a phase difference state controller 4, a reception state It is connected to a controller 5 and an oscillator 7. 9 is a variable frequency divider 8
And a decoder for decoding data received from the recovered clock and baseband signal so as to be optimal for identification, and is connected to the detector 1, the reception state controller 5, and the variable frequency divider 8.

Next, the operation of the above embodiment will be described.
Upon receiving the signal, the detector 1 converts the signal into a baseband signal. In the connected change point detector 2 to the detector 1, the detection
A change point of the baseband signal converted by the detector 1 is extracted, a phase difference between the extracted change point and a clock signal used for identification is detected by a phase difference comparator 3, and a phase difference state counter 4 detects the phase difference. The difference between the number of phase advance and the number of phase lag is determined by the counting controller 6.
When the frequency reaches a predetermined constant threshold value designated by , the frequency division number of the variable frequency divider 8 is changed so as to eliminate the phase difference. However, the time that the reception state controller 5 knows from the previously decoded data as the non-reception time zone is acceptable.
The variable frequency divider 8 prohibits the change of the frequency division number, and operates at a fixed frequency division.

When the received data is divided into a synchronization establishment bit and an information bit as shown in FIG. 2, the boundary is estimated by the reception state controller 5 and the time period during which the synchronization establishment bit is received is received. Since the base station includes many changing points of the baseband signal, the count controller 6 controls the variable frequency divider 8 so that the frequency of changing the frequency division number increases in order to quickly establish synchronization with the base station by using the change points. From the phase difference state counter 4
The threshold value is controlled, and thereafter, in the time period when the information bits are received, the variable frequency divider 8 controls the threshold value of the phase difference state counter 4 from the count controller 6 so that the frequency of changing the frequency division number is reduced. And generates a stable identification clock. In the decoder 9,
The variable frequency divider 8 decodes the clock and the data received from the baseband signal reproduced so as to be optimal for identification.

As described above, according to the present embodiment, not only during reception of a signal, but also when reception is once stopped and then started again, operation is quickly performed in synchronization with the transmitter, and identification is performed. This has the advantage that the most suitable clock can be reproduced and the data can be decoded without errors.

[0013]

As is apparent from the above embodiment, according to the present invention, a detector for converting a received signal into a baseband signal, a change point detector for extracting a change point of the converted baseband signal, A phase comparator that detects the phase difference between the changed transition point and the clock signal used for identification, and counts the number of phase advance and phase delay as a result of the phase comparison, and a certain number of times the difference between the number of phase advance and phase delay is obtained A phase difference state counter that instructs the variable frequency divider to change the frequency division number when
A reception state controller that identifies the time at which the receiving device receives data based on information obtained from the received data, and a variable bit for establishing synchronization and an information bit when the reception state controller instructs data reception. A counting controller that switches the frequency of changing the frequency of the frequency divider, an oscillator that is a source of a clock signal used for identification, and a frequency dividing number of the signal from the oscillator based on an instruction of the phase difference state counter. A variable frequency divider to change,
Since it is equipped with a clock that is reproduced so as to be optimal for discrimination by the variable frequency divider and a decoder that decodes data received from the baseband signal, a slot to be received from the absence of a received signal is provided. When the receiving operation is started, the frequency of change is increased in the synchronization establishment bit, and the identification clock synchronized with the transmitter clock is quickly reproduced,
It is possible to provide a data receiving apparatus capable of decoding data with a stable identification clock while changing the information bits with a low frequency of change.

[Brief description of the drawings]

FIG. 1 is a block diagram of a data receiving apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram showing a slot format of a received signal.

FIG. 3 is a block diagram of a conventional data receiving apparatus.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Detector 2 Change point detector 3 Phase comparator 4 Phase difference state counter 5 Reception state controller 6 Count controller 7 Oscillator 8 Variable frequency divider 9 Decoder

Claims (1)

(57) [Claims] 1. A detector for converting a received signal into a baseband signal, a change point detector for extracting a change point of the converted baseband signal, and a phase difference between the extracted change point and a clock signal used for identification. Phase detector to detect the phase advance and phase lag count of the phase comparison result
Phase difference state counter and whether the received signal is decoded data
A receiving state controller for identifying a time at which the receiving apparatus receives data based on the information obtained, and receiving a synchronization establishment bit and an information bit when the receiving state controller instructs data reception. Separate time zone
A counting controller for switching a threshold value in the phase difference state counter, an oscillator serving as a source of a clock signal used for identification, and an oscillator based on instructions from the reception state controller and the phase difference state counter. comprising a variable frequency divider to change the frequency division number of the signal, and a decoder for decoding the data received from the recovered clock and the base band signal to be optimum identified by the variable frequency divider, wherein Phase difference state counting
The difference between the number of phase advance and the number of phase lags is
Variable frequency divider when a certain number of times specified by
A data receiving apparatus for instructing a change of a frequency division number .