JP2632964B2 - Test processing method of coaching device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a logic device test processing method for testing a logic function of a designed logic device using a logic simulator that executes a simulation of a logic device described at a gate level. The purpose of the simulation is to execute the logic simulation executed according to the test program quickly, and it is configured with the same architecture as the logic device to be tested, and simulates the logic function of the logic device at the software instruction level. A software simulator to execute, the software simulator processes a program part for setting a test environment in a test program, and a logic simulator is obtained according to the execution process of the soft simulator. Logical unit resource status It is configured to execute a program portion related to a test in the test program using the data.

[Industrial applications]

The present invention relates to a test processing method of a logic device for testing a logic function of a designed logic device, and particularly, when executing a test using a logic simulator, a logic simulation for the test can be quickly executed. The present invention relates to a test processing method of a logic device for performing the above.

In the development of logic devices such as computers, as the integration density and packaging density of logic devices increase, at the design stage,
It is necessary to test whether the logic function of the logic device is as specified. In recent years, logic simulators for performing simulations of logic functions of logic devices have been developed to achieve this purpose. However, this logic simulator execution speed is
In fact, the actual processing speed is much slower than the actual processing speed. From now on, it is desired to provide a test processing method for a logic device so that a logic simulation by the logic simulator can be executed quickly.

[Conventional technology]

In order to test the logic function of a logic device designed using a logic simulator, a circuit model of the designed logic device to be simulated is developed in the logic simulator, and the developed logic device is developed. A test program for testing the logical function of the above is input. Then, the logic simulator executes a logic device test by performing a logic simulation according to the input test program.

This input test program can be broadly classified,
The test program is divided into an initialization program for setting a test environment and a test program for executing an actual test. The initialization program portion and the test program portion are indispensable for executing the logic simulation. From this, the prior art adopts a configuration in which both the initialization program portion and the test program portion are input as test programs to the logic simulator.

[Problems to be solved by the invention]

However, the initialization program portion includes an instruction sequence generation program for dynamically generating an instruction sequence of a test program portion that is a true test program. This instruction sequence generation program is actually a program that requires a considerable number of steps. For this reason, in the related art, there is a problem that the execution processing speed of the logic simulator is greatly delayed, and a test of the logic device cannot be executed quickly.

The present invention has been made in view of such circumstances,
When testing the logic function of a logic device designed using a logic simulator, a logic device test processing method is provided that enables quick execution of a logic simulation, thereby realizing a quick test process. It is intended for.

[Means for solving the problem]

 FIG. 1 is a diagram illustrating the principle of the present invention.

In the figure, 1 is a designed logic device to be tested, 10 is a logic simulator that simulates the logic function of the logic device 1 described at the gate level, 20 is a test program, A program 30 for testing the logic device 1 is a software simulator, which has the same architecture as the logic device 1 and executes a simulation for a logic function of the logic device 1 at a software instruction level. Things. The logic simulator 10 includes a test execution program execution unit 11, a logic device model unit 12, and a state data setting unit 13.The test program 20 includes an initialization execution program 21 and a test execution program 22. , An initialization execution program execution unit 31 and a state data storage unit 32.

The test execution program execution unit 11 executes the test execution program 22 to execute a simulation of the logical function of the logical device 1, and the logical device model unit 12 determines that the test execution program execution unit 11 executes the simulation process. FIG. 3 is a circuit model diagram of the logic device 1 described at the gate level and required for the
Processing to set the storage data of the state data storage unit 32 determined with the end of the processing of the initialization execution program execution unit 31 in the resource part of the corresponding logical device model unit 12,
The initialization execution program 21 is a program part for setting a test environment in the test program 20, and the test execution program 22 is a program part related to an actual test in the test program 20. Department
31 sets the test environment by executing the initialization execution program 21, and the state data storage unit 32 stores the resources related to the resources of the logical device model unit 12 which are obtained according to the execution by the initialization execution program execution unit 31. Stores state data.

[Action]

In the present invention, the initialization execution program execution unit 31 executes the initialization execution program 21, and the state data setting unit 13 stores the logical device model unit 12 to be stored in the state data storage unit 32 with this execution. The status data on the resource of the unit is set in the resource portion of the corresponding logical device model unit 12. Then, the test execution program execution unit 11 starts the test execution program 22 based on the set state data.
Is executed, the simulation of the logical device model unit 12 is executed.

Thus, according to the present invention, the logic simulator 10
Eliminates the need to execute the initialization execution program 21 in the test program 20. Therefore, the logic simulator 10
Thus, the simulation of the logical device model unit 12 can be executed quickly, and the test of the designed logical device 1 can be executed quickly.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to an embodiment for logic simulation of a computer.

FIG. 2 shows a configuration diagram of an embodiment of the present invention. In the figure, 2 is a logical specification, which describes the logical specification of the computer to be designed, and 3 is a logical design data file, which is designed based on the logical specification 2. It stores circuit information about the logic circuit of the computer to be tested described at the gate level.

10 is the logic simulator described in FIG.
A simulator for simulating the logic function of the computer under test described at the gate level. Reference numeral 10a denotes an input unit of the logic simulator 10, which receives state data and a test program required for the logic simulation of the computer under test. A computer that executes processing, 10b is a computer model to be tested that is developed on the logic simulator 10, and is a circuit model of the computer to be tested described at the gate level, and is a test model according to the test program received by the input unit 10a. A controller for executing a logic simulation of the logic function of the computer, 10c is a control unit of the logic simulator 10, and controls a logic simulation executed by the computer model 10b to be tested.

Reference numeral 20 denotes the test program described in FIG.
As described with reference to the figure, an initialization execution program 21 and a test execution program 22 are provided. Numeral 30 denotes a software simulator also described in FIG. 1, which operates as one job under the operating system and simulates, at the software instruction level, a logical function of the computer under test described in the logical specification 2. What to do,
Reference numeral 30a denotes an execution unit of the software simulator 30, which executes initialization logic for setting a test environment according to the test program 20 by executing the logic of the architecture of the computer under test, and 30b denotes an execution unit of the software simulator 30. A resource unit, which represents resources such as a main memory and registers of the computer to be tested; 30c is an output unit of the software simulator 30, and is a resource unit 30b determined upon completion of the execution process of the execution unit 30a. , And the test program 20 after the initialization process, that is, the test execution program 22.

Numeral 40 denotes a simulation data file which stores the status data output from the software simulator 30 and the test execution program 22, and numeral 50 denotes a conversion program which stores the logic of the computer under test stored in the logical design data file 3. Converts circuit information to a logic simulator
It is developed as a test target computer model 10b on FIG.

Still, 101 is the CPU that constitutes the computer model 10b under test.
Unit, 102 is a memory unit that also constitutes the computer model under test 10b, and 301 is a CPU represented by the resource unit 30b.
The unit 302 is a memory unit also represented by the resource unit 30b. The logic simulator 10 and the software simulator 30 have the same architecture of the computer to be tested, so the CPU unit 101 and the CPU unit 301 are the same, although there is a difference in expression, and the memory unit 102 The memory unit 302 is the same.

Next, the processing content of the test processing method of the present invention will be described with reference to the flowchart shown in FIG.

In order to execute a test of the logical function of the computer under test,
First, as shown in step 1, a soft simulator
The test program is stored in the memory unit 302 of the 30 resource units 30b.
Load 20. Subsequently, in step 2, the execution unit
30a is one of the loaded test programs 20
Decode and execute instruction steps. Then, in the next step 3, status data on the registers of the CPU unit 301, the memory unit 302, and the like obtained by this execution are set in the corresponding locations of the resource unit 30b. The executing unit 30a determines in a subsequent step 4 whether or not the initialization processing has been completed. This determination is made based on whether or not the instruction of the test program 20 read for the next execution processing is an instruction indicating the boundary between the initialization execution program 21 and the test execution program 22. The instruction indicating this boundary indicates that the initialization process has been completed.
, Which is embedded in the test program 20 to be notified, and is architecturally defined as a no-operation and has a special operand.

If it is determined in step 4 that the initialization process has not been completed, the process returns to step 2 to execute the instruction step of the test program 20 read as the next execution instruction. In this way, by repeating the processing of step 2 to step 4,
By the determination in step 4, it is determined that the initialization process has been completed. That is, when the execution of the portion related to the initialization execution program 21 of the test program 20 ends, it is determined that the test environment for the logic simulator 10 has been required. At this time, the process proceeds to step 5, and the output unit 30c compares the state data set in the resource unit 30b and the test execution program 22 which is an unprocessed part in the test program 20 with the simulation data file 40.
Will be processed to be stored.

The processing up to step 5 described above is executed by the software simulator 30. Note that the processing executed by the initialization processing includes, in addition to the above-described instruction string generation processing, generation processing of an address conversion table when the test target is a computer.

In this way, when the initialization process by the software simulator 30 is completed, the input unit 10a of the logic simulator 10
In step 6, the simulation data file 40
Of the computer model to be tested 10b
Expand to That is, the resource section of the software simulator 30
The state data of the target computer model 10b of the logic simulator 10 is set, and the unprocessed test execution program 22 is set in the target computer model 10b.
To be stored in the memory unit 102. With this processing, the status data of the CPU unit 301 is
01 is set, and the status data of the memory unit 302 is set in the memory unit 102.

When it is determined in the next step 7 that the development processing in step 6 has been completed, the computer model to be tested 10b continues the execution of the test program 20 from the point in the subsequent step 8 where the software simulator 30 interrupted the processing. Will be. With this processing, the logic simulation of the computer model 10b to be tested is executed in accordance with the test execution program 22, and the logic circuit information of the computer to be tested stored in the logic design data file 3 is designed in accordance with the two logical specifications. Will be tested. And
In the following step 9, this test result is output.

As described above, in the present invention, the software simulator 30 executes the processing for setting the test environment, and the logic simulator 10 executes the logic simulation based on the set test environment. Make up.

〔The invention's effect〕

As described above, according to the present invention, when a test of a logic function of a logic device is performed using the logic simulator, the logic simulator is configured to execute only a true test portion. Therefore, the simulation processing time is shortened, and the test of the logic function of the logic device can be executed quickly.

[Brief description of the drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is a flowchart executed by the present invention. In the figure, 1 is a logic device, 2 is a logic specification, 3 is a logic design data file, 10 is a logic simulator, 10a is an input unit, 1
0b is a computer model to be tested, 10c is a control unit, 11 is a test execution program execution unit, 12 is a logic device model unit, 13 is a state data setting unit, 20 is a test program, 21 is an initialization execution program, and 22 is a test execution. Program, 30 is a software simulator, 30a is an execution unit, 30b is a resource unit, 30c is an output unit, 31
Is an initialization execution program execution unit, 32 is a state data storage unit, 40 is a simulation data file, 50 is a conversion program, 101 is a CPU unit, 102 is a memory unit, 3
01 is a CPU unit and 302 is a memory unit.

Claims (1)

(57) [Claims] A logic simulator (10) for executing a simulation of a logic circuit described at a gate level is prepared, and a logic device (1) described at a gate level to be tested is provided in the logic simulator (10). And a test processing method for executing a test of the logical device (1) to be tested by inputting a test program (20) for testing the logical function of the developed logical device (1). And a software simulator (30) configured with the same architecture as the logic device (1) and executing a simulation for the logic function of the logic device (1) at a software instruction level. ) Executes a program part for setting a test environment in the test program (20), and The logical simulator (10) uses the state data relating to the resources of the logical device (1) to be obtained in accordance with the execution processing of the software simulator (30), and uses the state data relating to the test in the test program (20). A test processing method for a logic device, characterized in that a test of the logic device (1) is performed by processing to execute a part.