JP2811763B2 - Method for manufacturing insulated gate field effect transistor - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a gate insulating film of an insulated gate field effect transistor.

[Prior art] In recent years, as the need for three-dimensional ICs, large, high-resolution liquid crystal display panels, and high-speed, high-resolution contact-type image sensors has increased, technology for forming high-quality gate insulating films at low temperatures has been increasing. Has become important. The thermal oxidation method is 900-1200
(1) An element cannot be formed on an inexpensive glass substrate. (2) The three-dimensional IC has a problem of giving an adverse effect (diffusion of impurities, etc.) to an element in a lower layer portion, and a technique for forming an oxide film at a low temperature by a CVD method or the like is being studied.

[Problems to be Solved by the Invention] However, the oxide film formed by the CVD method has problems such as a high gate dielectric strength and a high interface state density, and it is difficult to stably form a practical-level element. there were. Accordingly, the present invention is to solve such a problem, and an object of the present invention is to provide a method for forming a gate insulating film for an insulated gate field effect transistor having a high gate withstand voltage and a low interface state density. To provide.

[Means for Solving the Problems] The present invention relates to a method of manufacturing an insulated gate field effect transistor, which comprises introducing a gate insulating film made of a silicon oxide film by sputtering into a gas tank containing at least argon gas and helium gas. The method is characterized in that a film is formed.

In the method of manufacturing an insulated gate field effect transistor according to the present invention, the concentration of the helium gas is 5% or more.

In the method for manufacturing an insulated gate field effect transistor according to the present invention, the gate insulating film is formed such that an internal pressure in the tank is less than 1.0 Pa.

The method of manufacturing an insulated gate field effect transistor according to the present invention is characterized in that at least a part of a channel region of the insulated gate field effect transistor is a non-single-crystal semiconductor.

Embodiment FIG. 1 is an example of a manufacturing process diagram of a semiconductor device according to an embodiment of the present invention. FIG. 1 shows an example in which a thin film transistor (TFT) is formed as a semiconductor element.

In FIG. 1, (a) shows a silicon layer 102 formed on an insulating amorphous material 101 such as an insulating amorphous substrate such as glass or quartz or an insulating amorphous material layer such as SiO _2. This is the step of performing As an example of the film forming conditions, 500 ° C. to 56 ° C. by the LPCVD method
A method of forming a silicon film with a thickness of about 100 to 2000 mm at about 0 ° C., a gas obtained by diluting monosilane or monosilane with hydrogen, argon, helium, etc. while maintaining the substrate temperature at room temperature to about 600 ° C. by a plasma CVD method. Is introduced into a reaction chamber, and high-frequency energy or the like is applied to decompose the gas to form a silicon layer on a desired substrate with a thickness of about 100 to 2000 mm. However, the film formation method is not limited to this, for example, a sputtering method, an evaporation method, an EB evaporation method,
There is a method of forming amorphous silicon or microcrystalline silicon by MBE or the like.

FIG. 1 (b) shows a step of crystal growth of the silicon layer 102 by heat treatment or the like. The heat treatment conditions include the step (a)
The optimum conditions differ depending on the method of forming the silicon layer.

For example, when the film is formed by the LPCVD method, the polycrystalline silicon layer 103 is formed by performing a heat treatment at about 550 ° C. to 650 ° C. for about 2 to 50 hours in an atmosphere of an inert gas such as nitrogen or Ar.

Further, when the film is formed by the plasma CVD method, for example, there is a difference as described below depending on the substrate temperature at the time of film formation.

(1) A film formed at a relatively low substrate temperature of about room temperature to about 150 ° C becomes amorphous silicon containing a large amount of hydrogen in the film, but compared with a film formed at about 200 to 300 ° C. Thus, hydrogen in the film can be removed by heat treatment at a lower temperature. An example of the heat treatment condition is described below. First annealing is performed on the formed amorphous silicon film in the plasma CVD reaction chamber. Since an amorphous silicon film having a low film formation temperature is a porous film, if the film is taken out to the atmosphere as it is after film formation, oxygen and the like are easily taken into the film, which causes a deterioration in film quality. When the heat treatment is performed appropriately, the film is densified, and the incorporation of oxygen and the like is prevented. The heat treatment temperature is desirably 300 ° C. or higher, and increasing the temperature to about 400 to 500 ° C. is particularly effective. Even if the heat treatment temperature is lower than 300 ° C., there is an effect of densification of the film by the heat treatment. However, if annealing is performed continuously without breaking vacuum, the first annealing can be omitted.

Subsequently, a second annealing is performed. When a relatively low-temperature heat treatment at about 550 ° C. to 650 ° C. is performed for several hours to about 20 hours, desorption of hydrogen and crystal growth occur in an amorphous silicon film formed at a low film formation temperature, and a crystal grain size of 1 Polycrystalline silicon having a large grain size of about 2 μm is formed. In addition, it is not preferable that both the first annealing and the second annealing rapidly increase the temperature in a short time when the temperature is increased to a predetermined annealing temperature. The reason is that as the temperature increases (especially 300
When the temperature rises rapidly, defects are easily formed in the film. In some cases, pinholes are formed or the film is peeled off.
At a temperature of at least 300 ° C. or higher, a heating rate lower than 20 ° C./min (a heating rate lower than 5 ° C./min is particularly desirable)
When the temperature is gradually raised in step (b), the number of defects in the film decreases.
The details of the heating method will be described later.

(2) The film formed at a substrate temperature of about 150 ° C. to 300 ° C. has a reduced amount of hydrogen in the film but has a lower temperature at which hydrogen is desorbed than the amorphous silicon film formed at a low temperature. Shift to higher temperature. However, since the film after film formation is denser than a film formed at a low temperature, the first annealing described above can be omitted. The second annealing condition is that when a heat treatment at about 550 to 650 ° C. is performed for several hours to about 40 hours, desorption of hydrogen and crystal growth occur, and polycrystalline silicon having a large grain size of 1 to 2 μm is formed. Is done. The details of the method of raising the temperature from 550 ° C. to 650 ° C. will be described later, but at least 30 ° C. as in (1).
20 ° C / min (preferably 5 ° C / min) at temperatures above 0 ° C
It is desirable to gradually increase the temperature at a slower rate of temperature increase because the number of defects in the film is reduced.

(3) When the substrate temperature exceeds 300 ° C., the amount of hydrogen in the film further decreases, but the annealing at about 550 ° C. to 650 ° C. makes it difficult for hydrogen to be desorbed. Heat treatment is important. When a film formed at a substrate temperature of about 500 ° C. or higher is subjected to solid phase growth, polycrystalline silicon oriented in <110> or <100> is obtained.
There are effects such as reduction of the interface state density of FT and improvement of field effect mobility.

FIG. 1C shows a step of heat-treating the polycrystalline silicon layer 103 at a predetermined heat treatment temperature higher than that of the step (b).
Although step (c) can be omitted, it is an important step to improve the crystallization rate. The crystallization ratio of the polycrystalline silicon layer 103 grown by the solid phase growth method in the step (b) is not always high. In particular, a silicon film formed of LPCVD at a relatively low temperature of about 500 ° C. to 560 ° C. (amorphous silicon or microcrystalline silicon in which a fine crystal region exists in an amorphous phase). When solid phase growth is performed by heat treatment, the crystallization ratio is as low as about 50% to 70%. Therefore, it is important to provide a step of crystallizing an uncrystallized region of the polycrystalline silicon layer by performing a heat treatment at a higher temperature in the step (c) than in the step (b). As a result, the crystallization rate can be increased to 99% or more. As the heat treatment temperature, an optimum value exists between about 700 ° C. and 1200 ° C. However, when glass is used as the substrate, since it is not possible to expose to the above-mentioned high temperature, only the vicinity of the semiconductor surface layer is heated to the above-described temperature by irradiating short wavelength light such as an excimer laser, 600 ° C near the interface between the semiconductor layer and the substrate
It is important to optimize the irradiation intensity and irradiation time so as to be less than the degree. As an example, conditions such as irradiation of 1 to 10 pulses (1 pulse number + ns) at an irradiation intensity of about 0.1 to 1.0 J / cm ² using a XeCl excimer laser (wavelength 308 nm) satisfy the above-described conditions. If the interface between the semiconductor layer and the substrate is about 600 ° C. or less when laser irradiation is performed, the condition for melting the surface of the semiconductor layer is preferable because the crystallinity of the semiconductor surface layer becomes better. In particular, since the surface layer is a region where the inversion layer is formed, improvement in crystallinity of the surface layer leads to improvement in transistor characteristics. As another heat treatment method, for example, about 1 hour at 850 ° C. or 10 hours at 1000 ° C. in an inert gas atmosphere such as nitrogen or Ar in an annealing furnace.
There is also a method of performing heat treatment for about 20 minutes, a lamp annealing using a halogen lamp, an arc lamp, an infrared lamp, a xenon lamp, a mercury lamp, a laser annealing using an Ar laser, a He-Ne laser, or the like.

FIG. 1D shows a step of forming the gate insulating film 104 by a sputtering method. When sputtering with only Ar gas,
The dielectric strength of the oxide film is low, and the interface state density of Si / SiO ₂ is also low. However, as a result of our investigation, it has been clarified that the above problem can be solved by introducing He gas in addition to Ar gas. As an example of the film formation method, Ar gas and He
There is a method in which a gas is introduced into a vacuum chamber and sputtering is performed using SiO ₂ as a target. When the concentration of the He gas in the mixed gas is 5% or more, the effect of reducing the damage appears, and when the concentration is 10% or more, the effect becomes remarkable. Practically, about 10% to 50% is desirable. (If it is 50% or more, the effect of reducing the damage is saturated, and the sputter rate is further reduced.) Further, the internal pressure at the time of sputtering also has an important relationship with the reduction of the damage. In other words, the lower the internal pressure, the more the damage tends to decrease.
The effect of damage reduction begins to appear below a, especially at 1.0 Pa
At less than this, the effect of reducing the damage becomes remarkable.

The gas introduced into the vacuum chamber may contain oxygen and the like in addition to Ar gas and He gas. There is also a method of forming an oxide film by using Si instead of SiO ₂ as a target and introducing an Ar gas, a He gas, an oxygen gas or the like into a vacuum chamber. In addition, even if Ne gas is used instead of He gas, the same effect as that of He gas is obtained. However, a higher quality oxide film is obtained by using He gas.

In addition, it is also effective to introduce a gas containing at least hydrogen gas into the vacuum chamber and remove the natural oxide film on the silicon layer 102 by exposing it to hydrogen plasma before forming the oxide film. In this case, (1) the substrate temperature is from room temperature to 300 ° C.
The natural oxide film can be removed at a low temperature. (2) After removing the natural oxide film, a gate insulating film can be formed continuously without breaking vacuum. This has the effect of reducing the interface state of Si / SiO ₂ .

FIG. 1 (e) shows a step of forming a semiconductor element.
FIG. 1E shows an example in which a TFT is formed as a semiconductor element. In the figure, 104 is a gate insulating film, 105 is a gate electrode, 106 is a source / drain region, 10
7 is an interlayer insulating film, 108 is a contact hole, and 109 is a wiring. As an example of a TFT forming method, after forming a gate electrode,
Source / drain regions are formed by ion implantation, thermal diffusion, plasma doping, ion shower doping, etc.
An interlayer insulating film is formed by a CVD method, a sputtering method, a plasma CVD method, or the like. Further, a contact hole is formed in the interlayer insulating film,
The TFT is formed by forming the wiring. When glass is used as a substrate, a source / drain region is formed by implanting impurities such as B and P by ion implantation,
An ion shower doping method, a plasma doping method, and the like are effective in addition to a method of activating impurities by performing a heat treatment at a low temperature of about 600 ° C. for several hours to several tens hours.

The present invention is important in that a high-quality oxide film can be formed at a low temperature by a sputtering method instead of the conventional thermal oxidation method. The details are described below. In the conventional method of sputtering with Ar gas using SiO ₂ as a target, as described above, the withstand voltage was low, the Si / SiO ₂ interface state density was high, and a practical level oxide film could not be formed. Damage caused by Ar ions incident on the substrate surface is considered to be one of the causes. Therefore, means for reducing the number of Ar ions, energy, and the like incident on the substrate surface is essential. In addition to Ar gas
By introducing He gas, the above-mentioned damage is reduced,
It has been confirmed that characteristics that are equal to or higher than those of the thermal oxide film can be obtained in both the withstand voltage and the interface state density. In particular, it has been clarified that the dielectric strength on polycrystalline silicon is higher than that of a thermal oxide film (dielectric strength 3-4 MV / cm), and is about 7-8 MV / cm. The cause is that when polycrystalline silicon is thermally oxidized,
Oxidation easily proceeds along the crystal grain boundaries, so that the oxide film becomes protruding and electric field concentration tends to occur. On the other hand, when an oxide film is formed at a low temperature by a sputtering method, oxygen is hardly diffused along the crystal grain boundaries, and the above-described electric field concentration is unlikely to occur. Furthermore, the oxidation along the crystal grain boundaries forms a high potential barrier at the crystal grain boundaries, thus causing a reduction in the field-effect mobility of the TFT, but using an oxide film formed by the sputtering method of the present invention. In the case, there is almost no diffusion of oxygen along the grain boundary,
Since the potential barrier at the grain boundary can be lowered, there is also an effect that the field effect mobility is greatly improved.

The oxide film formed by the sputtering method according to the present invention has a thickness of 300
Since the film can be formed at a low temperature of about ° C or less, it can be applied to a low-temperature process using an inexpensive glass substrate.

Polycrystalline silicon TFT (N-channel) formed by a low-temperature process using the semiconductor device manufacturing method according to the present invention
Has a field-effect mobility of about 200 to 250 cm ² / V · sec, which is superior to TFT formed by thermal oxidation.

Further, a step of exposing the semiconductor element to a plasma atmosphere of a gas containing at least hydrogen gas or ammonia gas is provided in the TFT manufacturing step, and when the TFT is hydrogenated, a defect density existing at a crystal grain boundary is reduced, and the electric field is reduced. The effect mobility is further improved.

Also, doping the channel region with an impurity, Vt
Means for controlling h (threshold voltage) is also very effective. In a polycrystalline silicon TFT formed by the solid phase growth method, N
Vth of the channel transistor shifts in the depletion direction, and P-channel transistor tends to shaft in the enhancement direction. When the TFT is hydrogenated, the tendency becomes more remarkable. Therefore, if the channel region is doped with an impurity of about 10 ¹⁵ to 10 ¹⁹ / cm ³ , the shift of Vth can be suppressed. For example, the first
In the figure, there is a method of implanting an impurity such as B (boron) at a dose of about 10 ¹¹ to 10 ¹³ / cm ² by ion implantation or the like before forming a gate electrode. In particular, when the dose is about the above value, the off-state current of both the P-channel transistor and the N-channel transistor is minimized.
Vth can be controlled. Therefore, even when a CMOS type TFT element is formed, the entire surface can be channel-doped in the same step without selectively channel-doping Pch and Nch.

In addition, the present invention relates to a poly-Si TFT shown in the embodiment of FIG.
The present invention is not limited to this, and can be used for a gate insulating film over single crystal silicon, a gate insulating film over non-single-crystal silicon such as polycrystalline silicon, microcrystalline silicon, and amorphous silicon.
Further, the present invention is not limited to TFTs, but can be applied to insulated gate semiconductor devices in general. Further, the oxide film of the present invention can be used not only as a gate insulating film but also as an interlayer insulating film, a passivation film, and the like, and has a great merit that an insulating film having a high withstand voltage can be formed at a low temperature.

[Effects of the Invention] As described above, according to the present invention, the withstand voltage is high,
An oxide film having a low interface state density can be formed at a low temperature. In particular, when an oxide film is formed on polycrystalline silicon by the sputtering method according to the present invention, the withstand voltage is higher and the interface state density is lower than when an oxide film is formed by thermally oxidizing polycrystalline silicon. Was completed. Furthermore, compared to thermal oxide film
Another effect is that the field-effect mobility of the TFT is greatly improved. As a result, it is possible to form a high-performance semiconductor device on an insulating amorphous material, and it is easy to produce a large, high-resolution liquid crystal display panel, a high-speed, high-resolution contact-type image sensor, or a three-dimensional IC. Can be formed. Also, since the method for forming an oxide film according to the present invention is a low-temperature process,
It is also possible to use an inexpensive glass substrate as the substrate. In a three-dimensional IC, an upper-layer element can be formed without adversely affecting the lower-layer element (for example, redistribution of impurities).

Further, the present invention can be applied to general insulated gate semiconductor devices other than the TFT shown in the embodiment of FIG.

[Brief description of the drawings]

1 (a) to 1 (e) are manufacturing process diagrams of a semiconductor device according to an embodiment of the present invention. 101 insulating amorphous material 102 silicon layer 103 polycrystalline silicon layer 104 gate insulating film 105 gate electrode 106 source / drain region 107 interlayer insulating film 108 contact hole 109 ... Wiring

Claims (4)

(57) [Claims] In a method of manufacturing an insulated gate field effect transistor, a gas containing at least argon gas and helium gas is introduced into a tank, and a gate insulating film made of a silicon oxide film is formed by a sputtering method. Of manufacturing an insulated gate field effect transistor. 2. The method according to claim 1, wherein the concentration of the helium gas is 5% or more. 3. The gate insulating film has an internal pressure of 1.
3. The method for manufacturing an insulated gate field effect transistor according to claim 1, wherein the method is performed at less than 0 Pa. 4. The insulated gate electric field according to claim 1, wherein at least a part of a channel region of the insulated gate field effect transistor is made of a non-single-crystal semiconductor. Method for manufacturing effect transistor.