JP2867775B2 - Method for manufacturing semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor memory, and more particularly to an SRAM (MOS static ran).
dom access memory).

[0002]

2. Description of the Related Art A flip-flop type static memory cell has two high resistances and four N-channel MOSFEs.
T. As shown in the equivalent circuit diagram of FIG. 3, one drain of a pair of drive MOSFETs Q ₁ and Q ₂ is connected to the other gate, and load resistances R ₁ and R ₂ are connected to the respective drains. Source of Q _1, Q ₂ is fixed to the ground potential, the power supply voltage V _CC is applied to the other end of R _1, R _2, the flip-flop circuit consisting of _{Q 1, Q 2, R 1} , R 2 It supplies a very small current.
Transfer transistors Q ₁ and Q ₂ are connected to storage nodes N ₁ and N ₂ of the flip-flop circuit. Thus, a 1-bit memory cell has four transistors Q ₁ ,
It consists of Q ₂ , Q ₃ , Q ₄ and two load resistors.

Further, a word line 11 and a data line 12
a, 12b are connected, and the storage nodes N ₁ and N _2
1 and C ₂ are added. Normally, load resistances R ₁ , R ₂
Is a high-resistance polysilicon.

Next, an equivalent circuit diagram and FIG. 4D which is a sectional view corresponding to FIG. 3 will be described. The gate electrodes 3a and 3b of the MOSFET are made of a first conductive film, and the ground wiring 8 is made of a second conductive film. High resistance polysilicon 10a which is a part of the polysilicon which is a third conductive film is in the load resistor R _1, R _2. High resistance polysilicon 10a
At both ends are low-resistance polysilicons 10b and 10c.

The low resistance polysilicon 10c is connected to the power supply voltage V _CC
And the low-resistance polysilicon 10b is connected to the transfer MOSF
It is connected to the ET source 4b. Driving MOSFET
Is connected to a ground potential V _SS by a ground wiring 8. The data line 11 is connected to the drain 4c of the transfer MOSFET.

Next, a method of manufacturing a ground wiring will be described with reference to FIG.
This will be described with reference to (a) to (c).

First, as shown in FIG. 4A, a field oxide film 2 for element isolation is formed on a P-type silicon substrate 1 by LOCOS selective oxidation. Next, the gate oxide film 2
a, 2b and gate electrodes 3a, 3b are formed, and the source-drain 4a, 4b, 4c is formed by ion implantation using the gate electrodes 3a, 3b as a mask.
100 nm thick CV to be an interlayer insulating film (capacitive insulating film)
A D oxide film 5 is deposited. Next, the CVD oxide film 5 is etched using a photoresist (not shown) as a mask,
After opening a contact 7 for connecting the source 4a of the drive MOSFET and a ground wiring to be formed later, the photoresist is removed using nitric acid or O ₂ plasma.

Next, as shown in FIG. 4B, a thin oxide film (not shown) formed on the contact 7 at the time of removing the photoresist is etched with dilute hydrofluoric acid, and then a 400 nm-thick poly is formed on the entire surface. Silicon 6 is deposited.

Next, as shown in FIG. 4C, the polysilicon 6 is etched using a photoresist (not shown) as a mask to form a ground wiring 8, and then the photoresist is removed.

[0010]

FIG. 3 and FIG. 4 (d)
Driving MOSFET of static memory cell shown in
MOS by the PN junction capacitance between the drains 4c of Q ₁ and Q ₂ and the P-type silicon substrate 1 and the gate oxide film 2b
The capacity decreases as the memory cell area decreases. If the accumulated charge becomes insufficient to compensate for the charge disappearance due to α-rays, soft errors increase. Therefore, the CVD oxide film 5, which is a capacitance insulating film between the ground wiring 8 and the gate electrode 3a, is thinned to increase the amount of charge stored in the capacitance element, thereby suppressing soft errors due to α rays.

As the capacitance insulating film becomes thinner, the following problems occur. After the capacitive insulating film 5 is grown on the gate electrodes 3a and 3b, the capacitive insulating film is etched using a photoresist as a mask, and a contact 7 for connecting the source 4a of the drive MOSFET and the ground wiring 8 is opened. Next, the photoresist is removed using nitric acid or O ₂ plasma. At this time, the thin oxide film formed on the surface of the silicon substrate 1 at the opening of the contact 7 is etched with dilute hydrofluoric acid. When the capacitor insulating film 5 is sufficiently thick, there is no problem if the capacitor insulating film 5 is etched at the same time as the oxide film with a thin contact opening. However, when the capacitor insulating film 5 becomes about 30 nm thick, it is etched by dilute hydrofluoric acid. The variation in the thickness of the capacitor insulating film 5 cannot be ignored. The variation in the film thickness causes a deterioration in the interlayer breakdown voltage, which causes a decrease in the yield.

On the other hand, if a nitride film having a large relative dielectric constant, which can increase the film thickness and increase the withstand voltage to obtain the same capacitance, is used as the capacitor insulating film, the following problem arises. Since the nitride film has many pinholes, oxidation of the nitride film is usually performed in an O ₂ atmosphere at 900 ° C. for several tens of minutes. At this time, since the thickness of the oxide film formed by oxidizing the surface of the nitride film is several nm, the capacity increases, but dilute hydrofluoric acid etching for removing the thin oxide film formed in the contact opening cannot be performed.

[0013]

According to the method of manufacturing a semiconductor memory of the present invention, a gate electrode is formed on one main surface of a semiconductor substrate, and a capacitor insulating film and a first conductive film are sequentially deposited on the entire surface. A step of selectively etching the first conductive film and the capacitor insulating film to form an opening exposing a portion of the semiconductor substrate surface; and depositing a second conductive film over the entire surface; Selectively etching the first conductive film and the second conductive film to form a ground wiring connected to the surface of the semiconductor substrate through the opening.

[0014]

FIG. 1 (a) shows a first embodiment of the present invention.
This will be described with reference to FIGS.

First, as shown in FIG. 1A, a field oxide film 2 for element isolation is formed on a P-type silicon substrate 1 by LOCOS selective oxidation. Next, the gate oxide film 2
a, 2b and gate electrodes 3a, 3b are formed, and the source-drain 4a, 4b, 4c is formed by ion implantation using the gate electrodes 3a, 3b as a mask.
A 40 nm thick CVD oxide film 5 serving as a capacitance insulating film and a 200 nm thick polysilicon 6 are deposited.

Next, as shown in FIG. 1B, the polysilicon 6 and the CVD oxide film 5 are etched using a photoresist (not shown) as a mask to form a drive MOSFET.
After opening a contact 7 for connecting the source 4a to the ground wiring formed later, the photoresist is removed using nitric acid or O ₂ plasma.

Next, as shown in FIG. 1 (c), a thin oxide film (not shown) formed on the contact 7 at the time of removing the photoresist is etched with dilute hydrofluoric acid, and the entire surface is again formed to a thickness of 200 nm. Polysilicon 6 is deposited.

Next, as shown in FIG. 1D, the polysilicon 6 is etched using a photoresist (not shown) as a mask, and then the photoresist is removed. At this time, a capacitor (capacitor) is formed between the ground wire 8 and the gate electrode 3b at the same time when the ground wire 8 made of the polysilicon 6 is formed.

Next, a second embodiment of the present invention will be described with reference to FIGS.

First, as shown in FIG. 2A, a field oxide film 2 for element isolation, gate oxide films 2a and 2b, and gate electrodes 3a and 3b are formed on a P-type silicon substrate 1 in the same manner as in the first embodiment. Are formed, the source-drain 4a,
4b and 4c are formed. Next, the thickness 4 to be the capacitance insulating film
A 0 nm CVD oxide film 5 and a 200 nm thick polysilicon 6 are deposited.

Next, as shown in FIG. 2B, the polysilicon 6 and the CVD oxide film 5 are etched using a photoresist (not shown) as a mask to form a drive MOSFET.
After opening a contact 7 for connecting the source 4a to the ground wiring formed later, the photoresist is removed using nitric acid or O ₂ plasma.

Next, as shown in FIG. 2C, a thin oxide film (not shown) formed on the contact 7 at the time of removing the photoresist is etched with dilute hydrofluoric acid, and then a tungsten film having a thickness of 200 nm is formed on the entire surface. A silicide 9 is deposited.

Next, as shown in FIG. 2D, the tungsten silicide 9 and the polysilicon 6 are etched using a photoresist (not shown) as a mask, and then the photoresist is removed. At this time, a ground wire 8 made of polysilicon 6 and tungsten silicide 9 is formed, and at the same time, a capacitor is formed between ground wire 8 and gate electrode 3b.

In this embodiment, since the ground wiring 8 has a polycide structure, the layer resistance can be reduced as compared with the case where only the polysilicon is used.

CV which has been used as a capacitive insulating film
The same effect can be obtained by using an insulating film made of a nitride film or the like instead of the D oxide film. Also, a metal film can be used as the ground wiring instead of polysilicon or polycide.

[0026]

According to the present invention, the distance between the gate electrode and the ground wiring is 30 nm.
When forming a thin capacitive insulating film, the capacitive insulating film is covered with a conductive film constituting a ground wiring. Therefore, even if the silicon substrate surface in the contact opening is etched with dilute hydrofluoric acid, the capacitance insulating film is not etched. Therefore, a thin capacitive insulating film can be formed with high uniformity, and the production yield and element performance can be improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a first embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view showing a second embodiment of the present invention in the order of steps.

FIG. 3 is an equivalent circuit diagram showing a static memory cell.

FIG. 4 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor memory.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 P-type silicon substrate 2 Field oxide film 2a, 2b Gate oxide film 3a, 3b Gate electrode 4a Source of drive MOSFET 4b Source of transfer MOSFET 4c Drain of transfer MOSFET 5 CVD oxide film 6 Polysilicon 7 Contact 8 Ground wiring 9 Tungsten silicide 10a, 10b, 10c resistance polysilicon 11 data lines Q _1, Q ₂ drive MOSFET Q _3, Q ₄ transfer MOSFET R _1, R ₂ load resistor N _1, N ₂ storage node V _CC supply voltage C _1, C ₂ additional capacitor

Claims (1)

(57) [Claims] A step of forming a gate electrode on one main surface of a semiconductor substrate; a step of sequentially depositing a capacitive insulating film and a first conductive film over the entire surface; Forming an opening exposing a part of the semiconductor substrate surface, selectively depositing a second conductive film over the entire surface, and forming the first conductive film and the second conductive film on the entire surface.
Selectively etching the conductive film to form a ground wiring connected to the surface of the semiconductor substrate through the opening.