JP3144004B2 - Conditional branch processing unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a new conditional branch processing apparatus which does not cause a delay in processing time when a conditional branch instruction is processed in the same number of cycles as other instructions (sequentially executable instructions). It is intended to provide.

[0002]

2. Description of the Related Art The basic function of a control center in a computer is to fetch an instruction, decode the instruction, and execute the instruction. For this purpose, the CPU includes a control unit and an arithmetic unit.

The control structure of the program includes sequential control for processing instructions in order, and conditional branching control for selectively performing processing according to whether a specified condition is satisfied or not satisfied.

That is, if the instruction is an instruction that can be executed successively, the CPU processes the instruction in order, and if the instruction is a conditional branch instruction, the status (state value) relating to the operation result of the ALU (arithmetic logic circuit). ) To select whether to jump to the destination address or to shift to the next instruction, and change the processing flow.

When pipeline processing is performed using a plurality of CPUs that execute such instructions, it is preferable from the viewpoint of processing efficiency and processing time to make the execution steps per stage the same and shorten the length. It has been.

FIG. 4 shows a flow of a conventional program processing.

In the figure, a is an ALU, and the status output of the operation result is stored in a status register b and then sent to a two-input AND gate c.

Reference numeral d denotes a multiplexer, which is an address (program counter) value (indicated by "INC" in the figure) incremented (+1) in accordance with a signal from the AND gate c and a jump destination from a pipeline register described later. The address is selectively switched and transmitted to the microprogram memory e as the read address.

The instruction read from the microprogram memory e is temporarily stored in a pipeline register f, and an operation unit (a part for instructing the processing content) constituting the instruction is sent to an AND gate c to receive a status and AND operation is performed, and when the instruction is a conditional branch instruction, the value of the address portion is sent to the multiplexer d as it is.

FIG. 5 shows a case where the target instruction is not a conditional branch instruction (see FIG. 5 (a)) and a case where the target instruction is a conditional branch instruction (see FIG. 5 (b)). FIG. 9 is a time chart showing the relationship between the operation and the conditional branch processing, where “CL” is a clock signal, “AL” is an operation state, “ST” is a status output, and “RD” is a read and execution timing of a micro instruction. Represents. A
The operation by the LUa is performed by using the clock signal C as shown by hatching.
It starts from the rise of the pulse at L and ends between the fall of the pulse and the rise of the next pulse.

In this case, in order to execute each microinstruction in one timing (or clock) cycle, it is necessary to read the instruction within one cycle of the clock signal.

That is, for an instruction that does not branch conditionally,
As shown in FIG. 5A, the reading from the microprogram memory e is started from the rising edge of the clock pulse, and the reading is completed and started to be executed by the rising edge of the next pulse. It is possible to shift to reading of the next instruction at the rising timing of the subsequent pulse without delay.

However, in the case of the conditional branch instruction, FIG.
As shown in (b), the reading of the corresponding instruction must be started based on the status after the operation.

Therefore, as shown in the figure, if the reading is performed up to the rising edge of the subsequent pulse, it becomes impossible to proceed to the reading of the next instruction at the timing of the rising edge of the subsequent pulse.
Cycle time will be required.

[0015]

As described above, in the conventional conditional branch processing, the instruction to be executed next is read after waiting for the status relating to the operation result of the ALUa. As a result, there is a problem that the processing takes a long time. For example, when a large amount and high-speed processing is required as in the case of image data, there is an inconvenience that the processing is time-consuming.

In order to process a conditional branch instruction and an instruction not having the same number of cycles, the conditional branch instruction is composed of an instruction relating to an operation and an instruction relating only to a branch.
As shown below, List 1) Address Instruction Comment A10 (AB), LD ZR; Based on the operation result of (AB); Status of ZR (zero flag); Load to register A11 CJP LL; ZR = 1 If so, go to the label (LL). A12 XXXXXX; any instruction A13 LL: CONT; go to next step A14 YYYYYY; any instruction It is conceivable to write a program in the program or to lower the clock frequency. In any case, the entire conditional branch (operation +
This does not necessarily shorten the processing time required for branching.

Further, in the former case, the number of execution steps per stage in the pipeline processing increases, resulting in a disadvantage that the processing efficiency deteriorates.

[0018]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a conditional branch processing apparatus which selects either an incremented address or an unconditional jump destination address specified by a register. (1) a main memory for storing a microinstruction, reading an instruction in response to an address designation by the first selection means, and a microinstruction corresponding to a jump address included in a conditional branch microinstruction , And the switching of the incremented address and the unconditional jump destination address in the first selection means, and temporarily stores a microinstruction consisting of a conditional branch instruction, an unconditional branch address, and a conditional branch address. Registers and
One of the microinstructions read from the main memory and the sub memory is used to determine the operation result of the ALU (arithmetic logic circuit).
Selected according to task, and a second selecting means for delivering to the register, in one cycle period of the clock, A
During the execution of the operation related to the condition determination of the LU (arithmetic logic circuit) , micro instructions corresponding to a plurality of jump addresses corresponding to the unconditional branch address and the conditional branch address of the register are read from the main memory and the sub memory, respectively. , ALU in the state of the status in the one calculation result of (arithmetic logic circuit), sent to register by selecting a micro instruction read from the main memory, also, ALU (arithmetic logic times
The micro-instruction of the sub-memory is selected and sent to the register when the status of the operation result of the ( path) is in another state.

[0019]

According to the present invention, when executing a conditional branch instruction including a plurality of address parts indicating a branch destination, an ALU (arithmetic logic)
Ma of the jump destination address during the operation in accordance with the conditions judgment of management circuit)
The micro instruction is read out from the main memory and the sub memory in advance, and the instruction is selectively executed in accordance with the result of the condition determination. And the conditional branch instruction can be executed in the same number of cycles as an instruction that can be executed successively, so that the number of execution steps involved in forming the conditional branch instruction into two instructions, an operation instruction and a branch instruction, is reduced. There is no increase or decrease in processing efficiency.

[0020]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a conditional branch processing apparatus according to the present invention.

FIG. 1 shows a flow of a program process relating to the conditional branch processing device 1. A plurality of microprogram memories are provided, and these are selectively switched and used according to the status in controlling the conditional branch. As a result, it is possible to shift to the execution of the next instruction without delay.

Reference numerals 2 (1) and 2 (2) denote multiplexers. The multiplexer 2 (1) at the preceding stage receives an operation part of a conditional branch instruction executed in the pipeline register 3 as a switching control signal, and outputs an address after increment. Alternatively, one of the branch addresses stored in the pipeline register 3 is selected and sent as an address signal to the microprogram memory 4A.

The two microprogram memories 4
A and 4B have the same size (bit width).
A is a main memory, and 4B is a sub memory.

The multiplexer 2 (2) receives the status of the operation result of the ALU 5 as a switching control signal, selects an instruction read from the microprogram memories 4A and 4B, and sends it to the pipeline register 3.

A microinstruction is temporarily stored in the pipeline register 3. In the figure, an operation section (CJA.) And two address sections (PO, A) are shown.
11) is stored.

That is, when the operation section is sent as a control signal to the multiplexer 2 (1) and the address of the conditional branch instruction is A10, the address (A11) next to the conditional branch instruction in the address section is the multiplexer. 2 (1), and the jump address (PO) of the conditional branch instruction in the address portion is transmitted as an address signal to the microprogram memory 4B.

FIG. 2 shows the timing of conditional branch processing when the following program is assumed.

List 2) Address Instruction Comment A10 (AB), LD ZR CJA. PO A11; Performance of (AB); Based on calculation result; Load ZR (zero flag) value; If ZR = 1; To label (LL) A11 XXXXXX; Optional instruction A12 ZZZZZZ; Optional instruction A13 LL: CONT; shift to next step A14 YYYYYY; arbitrary instruction In other words, in this example, the status (ZR) is obtained according to the register operation result of (A-B) in A10, and in response to this, the instruction of the subsequent step A11 or PO The instruction of A13 indicated as an address is selectively executed.

In FIG. 2, "CL" is a clock signal, "BR"
Indicates the execution state of the operation and conditional branch instruction, "ST" indicates ZR status output, "RMA" indicates the read state of microprogram memory 4A, "RMB" indicates the read state of microprogram memory 4B, and "EX" indicates the status. This shows the execution state of the instruction selected accordingly.

As shown in the figure, the instruction of A10 read from the microprogram memory 4A is executed by the pipeline register 3, and when the operation (AB) is being executed, two instructions to be executed next are both executed. Be led.

That is, the instruction A11 is read from the microprogram memory 4A, and the instruction A13 is read from the microprogram memory 4B.

At this time, the instruction of A10 executed by the pipeline register 3 includes an operation section "CJA."
It consists of two address parts "PO" and "A11", PO is sent as a read address to the microprogram memory 4B, and "A11" is sent to the multiplexer 2 (1) as an unconditional jump destination address. .

The operation section indicating that the instruction is a conditional branch instruction is sent as a control signal to the multiplexer 2 (1), whereby the address signal A11 is selected.

When the instruction to be executed is an instruction that can be executed sequentially, the incremented address is selected in the multiplexer 2 (1).

Thereafter, based on the result of the operation (AB) by the ALU 5, the ZR status is changed to the value of the multiplexer 2.
When the signal is output to (2), the multiplexer 2 starts from this point.
The instruction is selected when the time τ required for the switching of (2) has elapsed.

That is, when the value of the ZR status is 1, the instruction indicated by the address PO (in this example, the instruction "CONT" of A13 is added with the unconditional jump instruction "JMP A14" to the next step A14) Is loaded into the pipeline register 3 and executed. When the value of the ZR status is 0, the instruction of A11 (in this example, “XXXXXX”) is executed after being loaded into the pipeline register 3.

In any case, the reading of the selected instruction has been completed by the rise of the subsequent clock pulse, and the selected instruction is loaded into the pipeline register 3 in synchronization with the subsequent clock pulse. , The next instruction can be read.

It should be noted that the microprogram memory 4B is used only for conditional branch processing, and therefore, after execution of an instruction read from the microprogram memory 4B, the processing is always transferred to the microprogram memory 4A which is the main memory.

FIG. 3 conceptually shows the relationship between the status related to the list 2) and the branch processing.

In the conditional branch processing according to the present invention, the instructions at the two branch addresses relating to the conditional branch instruction are read out in advance during the operation, and when the status of the operation result is output, one of the instructions is output. Since it is selected and executed, there is no delay in processing that occurs when an execution instruction is read after the status of the operation result is obtained as shown in FIG. 5B.

Therefore, assuming that the time required for executing an instruction that can be sequentially executed is one cycle, the execution of the conditional branch instruction and the instruction after the branch requires two cycles, so that the instruction is executed in one cycle per instruction. The number of cycles can be matched between the conditional branch instruction and the other instructions.

[0042]

As is apparent from the above description, according to the present invention, when a conditional branch instruction including a plurality of address parts indicating a branch destination is executed, the next execution instruction is executed during the operation related to the conditional judgment. Is read in advance from the main memory and the sub memory, and instructions are selectively executed in accordance with the result of the condition determination. Therefore, there is no time delay that occurs when reading the corresponding instruction after waiting for the result of the condition determination as in the related art. Since the conditional branch instruction can be executed in the same number of cycles as other sequentially executable instructions, the number of execution steps caused by dividing the conditional branch instruction into two instructions, an operation instruction and a branch instruction, can be increased. There is no reduction in processing efficiency.

The above embodiment is merely an embodiment of the present invention, and the technical scope of the present invention should not be construed as being narrow only by this embodiment. For example, in the above-described embodiment, two microprogram memories are used in the conditional branch processing, and any one of the instructions read from these is selected and executed. However, the present invention is generally applied to a multiple branch processing using a plurality of memories. can do.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a conditional branch processing device according to the present invention.

FIG. 2 is a time chart for explaining a conditional branch process according to the present invention.

FIG. 3 is an explanatory diagram conceptually showing the relationship between status and branch processing.

FIG. 4 is a block diagram showing a configuration of a conventional conditional branch processing device .

5A and 5B are time charts for explaining a conventional conditional branching process, wherein FIG. 5A shows a processing status of sequentially executable instructions, and FIG. 5B shows a processing status of a conditional branch instruction.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Conditional branch processing device 2 (1) 1st selection means 2 (2) 2nd selection means 3 Register 4A Main memory 4B Sub memory 5 Arithmetic logic circuit

Continuation of the front page (56) References JP-A-60-181930 (JP, A) JP-A-57-75355 (JP, A) JP-A-1-162930 (JP, A) JP-A-62-182402 (JP) JP-A-57-75355 (JP, A) JP-A-3-152625 (JP, A) JP-A-2-266432 (JP, A) JP-A-3-33930 (JP, A) 58-68157 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G06F 9/30-9/42

Claims (1)

(57) [Claims] 1. A first selecting means for selecting either an incremented address or an unconditional jump destination address specified by a register, and storing a microinstruction and specifying an address by the first selecting means. A main memory from which an instruction is read upon receipt; a sub-memory for storing only a microinstruction corresponding to a jump address included in the conditional branch microinstruction; an incremented address and an unconditional address in the first selecting means; A register for controlling the switching of the jump destination address and temporarily storing a microinstruction consisting of a conditional branch instruction, an unconditional branch address, and a conditional branch address; and a microinstruction read from the main memory and the sub memory. ALU (arithmetic logic circuit)
2nd selected according to the status and sent to the register
And ALU (calculation unit) within one cycle of the clock.
Micro-instructions corresponding to a plurality of jump addresses corresponding to the unconditional branch address and the conditional branch address of the register are read from the main memory and the sub-memory, respectively, during the execution of the operation relating to the condition determination of the logic circuit). , in the state of the status in the one calculation result of the ALU (arithmetic logic circuit) selects the micro instruction read from the main memory and sent to the register, also, the ALU
A conditional branch processing device, wherein the micro-instruction of the sub-memory is selected and sent to the register when the status of the operation result of the (arithmetic logic circuit) is in another state.