JP3144825B2 - Output buffer circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer circuit, and more particularly to an output buffer circuit connected to an external input / output terminal.

[0002]

2. Description of the Related Art Conventionally, an N-channel MOSFET is provided at the last stage of an output buffer circuit of a semiconductor memory device such as a DRAM.
Have been used in series. This circuit will be described with reference to the drawings.

FIG. 5 shows an NMO at the last stage of an output buffer circuit.
Block diagram of the input and output portions of the semiconductor memory device using the S type buffer circuit, FIG. 6 shows a cross-sectional view of the final stage 35 of the output buffer circuit in FIG. 2 in the figure
Output data line pairs 1 and 22 are electrically complementary. 23
Is an output amplifier composed of a differential amplifier or the like, 46 and 35 are output buffer circuits, and especially 35 is the last stage of the output buffer circuit. 9 is a data input / output line, 25 is an external terminal, 2
6 is an input buffer circuit, 27 is an input amplifier, 28 and 29
Is an electrically complementary input data line pair. 7 is a power supply line, 10 is a ground line, 14 is a source and a drain of an N-channel MOSFET, 15 is a P-type silicon substrate, 16
Is an isolation region, and 51 is a source and a drain of the N-channel MOSFET.

First, the operation of this circuit will be described. Figure
5 , the output data line pair 21, 22 is connected to the output amplifier 23.
Are connected to the output buffer circuits 46 and 35 via the.
Output data pairs appearing on the output data line pairs 21 and 22 are output from the output buffer circuit 46 at a certain timing.
One is connected to the first N-channel MOSFET 47 in the final stage 35 of the output buffer circuit via the first control line 49,
The other is connected via a second control line 50 to a second N-channel MOSFET 48 in the final stage 35 of the output buffer circuit.
Is output to Here, when the output data line 21 is at the high level, the first control line 49 is at the high level, the first N-channel MOSFET 47 is turned on, the external terminal 25 is at the high level, and conversely, the output data line 21 is at the high level. When the signal is at the low level, the second control line 50 is at the high level, the second N-channel MOSFET 48 is turned on, the external terminal 25 is at the low level, and data is output to the outside. On the other hand, at the time of data input, the data input from the external terminal 25 is input to the input data line pair 2 by the input buffer circuit 26 and the input amplifier 27.
Transfer to 8 and 29.

However, the final stage 35 of the output buffer circuit
The first and second control lines 49 and 50 connected to the gate electrodes of the N-channel MOSFETs 47 and 48 have a logic amplitude equal to or higher than a ground potential (hereinafter VSS (TYP.)) And a power supply potential (hereinafter VCC).
(TYP.)) In the following cases, when the output data is at a high level, that is, when the potential of the first control line 21 is VCC (TYP.), The external terminal 25 is connected to the first N channel from VCC (TYP.). MOSFET
There is a problem that a potential lower by 47 Vth appears.

Therefore, conventionally, a booster circuit is provided in the output buffer circuit 46 so that the potential of the external terminal 25 becomes VCC (TYP.) When the output data is at a high level. Is solved by boosting the first control line 49 connected to the gate electrode of the first N-channel MOSFET 47 to a high potential of VCC (TYP.) + Vth or more. However, the first control line 49
Requires a certain amount of time to boost the voltage, which causes a problem that the time required for data output becomes longer.

When the logical amplitudes of the first and second control lines 49 and 50 are between VSS (TYP.) And VCC (TYP.), The external terminal 25 is inactive when the output data is at a high level. To VCC
The problem that the potential of (TYP.)-Vth appears and the problem that if the first control line 49 is boosted to solve the above problem, the time required for output becomes longer, The final stage 35 is made CMOS, that is, the first stage
N-channel MOSFET 47 is replaced with P-channel MOS
Although the problem is solved by using an FET, an NMOS type buffer circuit is used as in the past even when the peripheral circuit is changed to CMOS. The reason is that when the external terminal connected to the output buffer circuit is used for both data input and output, the potential at the time of high level of the input data is higher than VCC (TYP.) (For example, the input VCC (TY), which is the absolute maximum rating on the high voltage side of the voltage (hereinafter VIN)
P.) + 2 (V)), the last stage of the output buffer circuit is C
In the case of a MOS buffer circuit, a forward diode current flows from the drain node of the P-channel MOSFET constituting the MOS buffer circuit toward the N-well, and this current may trigger an element destruction such as latch-up. Because there is.

[0008] Figure 7 above, it will be described with reference to FIG. Figure 7 is a block diagram of the input and output portions of the fully CMOS of semiconductor memory device, FIG. 8 shows a cross-sectional view of the final stage 36 of the output buffer circuit in FIG. Figure
7 and 8 , those having the same functions as those in FIGS. 5 and 6 are denoted by the same reference numerals and description thereof is omitted. The difference is the figure
5 first to the N-channel MOSFET47 and P-channel MOSFET1 of, to change the function of the output buffer circuit 46 of the accompanying Figure 5 it is an output buffer circuit 24, first and second control lines in FIG. 5 which is the output line 49, 50
Are the first and second control lines 4 and 6, respectively. Reference numeral 11 denotes a source and a drain of a P-channel MOSFET, and reference numeral 12 denotes an N well.

First, the operation of this circuit will be described. Figure
7 , the output data line pair 21 and 22 is connected to the output amplifier 23.
Are connected to the output buffer circuits 24 and 36 via the.
The output data pairs appearing on the output data line pairs 21 and 22 are output from the output buffer circuit 24 at certain timings.
One is connected to the P-channel MOSFET 1 in the final stage 36 of the output buffer circuit via the first control line 4, and the other is connected to the final stage 36 of the output buffer circuit via the second control line 6.
Is output to the N-channel MOSFET 3 inside. At this time, the first and second control lines 4 and 6 are connected to the output buffer circuit 24.
At the time of output, they are electrically in-phase, and there is no particular step-up. Here, when the output data line 21 is at the high level, the first control line 4 goes to the low level,
When the channel MOSFET 1 is turned on and the external terminal 25 is at a high level (potential is VCC (TYP.)), Conversely, when the output data line 21 is at a low level, the second control line 6 is at a high level and the N-channel When the MOSFET 3 is turned on, the external terminal 25 is at a low level (the potential is ground potential (hereinafter referred to as VSS (TY)).
P.))) and the data is output to the outside. On the other hand, at the time of data input, the data input from the external terminal 25 is supplied to the input buffer circuit 26 and the input amplifier 27 by the input data line pair 2.
Transfer to 8 and 29.

At this time, the external terminal 25 is connected to, for example, VSS (TYP.)-1 according to the DRAM product specification.
(V) to VCC (TYP.) + 2 (V) are allowed to be applied, and therefore, a through current is prevented from flowing to the VCC line or the VSS line in the final stage 36 of the output buffer circuit. For this purpose, the output buffer circuit 24 controls the first and second control lines 4 and 6 connected to the gate electrodes of the P-channel MOSFET 1 and the N-channel MOSFET 3 to a high level and a low level, respectively, at the time of data input.

FIG. 8 shows that the conventional P-type substrate 15
Is set to VSS (TYP.)-1 (V) or less.
The potential of the external terminal 25 becomes equal to or lower than VSS (TYP.), That is, the connection node 9 of the FET in the final stage 36 of the output buffer circuit.
Potential of VSS (TYP.) Becomes less, also drain node 14 and the potential of the N-channel MOSFET3 connected to a connection node 9 becomes below VSS (TYP.), And the drain node 14 and the P-type substrate 15 The PN junction formed between
No forward current flows.

However, when the potential of the external terminal 25 is VCC
(TYP.) Or more, the potential of the connection node 9 of the FET in the final stage 36 of the output buffer circuit becomes VCC (TYP.) Or more,
P-channel MOSFET connected to connection node 9
The potential of one drain node 11 becomes equal to or higher than VCC (TYP.). Further, since the potential of the N-well 12 constituting the P-channel MOSFET 1 is VCC (TYP.) Conventionally, a forward current flows through the PN junction formed between the drain node 11 and the N-well 12, and this current flows. There is a problem that a trigger may cause device destruction such as latch-up.

The above is the case where the N-well is provided on the P-type substrate, and the same applies to the case where the P-well is provided on the N-type substrate.

[0014]

As described above, an NMOS buffer circuit in which N-channel MOSFETs are connected in series is used for the last stage of the output buffer circuit of the semiconductor memory device, and the first stage of the last stage of the output buffer circuit is used. And the first and second control lines connected to the gate electrodes of the second N-channel MOSFET have a logic amplitude between VSS (TYP.) And VCC (TYP).
P.), when the output data is high level, that is, when the potential of the first control line is VCC (TYP.), VCC (TYP.) Is applied to the external terminal.
There is a problem that a potential of −Vth appears. Next, the above problem is solved by providing a booster circuit in an output buffer circuit, and when output data is input to the output buffer circuit and the level is high, the second The first control line connected to the gate electrode of one N-channel MOSFET is VCC (TYP.) + V
If the problem is solved by increasing the voltage to a high potential equal to or higher than th, there is a problem that the time required for data output is increased.

To solve these problems, the last stage of the output buffer circuit is formed of CMOS, that is, the first N-channel MOSFET is formed of P-channel MOSFET, but the peripheral circuit is formed of CMOS. Even now, an NMOS buffer circuit is used as before. The reason is that when the external terminal connected to the output buffer circuit also serves as data input and output, when the potential when the input data is high level is higher than VCC (TYP.), The last stage of the output buffer circuit In the case of a CMOS buffer circuit, N
This is because a forward diode current flows toward the well (or N-type substrate), and this current may trigger an element breakdown such as latch-up.

In view of the foregoing, it is an object of the present invention to provide an output buffer circuit capable of speeding up data output and preventing abnormal operation of elements constituting a circuit.

[0017]

According to the present invention, in an output buffer circuit connected to an output data line pair, a final stage of the output buffer circuit is connected to a power supply line (hereinafter referred to as V).
(CC line) and the gate electrode connected to the first control line.
A channel MOSFET, a first N-channel MOSFET having a gate electrode connected to a third control line, and a second N-channel MOSFET having a source node connected to a ground line (VSS line) and a gate electrode connected to a second control line. The first and second N-channel MOSFETs are connected in series.
Connect the connection node of the SFET to the external terminal for input and output,
At the time of data input, the first control line is at a high level.
The second control line is at a low level, and the third control line is
Becomes low level and the output data is
The first control line and the
When the second control line is at high level or low level,
Before the output data is input to the output buffer circuit, the third control line is boosted to a potential higher than the potential of the VCC line by Vth of the first N-channel MOSFET or more. .

[0018]

[0019]

According to the present invention, the first N
The gate electrode of the channel MOSFET than the potential of VCC line N-channel MOSFET threshold voltage (V th)
By connecting to the third control line which is boosted to a higher potential, the potential of the external terminal becomes VCC when high-level data is output, and the output data is boosted before being input to the output buffer circuit. Therefore, it is possible to prevent a delay in the access time due to the boosting time.

[0020]

FIG. 1 is a block diagram of an input / output unit of a semiconductor memory device according to a first embodiment of the present invention. FIG. 2 is a sectional view of a final stage 31 of the output buffer circuit shown in FIG. FIG.
1 and 2, components having the same functions as those in FIGS. 7 and 8 are denoted by the same reference numerals, and description thereof will be omitted. The difference is
N-channel MO of the P-channel MOSFET1 in FIG. 7
The point is that an N-channel MOSFET 2 whose gate electrode is newly connected to the third control line 5 is inserted between the SFETs 3 and the connection node of the two N-channel MOSFETs is connected to the external terminal 25 for input / output. 8 is P channel MO
A connection node between the SFET and the N-channel MOSFET,
Reference numeral 13 denotes a source and a drain of the N-channel MOSFET.

First, the operation of this circuit will be described. In FIG. 1, output data line pairs 21 and 22 are output amplifiers 23.
Are connected to the output buffer circuits 24 and 31 via the.
The output data pairs appearing on the output data line pairs 21 and 22 are output from the output buffer circuit 24 at certain timings.
One is connected to the P-channel MOSFET 1 in the final stage 31 of the output buffer circuit via the first control line 4, and the other is connected to the final stage 31 of the output buffer circuit via the second control line 6.
Is output to the second N-channel MOSFET 3 inside.
At this time, the first and second control lines 4 and 6 are electrically in-phase at the time of output from the output buffer circuit 24, and are not particularly boosted. Here, output data line 2
When 1 is at the high level, the first control line 4 goes to the low level, the P-channel MOSET1 turns on, the external terminal 25 goes to the high level via the first N-channel MOSFET 2, and conversely, the output data line 21 Is low level,
When the second control line 6 goes high, the N-channel MOS
When the FET 3 is turned on, the external terminal 25 goes low and data is output to the outside. On the other hand, at the time of data input, data input from the external terminal 25 is transferred to the input data line pairs 28 and 29 by the input buffer circuit 26 and the input amplifier 27.

At this time, as described above, the external terminal 25 is connected to VSS (TYP.)-1 (V) to VCC (TYP.) +
2 (V) is allowed to be applied. Therefore, in order to prevent a through current from flowing to the VCC line or the VSS line in the final stage 31 of the output buffer circuit, the P-channel MOSFET 1 and the The first and second control lines 4 and 6 connected to the gate electrode of the second N-channel MOSFET 3 are controlled by the output buffer circuit 24 to be at a high level and a low level, respectively.
The control line 5 connected to the gate electrode is also set to the low level.

As described above, according to this embodiment, it is not necessary to boost the first and second control lines 4 and 6 by forming the final stage 31 of the output buffer circuit into CMOS,
Therefore, the data output can be performed at a higher speed than the conventional NMOS type circuit, and according to FIG.
5 is VSS (TYP _.) -1 (V) to VCC (TYP.) + 2
(V), that is, the final stage 3 of the output buffer circuit.
The potential of the connection node 9 of the FET in 1 is VSS (TYP.)-1.
(V) to VCC (TYP _.) + 2 (V), and the first and second N-channel MOSs connected to the connection node 9
The potentials of the drain nodes 13 and 14 of the FETs 2 and 3 are set to VSS.
(TYP.)-1 (V) to VCC (TYP.) + 2 (V), the potential of the P-type substrate 15 is less than VSS (TYP.)-1 (V). 13, 14 and P-type substrate 15
The reverse bias is always applied to the PN junction formed between the PN junction and the forward direction current does not flow. When data is input, the first N-channel MOSFET 2 is turned off by the third control line 5, so that the P-channel MOSFET 2 is turned off.
1 does not exceed VCC (TYP.), And the potential of the N-well 12 constituting the P-channel MOSFET 1 is VCC (TYP.). The forward current does not flow through the PN junction formed as described above.

(Embodiment 2) FIG. 3 is a block diagram of an input / output unit of a semiconductor memory device according to a second embodiment of the present invention.
FIG. 4 is a sectional structural view of the final stage 32 of the output buffer circuit shown in FIG. 3 and 4, FIG.
Those having the same functions as those in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted. Hereinafter, only points different from the first embodiment will be described.

First, the first stage of the final stage 32 of the output buffer circuit
The gate electrode of the N-channel MOSFET 41
Are connected. At the time of data output, as in the first embodiment, if the output data line 21 is at a high level, the P channel M of the last stage 32 of the output buffer circuit is output.
OSFET1 turns on and the first N-channel MOSFET
The external terminal 25 goes high through T41. Here, output data such as a boosted predecode line used in an NMOS type drive circuit in a word line selection circuit is output to the third control line 42.
Before inputting to the Vths 4 and 32, the high-level potential becomes higher than the potential of the Vcc line by Vth of the first N-channel MOSFET 41.
A control line that is boosted to a higher potential is used. Therefore, when high-level data is output in the first embodiment, the potential of the external terminal 25 is VCC (TYP.)-Vth. In this embodiment, the potential of the external terminal 25 is V.
CC (TYP.).

As described above, according to this embodiment, the speed of data output can be increased as in the first embodiment, and the potential of the external terminal 25 becomes V when outputting high-level data.
CC (TYP.). According to FIG. 4, when data is input, as in the first embodiment, the last stage 32 of the output buffer circuit is used.
PN junction formed between the drain nodes 13 and 14 of the first and second N-channel MOSFETs 41 and 3 and the P-type substrate 15 and between the drain node 11 and the N-well 12 constituting the P-channel MOSFET 1 PN
No forward current will flow through the junction.

[0027]

[0028]

[0029]

[0030]

[0031]

[0032]

The above two embodiments are the case of providing the N-well to the P-type substrate, it is also in the same manner when provided with a P-well in N-type substrate reversed.

[0034]

The present invention as described above, according to the present invention, in addition to the latch-up prevention is boosting the gate electrode of the first N-channel MOSFET threshold voltage than the high potential of the N-channel MOSFET than the potential of VCC line By connecting to the third control line, the potential of the external terminal becomes VCC when high-level data is output, and the output data is boosted before it is input to the output buffer circuit. The delay in access time can be prevented, and the practical effect is great.

[Brief description of the drawings]

FIG. 1 is a block diagram of an input / output unit of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a sectional structural view of a final stage 31 of the output buffer circuit in FIG.

FIG. 3 is a block diagram of an input / output unit of a semiconductor memory device according to a second embodiment of the present invention;

FIG. 4 is a sectional structural view of a final stage 32 of the output buffer circuit in FIG. 3;

FIG. 5 shows an NMOS type buffer at the last stage of the output buffer circuit .
Block diagram of the input / output unit of the conventional semiconductor memory device using the

FIG. 6 is a cross-sectional structural view of the final stage 35 of the output buffer circuit in FIG. 5

FIG. 7 shows a CMOS type buffer at the last stage of the output buffer circuit .
Block diagram of the input / output unit of the conventional semiconductor memory device using the

FIG. 8 is a cross-sectional structural view of the final stage 3 6 of the output buffer circuit in FIG. 7

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 P-channel MOSFET 2 N-channel MOSFET 3 N-channel MOSFET 4 1st control line 5 3rd control line 6 2nd control line 9 Data input / output line 25 External terminal 31 Final stage of output buffer circuit 32 Output buffer circuit Last stage

Continuation of front page (56) References JP-A-62-76923 (JP, A) JP-A-64-70995 (JP, A) JP-A-3-289716 (JP, A)

Claims (1)

(57) [Claims] In an output buffer circuit connected to an output data line pair, a final stage of the output buffer circuit has a source node connected to a power supply line (hereinafter, VCC line) and a gate electrode connected to a first control line. P-channel MOSFET,
A series of a first N-channel MOSFET having a gate electrode connected to a third control line and a second N-channel MOSFET having a source node connected to a ground line (VSS line) and a gate electrode connected to a second control line. A connection node between the first and second N-channel MOSFETs is connected to an external terminal for input / output, and when data is input, the first control line is at a high level.
The second control line is at a low level, and the third control line is
Becomes low level and the output data on the output data line pair
Causes the first control line and the second control line to go high.
In phase level of the bell or a low level, before the output data is input to the output buffer circuit, the third control line is boosted to Vth or higher potential of the first N-channel MOSFET than the potential of VCC line An output buffer circuit characterized by: