JP3146522B2 - Nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more particularly to an electrically erasable programmable read-only memory capable of electrically erasing data stored in a memory transistor and writing new data. The present invention relates to a device (hereinafter referred to as an EEPROM).

[0002]

2. Description of the Related Art Conventionally, various researches and developments have been made on nonvolatile semiconductor memory devices which do not lose written data even when the power is turned off. In particular, in recent years, the development of the EEPROM has rapidly progressed, and various products have been put to practical use.

[0003] There are various types of EEPROMs, and in recent years, a configuration in which memory transistors are connected in series has been proposed (R. Shirota et al., Te.
chemical digest of 1988 sy
mposium on VLSI technology
y P33-P34).

FIG. 12 is an equivalent circuit diagram showing an example of a conventional nonvolatile semiconductor memory device. First, the conventional example shown in FIG. 12 will be described. The code Q ^s i, j (i = 1 to 2, j = 1 to
4) is a selection transistor, and the code Q ^M i, j (i = 1 to 2, j
= 1 to 6) are memory transistors. The control gate electrodes of the memory transistors Q ^Mi , j (i = 1,2, j = 1-6) are connected to word lines Xi (i = 1-6) for each row. Selection transistor ^{Q s i, j (i =} 1~2, j = 1~
4) The first one connected to the bit lines Y1 and Y2
For selection transistors (Q ^s 1, 1 in the figure, Q ^s 1,3, Q
^s 2,1 and Q ^s 2,3) have the first Z1,
Z3 is connected to a second selection transistor group connected to the S to a source line (Q ^s 1, 2 in the figure, Q ^s 14,
Q ^s 2, 2, the gate electrode of Q ^s 2, 4) is connected to the second select line Z2, Z4, respectively.

[0005] Each of the first selection transistor Q ^s 1,2~Q
^s 2,3 and three memory transistors Q ^M 1,1 to Q ^M 1,3, Q
^{M 1,4~Q M 1,6, Q M 2,1~Q} M 2,3, Q M and 2,3~Q ^M 2,4, the second selecting transistor Q ^s 1,2~Q ^s 2 and 4 form a set, and are hereinafter referred to as each set memory array configuration group. Connected in series between the bit lines Y1, Y2 and the source line S,
Bit lines Y1, Y2 are connected to the first drain electrode of the selection transistor Q ^s 1,1~Q ^s 2,3 of the memory array configuration group.

FIG. 13 is a plan view of a memory array configuration group formed between a bit line Y1 (Y2) and a source line S in a conventional example, and FIG. 14 is taken along AA 'of FIG. It is sectional drawing.

[0007] Figure 13, 21 denotes a semiconductor substrate in FIG. 14, 22a is a first select transistor Q ^s 1,1 (Q ^s 1,3
Drain region of ~Q ^s 2,3), 22b source region of the second selecting transistor ^{Q s 1,2 (Q s 1,4~Q s} 2,4), 22
impurity diffusion layer region c is to connect the transistors in series, 23a, 23b are first and second selection transistor Q ^s 1, 1, a gate insulating film of the Q ^s 1, 2, 4 is a memory transistor Q ^M 1 the first gate insulating film ^{1 (Q M 1,2~Q M 2,6)} , 25
Is the second of the memory transistors Q ^M 1,1 (Q ^M 1,2 to Q ^M 2,6)
The gate insulating film 26 is a memory transistor Q ^M 1,1 (Q
Floating gate electrodes of ^{M 1,2~Q M} 2,6), 27 is a control gate electrode of the memory transistor ^{Q M 1,1 (Q M 1,2~Q M} 2,6), 2
8a, 28b is a gate electrode of the selection transistor ^{Q s 1,1, Q s 1,2,} 29 denotes an interlayer insulating film, 30 denotes a contact hole, 3
Reference numeral 1 denotes a metal wiring constituting the bit line Y1 (Y2).

The structural characteristic of this nonvolatile semiconductor memory device is that the first gate insulating film 24 of the memory transistor Q ^M 1,1
Is thin, for example, 90 angstroms, and tunneling easily occurs between the floating gate electrode 26 and the semiconductor substrate 21 and between the floating gate electrode 26 and the source / drain electrodes. Therefore, in this conventional example, electrical writing and erasing are performed using this operation principle (tunneling).

Next, the operation of this nonvolatile semiconductor will be described with reference to FIG.
Predetermined memory array subassembly in ^{Q s 1,1, Q M 1,1,} Q M 1,
It is assumed that access is made to 2, Q ^M 1,3 and Q ^s 1,2.
Note that each transistor is an N-channel transistor. Table 1 shows the potentials of the bit line Y1, the first and second selection lines Z1, Z2, and the word lines X1, X2, X3 in the data erasing, data writing, and data reading modes in this case. Here, the units of the numerical values in the table are all volts (V).

[0010]

[Table 1]

In the following description, data erasing means injecting electrons into the floating gate electrode, while data writing means extracting electrons from the floating gate electrode.

First, a mode for erasing data will be described. First, the bit line Y1 and the source line S are set to the ground potential, and the word lines X1, X2, X3 are set to a positive high voltage, for example, 17.
Set to V. Since the first and second selection lines are set to 5 V, the channel potential of each memory transistor Q ^M 1,1, Q ^M 1,2, Q ^M 1,3 and the potential of the source and drain electrodes are 0 V
Fixed to At this time, each memory transistor Q ^M 1,1,
Due to the positive high voltage applied to the control gate electrodes 27 of Q ^M 1,2 and Q ^M 1,3, the electric field in the first gate insulating film 24 becomes strong, and an FN electron tunneling phenomenon occurs. Semiconductor substrate 2
1 and the impurity diffusion layer 22c, electrons are injected into the floating gate electrode 26 via the first gate insulating film 24, and the threshold of each of the memory transistors Q ^M 1,1, Q ^M 1,2, Q ^M 1,3 is set. The value voltage increases. This state is a state in which data has been erased. In this erase mode, there is no selectivity of the memory transistors, so that the data stored in all the memory transistors are erased at the same time.

Next, the data is stored in the memory transistors Q ^M 1,
The mode for writing to 1, Q ^M 1,2 and Q ^M 1,3 will be described. A bit line Y1, the memory transistor Q ^M 1, 1 to be written first select line Z1, and, Q ^M 1,2, the word lines of the memory transistors connected to the bit line Y1 side than the Q ^M 1, 3 X1 , X2, X3 are set to a positive high voltage, for example, 20V. At the same time, the memory transistor Q to be written
^M 1, 1, Q ^M 1, 2, and Q ^M 1, 3 and the word lines X1, X2, X3 of the memory transistors connected to the source line S side of the memory transistor, to the ground potential source line S I do. At this time, since the control gate electrode 27 of the memory transistor to be written is at the ground potential and the drain electrode of the memory transistor is at the positive high potential of 20 V, the first gate insulating film 24 of the memory transistor to be written is strong. An electric field is applied, and electrons are emitted from the floating gate electrode 26 of the memory transistor to be written to the impurity diffusion layer 22c by the FN electron tunneling phenomenon. At this time, the memory transistor in which a high voltage is applied to the control gate electrode 27 and the drain electrode functions only as a transfer transistor. However, since the electric field of the first gate insulating film 24 of the memory transistor in this bias state is small, the FN No tunnel phenomenon occurs.

In the memory transistor connected to the source line S rather than the memory transistor to be written,
The potential of the control gate 27 becomes the ground potential, but does not increase because the drain electrode potential is cut off by the memory transistor to be written. As a result, the electric field in the first gate insulating film 24 becomes small, and the FN electron tunnel phenomenon does not occur. Thereby, selective writing to the memory transistor is achieved.

When there are a plurality of memory transistors to be written, the memory transistors on the source side S are sequentially written to the plurality of memory transistors connected to one selection transistor Q ^s 1,1 by the above-described method. . This is to protect already written data due to electric field stress during writing of the memory transistor, that is, to prevent threshold voltage fluctuation.

[0016] Incidentally, at the time of writing of this data and the second selection line Z2 connected to the gate electrode of the second selecting transistor Q ^s 1, 2 need to be held at 0V. This is because even if the control gate electrode potential of the memory transistor is 0 V, the channel current flows in the case of the already-written memory transistor, so that this channel current is cut off.

Next, a case where data stored in the memory transistor is read will be described. In this mode, the bit line Y1 is set to 1V, and the first and second selection lines Z1, Z
2 is fixed to 5V. Further, only the word lines X1, X2, X3 connected to the memory transistors to be read are set to the ground potential, and all other word lines are set to 5V. When the selected memory transistor is in the erased state at this time, no current flows from the bit line Y1 to the source line S because the threshold voltage is positive. On the other hand, when the selected memory transistor is in a write state, a current flows from the bit line Y1 to the source line S because the threshold voltage is negative. All other unselected memory transistors act as transfer gates. From this operation mode, the threshold value of each memory transistor must be a control gate voltage, for example, 5 V
The following must be controlled:

Next, the four memory array configuration groups in FIG. 12 are referred to as memory transistors Q ^M 1,3, Q ^M 2,3, Q ^M 1,6, Q ^M 2,6
The bias state of the four memory array configuration groups in the write state will be described as a representative. At this time, each bit line Y
1, Y2, each word line X3, X6, first and second selection lines Z1
Table 2 shows the potentials of Z4.

[0019]

[Table 2]

The units of the numerical values in Table 2 are volts (V).

Now, the memory transistors Q ^M 1,3 and Q ^M 2,3
The control gate electrode 27 of the same word line X3, the memory transistor Q ^M 1, 6 and Q ^M same word line X6 is also the control gate electrode 27 2,6, are connected. Therefore, the selective writing of the memory transistors Q ^M 1,3 and Q ^M 2,3 and the memory transistors Q ^M 1,6 and Q ^M 2,6 is performed by the bit line Y.
This is performed by controlling the potential of 1, Y2.

Now, consider the case where the memory transistor Q ^M 1,3 is written and the memory transistor Q ^M 2,3 is not written. At this time, the memory transistor Q ^M 1,3 is in the above-described write bias state, but since the write is not desired to the memory transistor Q ^M 2,3, the bit line Y2
Are kept at an intermediate potential of 10V. As a result, the bias state of the memory transistor Q ^M 2,3 to the control gate electrode 0
V and 10 V are applied to the drain electrode.

The bias state of the memory transistors Q ^M 1,3 is 0 V applied to the control gate electrode and 20 V applied to the drain electrode, whereas the drain voltage of the memory transistors Q ^M 2,3 is as low as 10 V. , electric field applied to the first gate insulating film toward the memory transistor Q ^M 2,3 is smaller than the memory transistor Q ^M 1, 3. Thus the memory transistor Q ^M 2,3 will not lead to cause F-N electron tunneling, erroneous writing to the memory transistor Q ^M 2,3 will not occur.

The memory transistors Q ^M 2,1 and Q ^M 2,2 have a control gate electrode of 20V and a drain electrode of 10V.
Are in a bias state to be applied respectively. Since this state is also smaller than the potential difference applied between the control gate electrode and the drain electrode in the erase mode, the FN electron tunneling phenomenon does not occur, and the erasure of the non-selected memory transistor of the non-write bit line at the time of writing is performed. Does not wake up.

For the memory transistors Q ^M 1,6 and Q ^M 2,6, the word line X6 is biased to 0V, and the gate electrode of the drain electrode is fixed to 0V by the first selection line Z3. First selection transistor Q
^s 1, 3, the Q ^s 2,3, because it is disconnected from the bit line Y1, Y2, electric field stress is erased and erroneous writing erroneous not applied does not occur.

[0026] As is apparent from the above description, the memory transistor Q ^M 1,1~Q ^M 2,6 to share the word line X1~X6
In order to prevent erroneous writing, an intermediate potential such as 10 V is required. In addition, without using this intermediate potential, the bit line is
For example, if it is attempted to control only two voltages of 0V and 20V, erroneous writing of the memory transistor sharing the word line can be prevented, but erroneous erasing of the non-selected memory transistor connected to the non-writing bit line at the time of writing. Progress cannot be prevented. That is, the threshold value of the non-selected memory transistor connected to the non-write bit line is unintentionally increased. This phenomenon is particularly remarkable in a memory transistor close to a bit line. A problem arises as the number of memory transistors connected in series increases as the number of times of erasing during writing increases. For example, if the threshold value of the non-write transistor becomes higher than the voltage applied to the control gate electrode at the time of reading, erroneous reading of data will occur, resulting in a fatal defect.

From the above description, the conventional nonvolatile memory transistor (1) uses the FN electron tunneling phenomenon at the time of erasing and writing. (2) In addition to the memory transistors, two selection transistors are connected in series between the bit line and the source line. (3) At the time of writing, in order to prevent unintentional erasure of the unselected transistor, three voltages of high, middle and low are used for the bit line bias. Etc.

[0028]

However, as described above, the conventional non-volatile memory device requires three types of bit line bias potentials for selective writing, and requires an intermediate potential, a high potential and a low potential. Since the FN electron tunneling is controlled by the potential difference, the setting range of each voltage is narrowed. In particular, the setting of the voltage of the intermediate potential is a cause of a defect regardless of whether the voltage is high or low.

Further, the conventional non-volatile memory device has a problem of over-erasing, that is, a problem that the threshold value of the memory transistor rises above the control gate voltage at the time of reading. In addition, precise setting and control of the erasing voltage are required, and these also have a drawback that they limit the manufacturing method of the memory transistor and lower the manufacturing yield.

Further, since the FN tunneling phenomenon is used for both writing and erasing of the memory cell, a high positive voltage is required to execute the writing / erasing mode. For this reason, there is a disadvantage that a high breakdown voltage transistor using a high breakdown voltage junction needs to be used as the bit line control transistor and the word line control transistor.

Further, since writing and erasing to and from the memory transistor use only the FN tunneling phenomenon, the first gate insulating film 24 must be formed by growing an extremely thin silicon oxide film of, for example, 100 Å or less. In addition, it is difficult to control the thickness and quality of the insulating film, and there is a disadvantage that the production yield is reduced.

Further, since writing to a memory cell can be executed only serially from the source line S side, it is necessary to erase the memory cell once and then reprogram at the time of writing. This means that functions such as word erasing and word writing cannot be realized, and the time required for reprogramming is prolonged. Even if used as a large-capacity non-volatile memory, its use is extremely limited. Have.

The present invention has been made in view of the above problems, and does not require an intermediate potential in selective writing, can execute writing at a relatively low voltage, and does not cause problems of overwriting and overerasing. Non-volatile semiconductor memory device suitable for high integration, which has a wide voltage margin for writing and erasing, can make the first gate insulating film thick, and can realize word writing and word erasing functions. It is intended to provide.

[0034]

The gist of the present invention is to serially connect a plurality of transistor pairs each including a memory transistor having a floating gate and a control gate and a first selection transistor connected in parallel with the memory transistor. A memory array in which the grouped memory array components are arranged in a matrix, a first word line commonly connected to the control gates of the memory transistors each arranged in the same row direction position,
A plurality of second word lines respectively corresponding to the plurality of first word lines and commonly connected to a gate of a first selection transistor arranged at the same row direction position, and a plurality of columns of a memory array A plurality of bit lines respectively corresponding to the plurality of bit lines; a plurality of second selection transistors connected between the plurality of bit lines and one end of the memory array configuration group; A plurality of select lines provided correspondingly connected to the gates of the second select transistors of the memory array configuration group belonging to the same row;
And a source line connected to the other end of the plurality of memory array configuration groups.

[0035]

When writing and reading data to and from the memory cell transistor, the first selection transistor forming a pair with the selected memory transistor is turned off, and all the first selection transistors forming a pair with the unselected memory transistor are turned on. , Function as a transfer gate.

[0036]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a plan view showing a first embodiment of a nonvolatile semiconductor memory device of the present invention, and FIGS. 2 and 3 are AA 'and B- of FIG.
It is sectional drawing in alignment with B '. 4 to 7 also show FIG.
FIG. 4 is a sectional view similar to FIG.
It is sectioned along C ′, DD ′, EE ′, and FF ′.

In the drawing, 1 is a P-type semiconductor substrate of, for example, 13 Ωcm, 2a, 2b, 2c are first impurity diffusion layers doped with an N-type impurity such as AS, for example, and 3 are, for example, 300 μm thick. The gate insulating film of the first selection MOS transistor made of an angstrom silicon oxide film, and the first selection MOS transistor 4 made of polycrystalline silicon containing an impurity such as P (phosphorus) has a thickness of 3000 Å. The gate electrode 5 of the type transistor is, for example, a gate insulating film of a second selection MOS type transistor made of a silicon oxide film having a thickness of 300 Å, and 6 is, for example, polycrystalline silicon containing impurities such as P (phosphorus). The gate electrode 7 of the second selection MOS transistor having a thickness of 3000 Å made of, for example, a chemical vapor deposition method Therefore, the thickness was formed 2500
An interlayer insulating film made of a silicon oxide film of Å, 8a is an impurity diffusion layer of a first selection transistor having a thickness of 500 Å made of N-type polycrystalline silicon containing, for example, AS at a high concentration, and 8b is made of, for example, B
The first 500 angstrom thick P-type polycrystalline silicon layer containing (boron) or the like at a high concentration of 3 × 10 ¹⁶ cm ^-3
Is a channel region of the selection transistor.

Reference numeral 9 denotes a first gate insulating film of a memory transistor made of, for example, a silicon oxide film having a thickness of 120 Å, and reference numeral 10 denotes a memory transistor having a thickness of 2,000 Å made of polycrystalline silicon containing impurities such as P (phosphorus). The floating gate electrode for use 11 is, for example, a second gate insulating film of a memory transistor made of a silicon oxide film having a thickness of 200 Å, and 12 is made of, for example, polycrystalline silicon containing an impurity such as P (phosphorus). Is a control gate electrode for a memory transistor.

Reference numeral 13 denotes a metal wiring interlayer film made of BPSG or the like having a thickness of 1.0 μm, for example, which insulates the metal wiring from each other. Reference numeral 14 denotes a contact hole formed in the interlayer film 13.
Is a metal wiring made of, for example, Al having a thickness of 1.0 μm,
16 is a field insulating film made of, for example, a silicon oxide film having a thickness of 6000 Å, and 17 is, for example, AS
Etc. to a high concentration of 10 ²⁰ cm ^-2 and a thickness of 5000
It is polycrystalline silicon grown to Angstrom and embedded between memory transistors.

Now, the gate electrode 6 of the second selection MOS transistor is connected to each row in the cell array as shown in FIG. 1 and becomes a selection line.
The gate electrode 4 of the OS-type transistor is connected to each row in the cell array as shown in FIG. 1 and serves as a second word line.

In the cell array, the control gate electrode 12 is connected to each row as a first word line, as shown in FIG. 1, and the field insulating film 16 is formed by connecting the impurity diffusion layers 2a and 2c of each transistor to a column. Each is separated.

In this embodiment, in addition to the second selection MOS type transistor provided on the semiconductor substrate 1 and a plurality of memory transistors connected in series to the second selection MOS type transistor, A first selection MOS transistor is connected in parallel with each of the memory transistors. In addition, in order to prevent a planar cell occupation area from increasing, a first selection MOS transistor is stacked above the memory transistor, and polycrystalline silicon is used to prevent voids between cells during high integration. The film 17 is provided along the impurity diffusion layer 8a of the first MOS transistor for selection so as to fill a gap between cells.

Therefore, in the present embodiment, the first selection MOS type transistor 100 includes a source / drain region (hereinafter also referred to as 8a) comprising an impurity diffusion layer 8a on an insulating film, a polycrystalline silicon film 17, and a channel. Region 8b,
It comprises a gate insulating film 3 above the channel region 8b and a gate electrode 4 on the gate insulating film 3,
The drain region 8a and the channel region 8b are insulated and separated for each column. MOS transistor 11 for second selection
A contact hole 14 is opened in the drain region 2a of the series transistor group including zero and a plurality of memory transistors, and a metal wiring 15 serving as a bit line is connected. The source electrodes of the series transistor group are commonly connected to each other to form a source diffusion layer wiring 2b.

Next, the operation of this embodiment will be described with reference to an equivalent circuit diagram shown in FIG. The code Q ^s i, j (i = 1 to 2, j = 1 to
6) denotes a first selection transistor, which is denoted by Q ^M i, j
(I = 1 to 2, j = 1 to 6) are memory transistors. The memory transistor Q ^M i, j and the first selection transistor Q ^s i, j each make a pair, and these pairs are connected in series, for example, Q ^M 1,1, Q ^M 1,2. , Q ^M 1,3 and Q
One memory array configuration group consisting of ^s 1,1, Q ^s 1,2, and Q ^s 1,3 is formed. The memory cell array 800 is obtained by arranging the memory array configuration groups in a matrix. In the plan view of FIG. 1, the source diffusion layer 2a and the bit line
The layout is arranged so as to be shared by two memory array configuration groups.

The control gate electrode 12 of the memory transistor Q ^M i, j is connected to the first word line Xi (i = 1 to 6) for each row, and the first selection transistor Q ^s i, j Gate electrode 4 is connected to a second word line Zi (i = 1 to 6) for each row.
It is connected to the.

The drain electrodes 2a of the memory array components connected in series are connected to the bit lines Yi (i = 1 to 2) for each column, while the source electrodes 2b are commonly connected to the source line S. Have been. It is further connected to the gate electrode 6 each row of the second selection transistor ^{Q c i (i = 1~4)} , are controlled by select line (Ci (i = 1~2).

Next, referring to Table 3, typical memory transistors Q ^M 1,1, Q ^M 1,2, Q in the write mode will be described.
An example of the bias potential of each word line, each bit line, each selection line, and the source line when ^M 1,3, Q ^M 2,1, Q ^M 1,5, and Q ^M 2,5 are selected is shown. The units of the numerical values in Table 3 are volts (V).

[0048]

[Table 3]

In the description of the present embodiment, writing means increasing the threshold voltage of the memory transistor by injecting electrons into the floating gate electrode 10.
The writing in this example utilizes hot electron injection by a channel current. For example, when writing to the memory transistor Q ^M 1, 1 is, 6V through a selecting transistor Q ^c 1 to the drain electrode than the bit line Y1 of the second memory transistor Q ^M 1, 1 is applied to the control gate The electrodes are supplied with 10 V from the first word line X1.

On the other hand, the gate electrode of the memory transistor Q ^M 1, 1 a first selection transistor is connected in parallel paired with Q ^s 1, 1 is supplied 0V from the second word line Z1 I'm off. Therefore, the current path due to the voltage supplied from the bit line Y1 to the drain electrode is only the path passing through the memory transistor Q ^M 1,1.

On the other hand, another memory transistor Q in the memory array configuration group to which this memory transistor Q ^M 1,1 belongs.
The control gate electrodes of ^M 1,2 and Q ^M 1,3 are connected to the first word line X
2. All are fixed to 0V by X3. Also, the first selection transistors Q ^s 1,2, Q
The gate electrodes of ^s 1,3 are connected to the second word lines Z2, Z3 by 10
V, and these first selection transistors Q
^s 1,2 and Q ^s 1,3 are turned on.

Therefore, the selected memory transistor Q
The source electrode of ^M 1,1 is connected to these select transistors Q ^s 1,2,
Through Q ^s 1, 3, is connected to a source line S of the ground potential, a channel current flows from the bit line Y1 to the source line S.
As a result, hot electrons are generated in the channel portion of the memory transistor Q ^M 1,1 and electrons are injected into the floating gate electrode.

However, the voltage supplied to the control gate electrode of the other memory transistors Q ^M 1,2, Q ^M 1,3 in the selected same memory cell configuration group is 0 V, and the voltage between the source and drain electrodes is Is not written because there is almost no potential difference.

[0054] Similarly when writing the memory transistor Q ^M 1, 2 supplies the 10V from the selection line C1 to the second gate electrode of the selection transistor Q ^c 1, supplies 6V from the bit line Y1 to the drain electrode . To the control gate electrodes of the other memory transistors Q ^M 1,1, Q ^M 1,3 in the same memory array configuration group, 0 V is supplied from the first word lines X1, X3, and the other first selection transistors are used. transistor Q ^s 1, 1, to the gate electrode of Q ^s 1, 3 and supplies the 10V from the second word line Z1, Z3, the first word line to the control gate of the memory transistor Q ^M 1, 2, which are selected supplying 10V from the first gate electrode of the selection transistor Q ^s 1, 2 that forms the selected memory transistor Q ^M 1, 2 and pair, supplying the 0V from the second word line Z2 .

In this manner, the first selection transistor Q paired with the selected memory transistor Q ^M 1,2
^s 1,2 cuts off the path bypassing the memory transistor Q ^M 1,2, and the other first selection transistors Q ^s 1,1,.
Since Q ^s 1,1 forms a path bypassing the unselected memory transistors Q ^M 1,1, Q ^M 1,3, only the selected memory transistor Q ^M 1,2 has a channel current between the source and drain. Flows. Thus, hot electrons are generated in the channel portion, and electrons are injected into the floating gate of the selected memory transistor Q ^M1,2 . At this time, the first selection transistor Q ^s 1,1, Q ^s 1,3 serves as a transfer gate between the bit line Y1~ source line S.

In order to prevent erroneous writing / erase of another memory array constituent group connected to the same bit line Y1 typified by the memory transistors Q ^M 1,5, it is connected to another memory array constituent group. First word lines X4 to X
6. The second word lines Z4 to Z6 and the selection line C2 are all 0V
Fixed to Therefore, the memory transistors Q ^M 1,4, Q
^No channel current passes through ^M 1,5 and Q ^M 1,6, and no erroneous writing occurs.

Selective writing of memory transistors connected to the same word line, for example, Q ^M 1,1 and Q ^M 2,1
This is realized by the bit line voltage. That is, when writing to the memory transistor Q ^M 2,1, the bit line Y1 is set to 0V.
If the potential difference between the source and the drain of the memory transistor Q ^M 1,1 is set to 0 V, writing is not performed. Even if the bit line Y1 is in the open state, no channel current flows similarly, so that erroneous writing is not performed.

Next, the erase mode will be described. Tables 4 and 5 show examples of the potential of each bit line, each word line, and the source line in the erased state. All units in the table are volts (V). Here, "erasing" means that electrons are emitted from the floating gate electrode to reduce the threshold voltage of the memory transistor.

Table 4 shows a case where data is erased from a source line, and Table 5 shows a case where data is erased from a bit line.

[0060]

[Table 4]

[0061]

[Table 5]

The erasing in this embodiment utilizes FN electron tunneling. That is, when a high voltage such as 20 V is applied to the source / drain region or one of them, and a low voltage such as 0 V is applied to the control gate electrode, the first voltage from the floating gate electrode toward the source or drain region is reduced. The electric field in the gate insulating film is strengthened, and the FN tunneling phenomenon is caused via the first gate insulating film, thereby utilizing the property of emitting electrons.

Therefore, erasing is possible from both the bit line side and the source line side. First, a case where erasing is performed from the source side will be described.

In the case of batch erasing, there is no selectivity of the memory transistors, and all the first word lines X1 to X6 are set to 0V.
Then, all the second word lines Z1 to Z6 are set to 20V, and all the select lines C1 and C2 are set to 0V. At this time, the potential of the impurity diffusion layer on the source line side and the drain side on the source line side of all the memory transistors Q ^M i, j (i = 1,2, j = 1-6) becomes high, so that the floating gate Electrons are emitted from the electrodes and erased.

When a word line is selected and erased, only the selected first word line is set to 0 V, and all other first word lines are set to 0V.
And all the second word lines are set to 20V.
Further, the selection lines C1 and C2 are set to 0 V, and each memory array configuration group is separated from the bit lines Y1 and Y2. 20 for source line
Since a high voltage of V is applied, as a result, the electric field between the floating gate electrode and the source / drain electrodes becomes small except for the selected word line, so that the FN electron tunneling phenomenon does not occur, so that the data is not erased. Only the memory transistor connected to the first word line selected in this way is erased.

On the other hand, when erasing from the bit line side, the operation is the same as the other operations described above, except that the impurity diffusion layer to which the voltage is applied is switched from the source region to the drain region.

FIG. 9 shows the change in the threshold voltage of the memory transistor Q ^Mi , j in these write / erase modes. When writing is performed, the threshold voltage of the floating electrode is increased by electrons injected into the floating gate electrode. Thus, no channel current flows even if, for example, 0 V is applied to the control gate electrode.

On the contrary, when erasing is performed, the threshold voltage decreases due to emission of electrons from the floating gate electrode. Thus, for example, a channel current flows even when 0 V is applied to the control gate electrode.

FIG. 10 shows the variation of the threshold voltage of the memory transistor Q ^Mi , j with time. Although only the method of electrically erasing is described here, batch erasing by ultraviolet irradiation, for example, may be used. Subsequently, the read mode will be described with reference to Table 6. All units in the table are volts (V).

[0070]

[Table 6]

Hereinafter, description will be made assuming that the memory transistor Q ^M 2,1 is accessed. 0 V is applied to the control gate electrode of the selected memory transistor Q ^M 2,1 from the first word line X1.
And applying a 0V from the second word line Z1 to the gate electrode of the memory transistor Q ^M 2,1 and for the first selection that paired transistors Q ^s 2,1. Channel of the first selection transistor Q ^s 2,1 is turned off, the memory transistor Q
Only the channel section of ^M 2,1 is used as the current path.

The selected memory transistor Q ^M 2,1
Other first selecting transistor Q ^s 2, 2 of the memory array configuration group, all the gate electrodes of the Q ^s 2,3 are in the 5V to select a state belonging, the bit line Y as a transfer gate
2 and the current path from the selected memory transistor Q ^M 2,1 to the drain electrode and the selected memory transistor Q
A current path from ^M 2,1 to the source line S is formed.

[0073] Consequently, if the threshold voltage is 0V or more in selected memory transistor Q ^M 2,1 write state, the potential of the control gate electrode of the memory transistor Q ^M 2,1 The selected and 0V since going on, by the memory transistor Q ^M 2,1, the current path from the bit line Y2 to the source line S, the current is cut off does not flow.

On the contrary, the selected memory transistor Q
^{If M} 2,1 is in the erased state and the threshold voltage is 0 V or less, a current flows from the bit line Y2 to the source line S via the memory transistor Q ^M 2,1.

As described above, the erase and write states of the selected memory transistor correspond to “present” and “absent” of the current from the bit line, respectively, and the presence or absence of this current is connected to the bit line. By detecting with a sense amplifier or the like, “0” or “1” of the read data is determined.

Here, the control gate electrode of the unselected memory transistor may be 0V or 5V. This is because this memory transistor does not need to function as a transfer gate due to the presence of the paired first selection transistor.

In this embodiment, the threshold voltage of the non-selected memory transistor at the time of reading may have any value from the same meaning. If the threshold voltage of the first selection transistor is lower than the voltage applied to the second word line, the first selection transistor functions as a transfer gate, and the read function of the device is performed. .

On the other hand, the first word line, the second word line, and the selection line of all the other memory array configuration groups to which the selected memory transistor does not belong are fixed to 0V. Therefore, the current path from the bit lines Y1 and Y2 through these other memory array constituent groups is cut off. For this reason, even if the threshold voltages of all the memory transistors in all the memory array configuration groups are 0 V or less, the operation is not affected.

In addition to the above-described read mode, in the present embodiment, it is possible to read memory transistors connected to the same first word line in parallel. For example, to read the memory transistors Q ^M 1,1 and Q ^M 2,1 simultaneously,
The bit line Y1 and the bit line Y2 may be connected to different sense amplifiers (not shown), and data may be output according to the respective currents.

The selection line has the following advantages. To parasitic leakage current flowing through the non-selected memory transistor during the write to the first can be blocked by the second selecting transistor Q ^c i, thereby enabling efficient writing. As a result, the variation width of the threshold voltage of the memory transistor Q ^Mi , j at the time of writing and erasing can be set wide.

[0081] Second, it is possible to the impurity diffusion layer connected to the bit line Yi only drain diffusion layer of the second selection transistor Q ^c i of each memory array configuration group, reduce the bit line capacitance can do.

FIG. 11 shows a second embodiment of the present invention. FIG. 11 is a sectional view of a portion corresponding to the portion shown in FIG. The difference from the first embodiment is that the channel portion 8a of the first MOS transistor for selection is present above the gate electrode 4 of the first MOS transistor for selection.

With this configuration, the electric field due to the high voltage applied to the control gate 12 of the memory transistor is prevented by the gate electrode 4 of the first selection MOS transistor, and the channel voltage of the first selection transistor is reduced. It has the advantage of being stable.

The other functions and the driving method are the same as in the first embodiment. The same applies to other configurations, and the same reference numerals are given to the same reference numerals as those of the first embodiment, and the description is omitted.

[0085]

As described above, according to the present invention, the memory transistor and the first selection transistor are connected in parallel to form one pair, and a plurality of the pairs are connected in series to form a memory array group. The second selection transistor is provided between the bit line and the pair of the memory transistor and the first selection transistor.

Further, the first selection transistor is provided in a stacked manner on the memory transistor, and the first selection transistor is provided on the polycrystalline silicon connecting the first selection transistor in series. Transistor source
A polycrystalline silicon film containing impurities of the same conductivity type as the source / drain regions of the first selection transistor at a high concentration is provided on the drain region, and each of the first selection transistor and the second selection transistor is provided. Embedded between them. Such a configuration has the following effects.

(1) There is no need to set an intermediate potential at the time of selective writing, and voltage setting of two values is sufficient. Therefore, it is easy to design peripheral circuits and control circuits. (2) The problem of overwriting / overerasing does not occur. This means that there is no upper or lower limit on the variation of the threshold voltage of the memory transistor. Therefore, a large difference in the threshold voltage of the memory transistor during writing and erasing can be obtained. Therefore, it is simple and easy to design the peripheral circuit, particularly the control circuit for the writing system. Further, even if a difference in writing characteristics occurs due to a variation factor at the time of manufacturing a memory transistor, the manufacturing yield is high because the allowable range is wide. (3) Hot electron injection can be used for writing. Therefore, the electric field in the first gate insulating film of the unselected memory transistor at the time of writing can be smaller than that at the time of erasing. Therefore, erroneous writing of the non-selected memory transistors connected to the same word line during writing can be easily prevented. In addition, the threshold voltage of the memory transistor after writing can be controlled at a low voltage of the control gate electrode, for example, 0 V. Therefore, the voltage of the control gate electrode at the time of writing is low, and the first word line is It is not necessary to use a high breakdown voltage transistor having a high breakdown voltage junction for the decoder to be driven, and the design of the decoder is facilitated. (4) Since it is not necessary to perform writing by FN electron tunneling and erasing can be performed by avalanche breakdown or ultraviolet irradiation other than by FN electron tunneling, the first memory transistor can be used. It is also possible to use a relatively thick silicon oxide film such as 130 Å for the gate insulating film. Therefore, control at the time of manufacturing the first gate insulating film of the memory transistor is easy and the manufacturing yield is high. (5) Since the drain voltage at the time of writing is low and the electric field in the first gate insulating film is weak, erroneous erasure at the time of writing to already written data is unlikely to occur. For this reason, there is no restriction on the writing order of the memory transistor group connected in series. Therefore, the design of the peripheral circuit is easy. (6) Word erasing and word writing are possible. That is, only the information of a specific word line can be rewritten. Therefore, the stored data can be updated without erasing all bits and writing all bits. This can greatly reduce the program time and is suitable for storing the stored data in the program at any time. (7) Since the first selection transistor paired with the memory transistor is provided on the upper portion of each memory transistor, the cell occupation area is the same as that of the related art. Further, a selection transistor is not required on the source side of each transistor group, and the array area when a cell array is formed is reduced. (8) Since the source / drain regions of the first selection transistor provided on the thin polycrystalline silicon film are buried with the polycrystalline silicon film, the first selection transistor is highly integrated. There is an advantage that voids are prevented from being formed in the source / drain regions.

In addition, since the distance between the first selection transistors is reduced electrically, the first selection transistor also has a function of reducing the parasitic resistance of the source and drain of the first selection transistor.

[Brief description of the drawings]

FIG. 1 is a plan view showing a first embodiment of the present invention.

FIG. 2 is a sectional view taken along the line A-A 'of FIG.

FIG. 3 is a sectional view taken along line B-B 'of FIG.

FIG. 4 is a sectional view taken along the line C-C 'of FIG.

FIG. 5 is a sectional view taken along line D-D 'of FIG.

FIG. 6 is a sectional view taken along the line E-E 'of FIG.

FIG. 7 is a sectional view taken along line F-F 'of FIG.

FIG. 8 is an equivalent circuit diagram of the first embodiment of the present invention.

FIG. 9 is a graph showing voltage-current characteristics of the memory transistor according to the first embodiment of the present invention.

FIG. 10 is a graph showing a program characteristic of the memory transistor according to the first embodiment of the present invention.

FIG. 11 is a sectional view showing a second embodiment of the present invention.

FIG. 12 is an equivalent circuit diagram of a conventional nonvolatile semiconductor memory device.

FIG. 13 is a plan view of a conventional example.

FIG. 14 is a sectional view of a conventional nonvolatile semiconductor memory device.

[Explanation of symbols]

Q ^M i, j Memory transistor Q ^s i, j First selection transistor Q ^ci Second selection transistor 1,21 Semiconductor substrate 2a, 2b, 2c, 22a, 22b, 22c First impurity diffusion layer 3 , 23a Gate insulating film of first selecting MOS transistor 4, 28a Gate electrode of first selecting MOS transistor 6, 28b Gate electrode of second selecting MOS transistor 5, 23b Second Gate insulating film of selection MOS type transistor 7, 29 Interlayer insulation film 8a, 8c Impurity diffusion layer of first selection MOS type transistor 8b Channel region of first selection MOS type transistor 9, 24 Memory MOS Gate insulating film of type transistor 10,26 floating gate electrode 11,25 second gate insulating film of MOS transistor for memory 12, 27 control gate electrode 13 metal wiring interlayer film 14, 30 contact hole 15, 31 metal wiring 16 field insulating film 17 polycrystalline silicon film 100 first selection MOS transistor 110 second selection MOS transistor

Continuation of front page (56) References JP-A-4-34981 (JP, A) JP-A-4-298079 (JP, A) JP-A-5-36942 (JP, A) JP-A-4-351792 (JP) JP-A-4-218960 (JP, A) JP-A-4-71269 (JP, A) JP-A-1-235278 (JP, A) JP-A-2-112286 (JP, A) 3-85770 (JP, A) JP-A-3-296276 (JP, A) JP-A-3-14272 (JP, A) JP-A-60-1697 (JP, A) JP-A-54-110742 (JP, A) A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792

Claims (3)

(57) [Claims] 1. A memory array configuration group in which a plurality of transistor pairs each including a memory transistor having a floating gate and a control gate and a first selection transistor connected in parallel with the memory transistor are connected in series. An arranged memory array, a first word line commonly connected to a control gate of each of the memory transistors arranged at the same row direction position, and each of the plurality of first word lines corresponding to the same one of the plurality of first word lines. A plurality of second word lines commonly connected to the gates of the first selection transistors arranged in the row direction; a plurality of bit lines provided corresponding to a plurality of columns of the memory array; And a plurality of second selecting transistors connected between the bit line of the memory array and one end of the memory array configuration group. Non-volatile comprising: a plurality of select lines each connected to the gate of a second selection transistor of a memory array configuration group belonging to the same row; and a source line connected to the other end of the plurality of memory array configuration groups. Semiconductor memory device. 2. Each of the memory transistors includes an impurity region formed in a semiconductor substrate, a first gate insulating film covering a surface of the semiconductor substrate, the floating gate laminated on the first gate insulating film, A second gate insulating film provided on the floating gate; and a control gate on the second gate insulating film, wherein the first selection transistor is formed on a semiconductor layer on an interlayer insulating film covering the control gate. 2. The nonvolatile semiconductor memory device according to claim 1, further comprising: a channel region provided; a third gate insulating film on the channel region; and a gate electrode on the third gate insulating film. 3. Each of the memory transistors includes an impurity region formed in a semiconductor substrate, a first gate insulating film covering a surface of the semiconductor substrate, and the floating gate laminated on the first gate insulating film. A second gate insulating film provided on the floating gate; and a control gate on the second gate insulating film, wherein the first selection transistor has a gate electrode on an interlayer insulating film covering the control gate. 2. The nonvolatile semiconductor memory device according to claim 1, further comprising a third gate insulating film on said gate electrode, and a channel region provided in a semiconductor layer on said third gate insulating film.