JP3148026B2 - Thermistor and manufacturing method thereof - Google Patents
Thermistor and manufacturing method thereofInfo
- Publication number
- JP3148026B2 JP3148026B2 JP34347392A JP34347392A JP3148026B2 JP 3148026 B2 JP3148026 B2 JP 3148026B2 JP 34347392 A JP34347392 A JP 34347392A JP 34347392 A JP34347392 A JP 34347392A JP 3148026 B2 JP3148026 B2 JP 3148026B2
- Authority
- JP
- Japan
- Prior art keywords
- thermistor
- pair
- plating layer
- layer
- base electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Details Of Resistors (AREA)
- Thermistors And Varistors (AREA)
Description
【0001】[0001]
【産業上の利用分野】本発明は、端子電極にリード線が
接合される温度センサとして、或いはプリント回路基板
に表面実装して電子機器の温度補償用サーミスタとして
用いられるサーミスタ及びその製造方法に関するもので
ある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thermistor used as a temperature sensor in which a lead wire is bonded to a terminal electrode, or used as a thermistor for temperature compensation of an electronic device by being surface-mounted on a printed circuit board and a method of manufacturing the same. It is.
【0002】[0002]
【従来の技術】従来、この種のサーミスタは、サーミス
タ素体の両端部にAg−Pdを主成分とする電極が焼付
けられている。電極成分にAgの他にPdを含有する理
由は、基板にサーミスタをはんだ付けする際に、Agが
はんだ中に溶出して消失することを防止し、電極のはん
だ耐熱性を得るためである。しかし、Pdの含有量を増
加すると電極のはんだ付着性が低下して基板へのサーミ
スタの固着力が弱くなるため、Pdの含有量には一定の
限界があった。このため電極のはんだ付けが高温で長時
間行われる場合には、従来のサーミスタはなおはんだ耐
熱性が不十分であった。はんだ耐熱性とはんだ付着性を
向上させるために、チップ型コンデンサと同様に、焼付
け電極である下地電極の表面にめっき層を設けることが
考えられるが、サーミスタ素体はコンデンサ素体と異な
り導電性を有するため、このサーミスタ素体を露出した
ままめっき処理した場合、素体表面にめっきが付着して
サーミスタの抵抗値が所期の値と異なり、しかもサーミ
スタ素体がめっき液で浸食されてサーミスタの信頼性が
低下する等の不具合を生じる。2. Description of the Related Art Conventionally, in this type of thermistor, electrodes mainly composed of Ag-Pd are baked at both ends of a thermistor body. The reason for containing Pd in addition to Ag in the electrode component is to prevent Ag from eluting and disappearing in the solder when soldering the thermistor to the substrate, and to obtain solder heat resistance of the electrode. However, when the content of Pd is increased, the solder adhesion of the electrode is reduced, and the fixing force of the thermistor to the substrate is weakened. Therefore, the content of Pd has a certain limit. For this reason, when the electrodes are soldered at a high temperature for a long time, the conventional thermistor still has insufficient solder heat resistance. In order to improve solder heat resistance and solder adhesion, it is conceivable to provide a plating layer on the surface of the base electrode, which is a baked electrode, as in the case of chip type capacitors. Therefore, if plating is performed while exposing the thermistor body, plating will adhere to the surface of the body and the resistance value of the thermistor will differ from the expected value, and the thermistor body will be eroded by the plating solution and the thermistor body will be eroded. Problems such as a decrease in the reliability of the device.
【0003】この点を改善するため、本出願人は焼付け
電極層が接触する部分以外のサーミスタ素体の表面をガ
ラス層で被覆し、焼付け電極層の表面にめっき層を形成
したサーミスタを特許出願した(特開平3−25060
3)。このサーミスタは、次の方法により製造される。
先ずサーミスタ素体用のセラミック焼結シートの両面に
ガラスペーストを印刷して焼成することにより絶縁性の
ガラス層を形成する。次いで両面がガラス層で被覆され
た焼結シートを短冊状に切断した後、両側の切断面に前
述と同様にガラスペーストを印刷焼成してガラス層を形
成する。次に前記切断面と垂直な方向にこの短冊状物を
細かく切断してチップを作る。このチップの切断面を包
むようにチップの両端部に導電性ペーストを塗布し、焼
成して焼付け電極層を形成する。更にこの焼付け電極層
を下地電極層としてその表面にめっき層を形成して焼付
け電極層とめっき層からなる端子電極を有するサーミス
タを得る。In order to improve this point, the present applicant filed a patent application for a thermistor in which the surface of the thermistor body other than the portion where the baked electrode layer contacts is covered with a glass layer and a plating layer is formed on the surface of the baked electrode layer. (Japanese Unexamined Patent Publication No. 3-25060)
3). This thermistor is manufactured by the following method.
First, an insulating glass layer is formed by printing and firing glass paste on both sides of a ceramic sintered sheet for a thermistor body. Next, after cutting the sintered sheet having both surfaces covered with the glass layer into a strip shape, a glass paste is printed and fired on the cut surfaces on both sides in the same manner as described above to form a glass layer. Next, the strip is finely cut in a direction perpendicular to the cut surface to produce a chip. A conductive paste is applied to both ends of the chip so as to cover the cut surface of the chip, and the paste is baked to form a baked electrode layer. Further, a plating layer is formed on the surface of the baked electrode layer as a base electrode layer to obtain a thermistor having a terminal electrode composed of the baked electrode layer and the plated layer.
【0004】また、相対向する両側面に設けたAg電極
がはんだ付けするときに溶出(Ag食われ)しないよう
に、2層構造の電極の上にはんだ層を形成したサーミス
タ素子が開示されている(特開平3−136204)。
このサーミスタ素子は、次の方法により作られる。先ず
円柱状に焼成されたサーミスタをスライシングソーによ
りウエハ状に切断した後、60〜80%Ag、3.5〜
7.0%ガラスフリット成分含有のペーストをウエハの
両面にスクリーン印刷して焼付けることにより電極下層
を形成する。次いでウエハ両面の電極下層の上に75〜
85%Ag、0〜1%ガラスフリット成分含有のペース
トをスクリーン印刷して焼付けることにより電極上層を
形成する。更にこの2層構造の電極を有するサーミスタ
ウエハをはんだ槽のはんだ液に浸漬させて電極上層の上
にはんだ層を形成した後、ダイシングソーによりチップ
状に切断してサーミスタ素子を得る。このサーミスタ素
子は、はんだ層を形成することによりはんだ付着性を向
上させ、電極下層にガラスフリット成分を多く含ませる
ことによりダイシングソーで切断したときの電極の剥離
を防止し、かつ電極上層にAg成分を多く含ませること
によりAg食われを起こしても電極が残存するようにし
ている。Further, there is disclosed a thermistor element in which a solder layer is formed on an electrode having a two-layer structure so that Ag electrodes provided on both side surfaces facing each other do not elute (Ag is eroded) when soldering. (JP-A-3-136204).
This thermistor element is manufactured by the following method. First, the cylindrical thermistor is cut into a wafer using a slicing saw, and then 60-80% Ag, 3.5-3.5%.
A paste containing 7.0% glass frit component is screen-printed and baked on both sides of the wafer to form an electrode lower layer. Next, 75-
An electrode upper layer is formed by screen-printing and baking a paste containing 85% Ag and 0 to 1% glass frit component. Further, the thermistor wafer having the electrode of the two-layer structure is immersed in a solder solution in a solder bath to form a solder layer on the electrode upper layer, and then cut into chips by a dicing saw to obtain a thermistor element. This thermistor element improves the solder adhesion by forming a solder layer, prevents the electrode from peeling when cut with a dicing saw by adding a large amount of a glass frit component to the electrode lower layer, and forms an Ag upper layer on the electrode. By including a large amount of components, the electrode remains even if Ag is eroded.
【0005】[0005]
【発明が解決しようとする課題】しかし、上記特開平3
−250603号公報に示されるサーミスタの製造方法
では、ガラス層の被覆を2回に分けて行う必要がある
上、チップになった後に、その両端部に導電性ペースト
を塗布したり、めっき層を形成したりする必要がある。
このため、チップにした後の取扱いに多大の注意を払わ
なければならない。これらのことから製造工程が複雑化
し、必然的に製造コストが高価になる問題点があった。
また、上記特開平3−136204号公報に示されるサ
ーミスタ素子の製造方法はチップにした後で特別の加工
を要しない利点があるものの、はんだ層をはんだ液への
ディッピングにより形成するため、均一な層ができにく
い欠点があり、しかもAg電極を2回焼付ける必要があ
るため、焼付けのためのエネルギ量が大きく、かつAg
食われを防止する対策を採っていないためAgのチップ
当りの使用量が増大し、コストを押上げる問題点があっ
た。However, Japanese Patent Application Laid-Open No.
In the method of manufacturing a thermistor disclosed in JP-A-250603, it is necessary to coat the glass layer in two parts, and after forming a chip, a conductive paste is applied to both ends of the chip, or a plating layer is formed. Or must be formed.
For this reason, great care must be taken in handling the chips. For these reasons, there has been a problem that the manufacturing process is complicated and the manufacturing cost is necessarily high.
The method of manufacturing a thermistor element disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 3-136204 has an advantage that no special processing is required after forming a chip. However, since the solder layer is formed by dipping in a solder liquid, the method is uniform. There is a disadvantage that the layer is difficult to be formed, and since the Ag electrode needs to be baked twice, the energy amount for the baking is large and the Ag electrode is
Since no countermeasures are taken to prevent erosion, the amount of Ag used per chip increases, which raises the problem of increasing costs.
【0006】本発明の目的は、はんだ耐熱性及びはんだ
付着性に優れ、電極のめっき処理による抵抗値の変化が
なく、サーミスタ素体と基板取付体とが電気的により確
実に接続され、信頼性の高いサーミスタを提供すること
にある。本発明の別の目的は、回路基板にはんだ付けす
るときに基板取付体が熱的ストレスを緩和することによ
り熱的耐久性が高められ、かつ基板へのはんだ付けが容
易なサーミスタを提供することにある。本発明の別の目
的は、下地電極層の表面にはんだ耐熱性とはんだ付着性
のある層を均一に形成するサーミスタの製造方法を提供
することにある。本発明の更に別の目的は、上記優れた
サーミスタを比較的容易にかつ安価に製造できるサーミ
スタの製造方法を提供することにある。SUMMARY OF THE INVENTION It is an object of the present invention to provide excellent heat resistance and solder adhesion, no change in resistance due to plating of electrodes, and a more reliable electrical connection between the thermistor body and the substrate mounting body.
The object is to provide a highly connected thermistor with high reliability. Another object of the invention is to solder to a circuit board.
Board mounting body to relieve thermal stress when
Thermal durability and soldering to the board
It is to provide an easy thermistor. Another object of the present invention is to provide a method for manufacturing a thermistor that uniformly forms a layer having solder heat resistance and solder adhesion on the surface of a base electrode layer. Still another object of the present invention is to provide a method for manufacturing a thermistor which can manufacture the excellent thermistor relatively easily and at low cost.
【0007】[0007]
【問題点を解決するための手段】図1、図7〜図11、
図14及び図15に示すように、本願請求項1に係る発
明は、6面体からなるチップ状サーミスタ素体11の相
対向する両側面に一対の端子電極12,12が形成され
たサーミスタの改良である。その特徴ある構成は、端子
電極12が貴金属を含む下地電極層16とこの下地電極
層16の表面に形成されためっき層17とからなる積層
電極であって、この積層電極の4つの側面が一対の端子
電極12,12が形成されないサーミスタ素体の他の4
面と同一面をなし、かつリードフレーム又はブロックか
らなる導電性のある一対の基板取付体31,32又は3
4の各主面が高温クリームはんだにより一対の端子電極
12の各主面に接合されたことにある。また、図12及
び図13に示すように、本願請求項5に係る発明の特徴
ある構成は、端子電極12が貴金属を含む下地電極層1
6とこの下地電極層16の表面に形成されためっき層1
7とからなる積層電極であって、この積層電極の4つの
側面が一対の端子電極12,12が形成されないサーミ
スタ素体の他の4面と同一面をなし、かつ四角筒状のリ
ードフレームからなる導電性のある基板取付体33の内
面が高温クリームはんだにより一対の端子電極12,1
2を含むサーミスタ素体11の両側部に接合されたこと
にある。なお、めっき層17が下地電極層16の表面に
形成されたNiめっき層17aと、このNiめっき層1
7aの表面に形成されたSn又はSn/Pbめっき層1
7bとを有することが、また基板取付体31,32,3
3,34が導電性のある金属素体30aとその表面に形
成されたSn又はSn/Pbめっき層30bとを備える
ことが好ましい。[Means for solving the problem] FIGS. 1 , 7 to 11,
As shown in FIGS. 14 and 15, the outgoing <br/> bright according to the present gun claim 1, a pair of terminal electrodes 12, 12 on both side surfaces facing each other of the chip-thermistor element 11 consisting of hexahedron It is an improvement of the formed thermistor. Its characteristic configuration is laminated to the terminal electrode 12 is formed of a plating layer 17. formed on the surface of the underlying electrode layer 16 this underlying electrode layer 16 containing a noble metal
Electrodes, and four side surfaces of the laminated electrode are a pair of terminals.
The other four of the thermistor body where the electrodes 12, 12 are not formed
Is the same plane as the surface and is a lead frame or block
A pair of conductive board mounting bodies 31, 32 or 3
4 is a pair of terminal electrodes made of high-temperature cream solder
12 are joined to each main surface . In addition, FIG.
As shown in FIG. 13 and FIG.
One configuration is such that the terminal electrode 12 is a base electrode layer 1 containing a noble metal.
6 and the plating layer 1 formed on the surface of the base electrode layer 16
7 and four of the laminated electrodes
Thermistors whose side surfaces do not have a pair of terminal electrodes 12
It is the same surface as the other four surfaces of the star element body, and
Of the conductive board mounting body 33 made of a metal frame.
The surface is made of a pair of terminal electrodes 12, 1 made of high-temperature cream solder.
2 on both sides of the thermistor body 11 including
It is in. The Ni plating layer 17a in which the plating layer 17 is formed on the surface of the base electrode layer 16 and the Ni plating layer 1
Sn or Sn / Pb plating layer 1 formed on the surface of 7a
7b, and the board mounting bodies 31, 32, 3
3, 34 are conductive metal body 30a and the surface
With the formed Sn or Sn / Pb plating layer 30b
Is preferred.
【0008】また、本発明のサーミスタの製造方法は、
図2に示されるサーミスタ素体用セラミック焼結シート
21の両面全体に下地電極層16,16を形成し(図3
及び図4)、これらの下地電極層16,16の各表面に
Niめっき層17a及びSn又はSn/Pbめっき層1
7bをこの順に形成し(図1及び図5)、この下地電極
層16とめっき層17からなる電極を両面に形成した焼
結シート21をダイシングソーによりチップ状に切断し
てチップ状サーミスタ素体11の相対向する両側面に一
対の端子電極12,12を設けた後(図6)、一対の端
子電極12,12の各主面にリードフレーム又はブロッ
クからなる導電性のある一対の基板取付体31,32,
34の各主面を高温クリームはんだにより接合する(図
7〜図11,図14及び図15)方法である。Further, a method for manufacturing a thermistor according to the present invention comprises:
The base electrode layers 16, 16 are formed on both surfaces of the ceramic sintered sheet 21 for thermistor body shown in FIG.
And FIG. 4 ), the Ni plating layer 17a and the Sn or Sn / Pb plating layer 1 are formed on the respective surfaces of the base electrode layers 16, 16.
7b are formed in this order (FIGS. 1 and 5 ), and the sintered sheet 21 on which both surfaces of the electrode composed of the base electrode layer 16 and the plating layer 17 are formed is cut into chips by a dicing saw to form a chip thermistor body. After a pair of terminal electrodes 12 and 12 are provided on both opposite side surfaces of the pair 11 (FIG. 6), a pair of terminal electrodes 12 and 12 are provided.
A lead frame or a block is provided on each main surface of the
, A pair of conductive board mounting bodies 31, 32,
34 are joined by high-temperature cream solder.
7 to 11, 11, 14 and 15) .
【0009】以下、本発明を詳述する。 (a) セラミック焼結シートの作製図2 に示すように、サーミスタ素体用セラミック焼結シ
ート21を用意する。この焼結シート21は次の方法に
より作られる。先ずMn,Fe,Co,Ni,Cu,A
l等の金属の酸化物粉末を1種又は2種以上混合する。
2種以上混合するときは、所定の金属原子比になるよう
に各金属酸化物を秤量する。この混合物を仮焼し粉砕
し、有機結合材を加え混合して直方体に成形した後、焼
成してセラミック焼結ブロック(図示せず)を作製す
る。次いでこのブロックをバンドソーを用いてウエハ状
に切断し、図2に示す焼結シート21を得る。なお、金
属酸化物の混合物を仮焼し粉砕した後、有機結合材と溶
剤を加え混練してスラリーを調製し、このスラリーをド
クターブレード法等により成膜乾燥してグリーンシート
を成形し、これを焼成し焼結シート21を得てもよい。Hereinafter, the present invention will be described in detail. (a) Preparation of Ceramic Sintered Sheet As shown in FIG. 2 , a ceramic sintered sheet 21 for thermistor body is prepared. This sintered sheet 21 is made by the following method. First, Mn, Fe, Co, Ni, Cu, A
One or more metal oxide powders such as 1 are mixed.
When mixing two or more, each metal oxide is weighed so as to have a predetermined metal atomic ratio. The mixture is calcined and pulverized, an organic binder is added and mixed to form a rectangular parallelepiped, and then fired to produce a ceramic sintered block (not shown). Next, this block is cut into a wafer using a band saw, and a sintered sheet 21 shown in FIG. 2 is obtained. After calcination and pulverization of the mixture of metal oxides, an organic binder and a solvent were added and kneaded to prepare a slurry, and the slurry was formed into a film by a doctor blade method and dried to form a green sheet. May be fired to obtain a sintered sheet 21.
【0010】(b) 下地電極層の形成 次に、図3に示すように、焼結シート21の両面全体に
貴金属粉末と無機結合材を含む導電性ペーストを塗布す
る。図4は図3のF部拡大図である。この塗布は導電性
ペーストを均一に印刷する印刷法によることが好まし
い。貴金属粉末を例示すれば、Ag,Au,Pd,Pt
等の貴金属、又はこれらを混合した粉末が挙げられる。
この焼成により下地電極層16が焼結シート21の両面
全体に形成される。なお、導電性ペーストを印刷法によ
り塗布し、これを焼成して焼付け電極層の下地電極層を
形成する以外に、焼結シート21の両面に溶射法により
下地電極層を形成することもできる。(B) Formation of Underlying Electrode Layer Next, as shown in FIG. 3 , a conductive paste containing a noble metal powder and an inorganic binder is applied to both surfaces of the sintered sheet 21. Figure 4 is an F part enlarged view of FIG. This coating is preferably performed by a printing method for uniformly printing the conductive paste. Examples of noble metal powders include Ag, Au, Pd, and Pt.
And a powder obtained by mixing these.
By this baking, the base electrode layer 16 is formed on both surfaces of the sintered sheet 21. In addition to applying a conductive paste by a printing method and baking the conductive paste to form a base electrode layer of a baked electrode layer, a base electrode layer may be formed on both surfaces of the sintered sheet 21 by a thermal spraying method.
【0011】(c) めっき層の形成 図1及び図5に示すように、下地電極層16,16の各
表面にめっき層17を設けて、下地電極層16及びめっ
き層17により電極を作製する。めっき層17はNiめ
っき層17a及びSn又はSn/Pbめっき層17bを
この順に形成する。これらのめっき層は電解めっきによ
り形成される。めっき浴はNi,Sn又はSn/Pbと
もそれぞれ公知のものを使用する。めっき層を二重構造
にするのは、Niめっき層17aによりはんだ耐熱性を
向上させはんだによる下地電極層の電極食われを防止す
るためであり、Sn又はSn/Pbめっき層17bによ
り端子電極12のはんだ付着性を向上するためである。(C) Formation of Plating Layer As shown in FIGS. 1 and 5 , a plating layer 17 is provided on each surface of the base electrode layers 16, 16, and an electrode is formed by the base electrode layer 16 and the plating layer 17. . As the plating layer 17, a Ni plating layer 17a and a Sn or Sn / Pb plating layer 17b are formed in this order. These plating layers are formed by electrolytic plating. Known plating baths are used for Ni, Sn and Sn / Pb. The reason why the plating layer has a double structure is to improve the solder heat resistance by the Ni plating layer 17a and prevent the electrode of the base electrode layer from being eroded by solder, and the terminal electrode 12 is formed by the Sn or Sn / Pb plating layer 17b. This is for the purpose of improving the solder adhesion.
【0012】(d) 一対の端子電極の形成 図5 及び図6に示すように、ダイヤモンドブレード付き
切断機のようなダイシングソーを用いて矢印Mの箇所で
下地電極層16とめっき層17が積層された焼結シート
21を破線に沿って切断し、短冊状のサーミスタ素体を
形成する。次いでこのサーミスタ素体を矢印Nの箇所で
破線に沿って切断し、多数のチップ状サーミスタ素体1
1の相対向する両側面に一対の端子電極12,12を形
成する。図6に示される上下の端子電極12,12を左
右になるようにサーミスタ10を90度回転させれば、
図1のチップ型サーミスタとなる。 (D) Formation of a pair of terminal electrodes As shown in FIGS. 5 and 6 , a base electrode layer 16 and a plating layer 17 are laminated at a position indicated by an arrow M using a dicing saw such as a cutting machine with a diamond blade. The sintered sheet 21 thus cut is cut along a broken line to form a strip-shaped thermistor body. Next, this thermistor body was cut along the broken line at the point of arrow N, and a large number of chip-like thermistor bodies 1 were cut.
A pair of terminal electrodes 12, 12 are formed on both opposite side surfaces of the pair.
To achieve. If the thermistor 10 is rotated 90 degrees so that the upper and lower terminal electrodes 12, 12 shown in FIG.
Chip of FIG. 1 thermistor ing.
【0013】(e) 基板取付体の接合 図7〜図11,図14及び図15 に示すように、サーミ
スタ10の一対の端子電極12,12の各主面には、リ
ードフレーム又はブロックからなる導電性のある一対の
基板取付体31,32,34の各主面が高温クリームは
んだにより接合される。基板取付体は金属素体30aと
この素体30aの表面に形成されたSn又はSn/Pb
めっき層30bとを備えることが好ましい。ここで金属
素体30aはSn又はSn/Pbめっき可能な材質であ
れば、特に制限されない。また図 12及び図13に示す
ように四角筒状のリードフレームからなる導電性のある
基板取付体33の内面が高温クリームはんだにより一対
の端子電極12,12を含むサーミスタ素体11の両側
部に接合される。このように構成することにより、サー
ミスタ素体と基板取付体とが電気的により確実に接続さ
れ、信頼性の高いサーミスタが得られるとともに、熱的
ストレスをサーミスタが受けたときに基板取付体31〜
34がこれを緩和し、サーミスタの耐久性が高まる。ま
た基板へのはんだ付けが容易になる。図7〜図9は断面
L字状のリードフレームを基板取付体31とする例を示
す。基板取付体31の鉛直方向に延びる主面が端子電極
12の主面に高温クリームはんだにより接合する。図1
0及び図11は断面コ字状のリードフレームを基板取付
体32とする例を示す。基板取付体32の折曲げ間隔は
サーミスタ素体11の厚さに応じて決められる。この例
も基板取付体32の鉛直方向に延びる主面が端子電極1
2の主面に高温クリームはんだにより接合する。図12
及び図13は四角筒状のリードフレームを基板取付体3
3とする例を示す。基板取付体33はサーミスタ素体1
1に丁度嵌合するように内部の寸法が決められる。筒内
面が高温クリームはんだにより一対の端子電極12を含
むサーミスタ素体11の両側部に接合する。図14及び
図15は直方体状のブロックを基板取付体34とする例
を示す。基板取付体34の一方の主面が高温クリームは
んだによりサーミスタ素体11の端子電極12の主面に
接合する。[0013] (e) bonding FIGS. 7 11 of the substrate mounting member, as shown in FIGS. 14 and 15, each main surface of the pair of terminal electrodes 12, 12 of the thermistor 10, Li
The main surfaces of a pair of conductive substrate mounting members 31 , 32 and 34 each formed of a card frame or a block are made of a high-temperature cream.
It is joined by the reason. The substrate mounting body is a metal element 30a.
Sn or Sn / Pb formed on the surface of the element body 30a
It is preferable to include the plating layer 30b. Here, the metal element 30a is not particularly limited as long as it is a material that can be plated with Sn or Sn / Pb. Also shown in FIG. 12 and FIG.
Made of square tubular lead frame made of conductive
The inner surfaces of the board mounting body 33 are paired with high-temperature cream solder.
Sides of the thermistor body 11 including the terminal electrodes 12
Joined to the part. With this configuration, Sir
The mist body and the board mount are more securely connected electrically.
In addition to obtaining a highly reliable thermistor, when the thermistor receives a thermal stress, the board mounting members 31 to
34 alleviates this and increases the durability of the thermistor. In addition, soldering to the substrate becomes easy. 7 to 9 show an example in which a lead frame having an L-shaped cross section is used as the board attachment body 31. FIG. The main surface extending in the vertical direction of the substrate mounting body 31 is joined to the main surface of the terminal electrode 12 by high-temperature cream solder. FIG.
0 and FIG. 11 show an example in which a lead frame having a U-shaped cross section is used as the substrate mounting body 32. The bending interval of the board mounting body 32 is determined according to the thickness of the thermistor body 11 . Also in this example, the main surface of the board mounting body 32 extending in the vertical direction is the terminal electrode 1.
2 is joined to the main surface by high-temperature cream solder. FIG.
And FIG. 13 shows a case where the rectangular cylindrical lead frame is
Here is an example of setting the number to 3. The substrate mounting body 33 is a thermistor body 1
The internal dimensions are determined so that they just fit into one . The inner surface of the cylinder includes a pair of terminal electrodes 12 with high-temperature cream solder.
On both sides of the thermistor body 11 . FIG. 14 and
FIG. 15 shows an example in which a rectangular parallelepiped block is used as the board mounting body 34. The main surface of the hand of the board mounting member 34 is joined to the main surface of the terminal electrode 12 of the thermistor element 11 by a high temperature solder.
【0014】[0014]
【作用】サーミスタのはんだ付け時には、端子電極12
のNiめっき層17aによりはんだ耐熱性が向上し、は
んだによる下地電極層16の電極食われが防止され、S
n又はSn/Pbめっき層17bにより端子電極12の
はんだ付着性が向上する。また、サーミスタ素体の端子
電極が形成されない他の4面は焼結シートの切断前で露
出していないため、めっき処理によってこれら4面はめ
っき液で浸食されず、サーミスタの抵抗値が所期の値に
対して変動しない。更に、端子電極12の主面にリード
フレーム又はブロックからなる基板取付体31,32,
34の主面を高温クリームはんだにより接合するので、
或いは四角筒状のリードフレームからなる基板取付体3
3をサーミスタ素体11の両側部に高温クリームはんだ
により接合するので、サーミスタ素体と基板取付体とが
電気的により確実に接続され、信頼性の高いサーミスタ
が得られるとともに、サーミスタの熱的耐久性がより高
まり、かつ基板へのはんだ付けが容易になる。 When the thermistor is soldered, the terminal electrode 12
The Ni plating layer 17a improves the solder heat resistance, prevents the underlying electrode layer 16 from being eroded by solder, and
The solder adhesion of the terminal electrode 12 is improved by the n or Sn / Pb plating layer 17b. In addition, the other four surfaces of the thermistor body where the terminal electrodes are not formed are not exposed before cutting the sintered sheet. Therefore, these four surfaces are not eroded by the plating solution due to the plating treatment, and the resistance value of the thermistor is expected. Does not change with respect to the value of. Furthermore, a lead is connected to the main surface of the terminal electrode 12.
Board mounting bodies 31 , 32 composed of frames or blocks ,
Runode be joined 34 main surface of the high-temperature solder paste,
Alternatively, a substrate mounting body 3 formed of a square cylindrical lead frame
3 is high-temperature cream solder on both sides of the thermistor body 11
So that the thermistor body and the substrate mounting body
A more reliable thermistor that is more securely connected electrically
Together is obtained, the thermal resistance of the thermistor Ri higher <br/> Well, and soldered to the substrate is facilitated.
【0015】[0015]
【発明の効果】以上述べたように、従来の特開平3−2
50603号公報に示されるサーミスタの製造方法では
工程数が多く複雑であったものが、また特開平3−13
6204号公報に示されるサーミスタ素子の製造方法で
は焼付けのためのエネルギ量が大きく、かつ貴金属のチ
ップ当りの使用量が増大してコストを押上げていたもの
が、本発明の製造方法によれば、少ない工程で、大きな
エネルギ量を消費せずに、かつ貴金属の使用量を増大さ
せずに、比較的容易に超小型のサーミスタを製造でき
る。このため、本発明の製造方法は量産に適し、製造コ
ストが安価になる。特に、下地電極層及びめっき層を形
成した後でサーミスタ素体を精密に切断することによ
り、素子の寸法、電極面積等を厳格に制御できるので、
チップになった後の特別な加工を要さず、しかも抵抗値
の精度が高いサーミスタが得られる。また、下地電極層
の表面にめっき層を形成することにより、はんだ耐熱性
とはんだ付着性に優れ、はんだによる電極食われを起こ
すことがない。更に、端子電極にリードフレーム又はブ
ロックからなる導電性のある基板取付体を設けることに
より、サーミスタ素体と基板取付体とが電気的により確
実に接続され、信頼性の高いサーミスタが得られるとと
もに、サーミスタの熱的耐久性がより高まり、かつ基板
へのはんだ付けが容易になる。 As described above, the conventional Japanese Patent Laid-Open Publication No.
In the method of manufacturing a thermistor disclosed in Japanese Patent No. 50603, the number of steps is large and complicated.
In the method of manufacturing a thermistor element disclosed in Japanese Patent Application Laid-Open No. 6204, the amount of energy for baking is large, and the amount of use of a noble metal per chip is increased, thereby increasing the cost. An ultra-small thermistor can be manufactured relatively easily in a small number of steps without consuming a large amount of energy and without increasing the amount of noble metal used. For this reason, the manufacturing method of the present invention is suitable for mass production and the manufacturing cost is reduced. In particular, by precisely cutting the thermistor body after forming the base electrode layer and the plating layer, the dimensions of the element, the electrode area, etc. can be strictly controlled,
A thermistor that does not require any special processing after forming a chip and has high resistance value accuracy can be obtained. Further , by forming a plating layer on the surface of the base electrode layer, the solder heat resistance and the solder adhesion are excellent, and the electrode is not eroded by the solder . In addition, connect the lead frame or
The Rukoto provided electrically conductive certain substrate mounting member made of locking
The electrical connection between the thermistor body and the substrate
If a thermistor that is actually connected and highly reliable can be obtained
Moni, Ri thermal resistance of the thermistor is more Takama, and the substrate
It becomes easy to solder to.
【0016】[0016]
【実施例】次に本発明の具体的態様を示すために、本発
明を実施例に基づいて説明する。以下に述べる実施例は
本発明の技術的範囲を限定するものではない。 <実施例> 次の方法により図1に示すサーミスタを作製した。先ず
市販の炭酸マンガン、炭酸ニッケル、炭酸コバルトを出
発原料とし、これらをMnO2:NiO:CoOに換算
して金属原子比3:1:2の割合でそれぞれ秤量した。
秤量物をボールミルで16時間均一に混合した後に脱水
乾燥した。次いでこの混合物を900℃で2時間仮焼
し、この仮焼物を再びボールミルで粉砕して脱水乾燥し
た。粉砕物に有機結合材を加え、均一に混合した後、混
合物を直方体に圧縮成形した。この圧縮成形物を大気圧
下、1200℃で4時間焼成し、たて約35mm、よこ
約50mm、厚さ約10mmのセラミック焼結ブロック
(図示せず)を作製した。次にこのブロックをバンドソ
ーでウエハ状に切断し、図2に示すたて約35mm、よ
こ約50mm、厚さ約0.5mmの焼結シート21を得
た。EXAMPLES Next, the present invention will be described based on examples to show specific embodiments of the present invention. The embodiments described below do not limit the technical scope of the present invention. <Example> The thermistor shown in FIG. 1 was produced by the following method. First, commercially available manganese carbonate, nickel carbonate, and cobalt carbonate were used as starting materials, and these were weighed at a metal atomic ratio of 3: 1: 2 in terms of MnO 2 : NiO: CoO.
The weighed product was uniformly mixed by a ball mill for 16 hours and then dehydrated and dried. Next, the mixture was calcined at 900 ° C. for 2 hours, and the calcined product was again pulverized by a ball mill and dehydrated and dried. After adding an organic binder to the pulverized material and mixing uniformly, the mixture was compression-molded into a rectangular parallelepiped. This compression molded product was fired at 1200 ° C. for 4 hours under atmospheric pressure to produce a ceramic sintered block (not shown) having a length of about 35 mm, a width of about 50 mm, and a thickness of about 10 mm. Next, this block was cut into a wafer by a band saw to obtain a sintered sheet 21 having a length of about 35 mm, a width of about 50 mm, and a thickness of about 0.5 mm shown in FIG .
【0017】次に、図3及び図4に示すように、焼結シ
ート21の両面全体に貴金属粉末と無機結合材を含む導
電性ペーストを印刷法により塗布した。導電性ペースト
は市販のAgペースト(デュポン社製JPN−117
6)であって、Ag粉末と、SiO2,TiO2,B
2O3,Na2O及びK2Oからなるガラス微粒子と、有機
ビヒクルとからなる。導電性ペーストを塗布したサーミ
スタ素体を大気圧下、乾燥した後、30℃/分の速度
で、820℃まで昇温しそこで10分間保持し、30℃
/分の速度で室温まで降温してAgからなる焼付け電極
層の下地電極層16,16を得た。Next, as shown in FIG. 3 and FIG. 4 , a conductive paste containing a noble metal powder and an inorganic binder was applied to both surfaces of the sintered sheet 21 by a printing method. The conductive paste is a commercially available Ag paste (JPN-117 manufactured by DuPont).
6) wherein Ag powder, SiO 2 , TiO 2 , B
It is composed of glass fine particles composed of 2 O 3 , Na 2 O and K 2 O, and an organic vehicle. After the thermistor body coated with the conductive paste is dried under atmospheric pressure, the temperature is increased to 820 ° C. at a rate of 30 ° C./min, and held there for 10 minutes.
The temperature was lowered to room temperature at a rate of / min to obtain the underlying electrode layers 16 and 16 of the baked electrode layer made of Ag.
【0018】図5に示すように、電解めっき法により下
地電極層16,16の各表面に厚さ1〜2μmのNiめ
っき層17aを形成し、続いてその上に、同様に厚さ3
〜6μmのSnめっき層17bを形成した(図1)。続
いて上記切断機を用いて矢印Mの箇所で焼結シート21
を短冊状に切断した後、同一の切断機を用いて矢印Nの
箇所で短冊状サーミスタ素体の切断面と垂直な方向でチ
ップ状に切断して、図6に示すように幅W=約0.5m
m、長さL=約1.0mm、厚さT=約0.5mmのサ
ーミスタ10を得た。 As shown in FIG . 5 , a Ni plating layer 17a having a thickness of 1 to 2 μm is formed on each surface of the base electrode layers 16 and 16 by electrolytic plating, and then a Ni plating layer 17 having a thickness of 3 μm is formed thereon.
A Sn plating layer 17b of about 6 μm was formed (FIG. 1). Subsequently, the sintered sheet 21 is cut at the position indicated by the arrow M by using the above-described cutting machine.
Is cut into strips using the same cutting machine, and cut into chips in the direction perpendicular to the cut surface of the strip-shaped thermistor body at the location of arrow N, as shown in FIG. 0.5m
m, a length L = about 1.0 mm, and a thickness T = about 0.5 mm were obtained .
【0019】<比較例> Niめっき層とSnめっき層を設けずに、Ag80%と
Pd20%を含む導電性ペーストを850℃で焼付けて
Ag−Pdからなる焼付け電極層のみで端子電極を構成
した。それ以外は上記実施例と同様にサーミスタを作製
した。Comparative Example A conductive electrode containing 80% of Ag and 20% of Pd was baked at 850 ° C. without providing a Ni plating layer and a Sn plating layer to form a terminal electrode only with a baked electrode layer made of Ag-Pd. . Otherwise, a thermistor was manufactured in the same manner as in the above-described example.
【0020】<比較試験と結果> ・はんだ付着性 実施例のサーミスタと比較例のサーミスタを20個ずつ
用意し、230℃の温度で溶融させたAg入りの共晶は
んだ(H60−A)浴中にピンセットで試料を挟んで4
秒間浸漬し、端子電極のはんだ付着面積を光学顕微鏡で
調べた。その結果を表1に示す。 ・はんだ耐熱性 実施例のサーミスタと比較例のサーミスタを20個ずつ
用意し、270℃の温度で溶融させたAg入りの共晶は
んだ(H60−A)浴中にピンセットで試料を挟んで1
0秒間浸漬し、端子電極の消失状態を光学顕微鏡で調べ
た。その結果を表1に示す。<Comparative Test and Results> Solder Adhesiveness The thermistor of the example and the thermistor of the comparative example were prepared in a quantity of 20 each, and were placed in an Ag-containing eutectic solder (H60-A) bath melted at 230 ° C. Sandwich the sample with tweezers
After immersion for 2 seconds, the solder adhesion area of the terminal electrode was examined with an optical microscope. Table 1 shows the results. Solder Heat Resistance Twenty pieces each of the thermistor of the example and the thermistor of the comparative example were prepared.
After immersion for 0 second, the disappearance of the terminal electrode was examined with an optical microscope. Table 1 shows the results.
【0021】[0021]
【表1】 [Table 1]
【図1】本発明のサーミスタの外観斜視図。FIG. 1 is an external perspective view of a thermistor of the present invention.
【図2】本発明のサーミスタのサーミスタ素体となるセ
ラミック焼結シートの外観斜視図。FIG. 2 is an external perspective view of a ceramic sintered sheet as a thermistor body of the thermistor of the present invention.
【図3】その焼結シートの両面全体に下地電極層が形成
された斜視図。FIG. 3 is a perspective view in which a base electrode layer is formed on both sides of the sintered sheet.
【図4】図3のF部拡大斜視図。FIG. 4 is an enlarged perspective view of a portion F in FIG. 3 ;
【図5】図4の焼結シートの両面の下地電極層の各表面
にめっき層が形成された斜視図。FIG. 5 is a perspective view in which a plating layer is formed on each surface of a base electrode layer on both surfaces of the sintered sheet of FIG. 4 ;
【図6】図5の焼結シートをチップ状に切断した斜視
図。FIG. 6 is a perspective view of the sintered sheet of FIG. 5 cut into chips.
【図7】本発明のサーミスタの基板取付体の斜視図。FIG. 7 is a perspective view of a substrate mounting body of the thermistor of the present invention.
【図8】図7の基板取付体を接合したサーミスタの斜視
図。FIG. 8 is a perspective view of a thermistor to which the substrate mounting body of FIG. 7 is joined.
【図9】図7の基板取付体を別の方法で接合したサーミ
スタの斜視図。FIG. 9 is a perspective view of a thermistor to which the substrate mounting body of FIG. 7 is joined by another method.
【図10】本発明のサーミスタの別の基板取付体の斜視
図。FIG. 10 is a perspective view of another substrate mounting body of the thermistor of the present invention.
【図11】図10の基板取付体を接合したサーミスタの
斜視図。FIG. 11 is a perspective view of a thermistor to which the substrate mounting body of FIG. 10 is joined.
【図12】本発明のサーミスタの別の基板取付体の斜視
図。FIG. 12 is a perspective view of another substrate mounting body of the thermistor of the present invention.
【図13】図12の基板取付体を接合したサーミスタの
斜視図。FIG. 13 is a perspective view of a thermistor to which the substrate mounting body of FIG. 12 is joined.
【図14】本発明のサーミスタの更に別の基板取付体の
斜視図。FIG. 14 is a perspective view of still another substrate mounting body of the thermistor of the present invention.
【図15】図14の基板取付体を接合したサーミスタの
斜視図。FIG. 15 is a perspective view of a thermistor to which the substrate mounting body of FIG. 14 is joined.
【符号の説明】 10 サーミスタ 11 サーミスタ素体 12 端子電極 16 下地電極層 17 めっき層 17a Niめっき層 17b Sn又はSn/Pbめっき層 21 セラミック焼結シート 30a 金属素体 30b Sn又はSn/Pbめっき層 31,32,33,34 基板取付体[Description of Signs] 10 Thermistor 11 Thermistor element 12 Terminal electrode 16 Base electrode layer 17 Plating layer 17a Ni plating layer 17b Sn or Sn / Pb plating layer 21 Ceramic sintered sheet 30a Metal element 30b Sn or Sn / Pb plating layer 31, 32, 33, 34 Board mounting body
Claims (8)
(11)の相対向する両側面に一対の端子電極(12,12)が形
成されたサーミスタにおいて、 前記端子電極(12)が貴金属を含む下地電極層(16)と前記
下地電極層(16)の表面に形成されためっき層(17)とから
なる積層電極であって、前記積層電極の4つの側面が前
記一対の端子電極(12,12)が形成されないサーミスタ素
体の他の4面と同一面をなし、かつリードフレーム又は
ブロックからなる導電性のある一対の基板取付体(31,3
2,34)の各主面が高温クリームはんだにより前記一対の
端子電極(12)の各主面に接合されたことを特徴とするサ
ーミスタ。1. A chip-shaped thermistor element comprising a hexahedron
(11) In the thermistor having a pair of terminal electrodes (12, 12) formed on opposite side surfaces thereof, the terminal electrode (12) includes a base electrode layer (16) containing a noble metal and the base electrode layer (16). And a plating layer (17) formed on the surface of the laminated electrode, wherein the four side surfaces of the laminated electrode and the other four surfaces of the thermistor element body on which the pair of terminal electrodes (12, 12) are not formed. name the same plane, and the lead frame or
A pair of conductive board mounts consisting of blocks (31, 3
Each main surface of (2,34) is made up of a pair
A thermistor characterized by being joined to each main surface of a terminal electrode (12) .
ム(31)である請求項1記載のサーミスタ。2. The thermistor according to claim 1, wherein the thermistor is a system.
ム(32)であって、前記リードフレーム(32)の折曲げ間隔(32), the bending interval of the lead frame (32)
がサーミスタ素体(11)の厚さに相応する請求項1記載の2 corresponds to the thickness of the thermistor body (11).
サーミスタ。Thermistor.
ある請求項1記載のサーミスタ。The thermistor according to claim 1.
(11)の相対向する両側面に一対の端子電極(12,12)が形A pair of terminal electrodes (12, 12) are formed on opposite side surfaces of (11).
成されたサーミスタにおいて、In the formed thermistor, 前記端子電極(12)が貴金属を含む下地電極層(16)と前記The terminal electrode (12) is a base electrode layer (16) containing a noble metal and the
下地電極層(16)の表面に形成されためっき層(17)とからWith the plating layer (17) formed on the surface of the base electrode layer (16)
なる積層電極であって、前記積層電極の4つの側面が前Wherein the four side surfaces of the laminated electrode are located on the front.
記一対の端子電極(12,12)が形成されないサーミスタ素Thermistor element where the pair of terminal electrodes (12, 12) are not formed
体の他の4面と同一面をなし、かつ四角筒状のリードフA rectangular tube-shaped lead frame that is flush with the other four surfaces of the body
レームからなる導電性のある一対の基板取付体(33)の内Of a pair of conductive board mounting bodies (33)
面が高温クリームはんだにより前記一対の端子電極(12,The surface of the pair of terminal electrodes (12,
12)を含む前記サーミスタ素体(11)の両側部に接合され12) is joined to both sides of the thermistor body (11) including
たことを特徴とするサーミスタ。A thermistor.
形成されたNiめっき層(17a)と、このNiめっき層(17
a)の表面に形成されたSn又はSn/Pbめっき層(17
b)とを有する請求項1ないし5いずれか記載のサーミス
タ。 6. A Ni plating layer (17a) having a plating layer (17) formed on the surface of a base electrode layer (16), and a Ni plating layer (17).
a) Sn or Sn / Pb plating layer (17)
The thermistor according to any one of claims 1 to 5 , comprising: b).
る金属素体(30a)とこの素体の表面に形成されたSn又Metal body (30a) and Sn or
はSn/Pbめっき層(30b)とを備えた請求項1ないしAnd a Sn / Pb plating layer (30b).
6いずれか記載のサーミスタ。6. The thermistor according to any one of 6.
(21)の両面全体に下地電極層(16,16)を形成する工程
と、 前記下地電極層(16,16)の各表面にNiめっき層(17a)及
びSn又はSn/Pbめっき層(17b)をこの順に形成す
る工程と、 前記下地電極層(16)とめっき層(17)とからなる積層電極
を両面に形成した焼結シート(21)をダイシングソーによ
りチップ状に切断してチップ状サーミスタ素体(11)の相
対向する両側面に一対の端子電極(12,12)を設ける工程
と、 前記一対の端子電極(12)の各主面にリードフレーム又は
ブロックからなる導電性のある一対の基板取付体(31,3
2,34)の各主面を高温クリームはんだにより接合する工
程と を含むサーミスタの製造方法。8. A ceramic sintered sheet for a thermistor body
Forming a base electrode layer (16, 16) on both surfaces of the (21); and forming a Ni plating layer (17a) and a Sn or Sn / Pb plating layer (17b) on each surface of the base electrode layer (16, 16). ) In this order, and a sintered sheet (21) formed on both sides of a laminated electrode comprising the base electrode layer (16) and the plating layer (17) is cut into a chip shape by a dicing saw to form a chip shape. A step of providing a pair of terminal electrodes (12, 12) on opposite side surfaces of the thermistor body (11)
And a lead frame or on each main surface of the pair of terminal electrodes (12).
A pair of conductive board mounts consisting of blocks (31, 3
(2, 34) bonding each main surface with high-temperature cream solder
And a method for manufacturing a thermistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34347392A JP3148026B2 (en) | 1992-11-30 | 1992-11-30 | Thermistor and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34347392A JP3148026B2 (en) | 1992-11-30 | 1992-11-30 | Thermistor and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06168803A JPH06168803A (en) | 1994-06-14 |
| JP3148026B2 true JP3148026B2 (en) | 2001-03-19 |
Family
ID=18361801
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP34347392A Expired - Lifetime JP3148026B2 (en) | 1992-11-30 | 1992-11-30 | Thermistor and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3148026B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101471829B1 (en) | 2010-06-24 | 2014-12-24 | 티디케이가부시기가이샤 | Chip thermistor and method of manufacturing same |
-
1992
- 1992-11-30 JP JP34347392A patent/JP3148026B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06168803A (en) | 1994-06-14 |
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