JP3149820B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device.

[0002]

2. Description of the Related Art Hitherto, a multilayer capacitor has been manufactured as follows. First, as shown in FIG. 18A, an oxide film 2 is formed on a Si substrate 1, and a resist 3 is applied thereon and patterned. Next, oxide film 2 is etched using resist 3 as a mask (FIG. 18B). After that, as shown in FIG. 19C, a polysilicon 4 is deposited, a resist 5 is applied, and then patterned, and the polysilicon 4 is etched and processed. This polysilicon 4 becomes a lower electrode. Thereafter, as shown in FIG. 19D, a capacitance insulating film 6 is formed on the surface of the polysilicon 4 and further an upper electrode 7 is formed. This element is used as a capacitive element in a wide range in a semiconductor device such as a dynamic memory (DRAM).

[0003] Recently, miniaturization of device dimensions has been progressing for high integration. Taking a semiconductor memory element as an example, as the miniaturization progresses, the element area becomes smaller, and the area in which a capacitor portion can be formed has become very narrow. In order to solve this, proposal of a device structure and formation of a three-dimensional capacitor unit structure have been advanced. However, even with this method, many problems remain in the device processing process in order to sufficiently secure the area of the capacitor.

The International Electron Device Meeting (International E)
LECTRON DEVICES Meeting) 1
November 988, pp. 596-599, New Stacked Capacitor Deal RAM Cell Characterized Via Storage Capacitor on a Bit-Line Structure (A New)
Stacked Capacitor DRAM Ce
ll Characterized by a Store
age Capacitor on a Bit-li
As shown in a paper published under the title of “Ne Structure”, the device structure is devised so that the area of the storage electrode can be further increased. However, even with this method, the only way to ensure a sufficient area of the capacitor portion is to increase the thickness of polysilicon, which is a storage electrode, to increase the area. This makes the polysilicon processing difficult.

[0005]

As an attempt to increase the surface area of polysilicon, Solid State Device and Materials (Solid State Dev) has been proposed.
ices and Materials) 1989,
Capacities-Enhanced on pages 137-140
Stacked-Capacitor We Engraved
Storage Electrode For Deep Submicron Deep Rams (Capacitance-E
enhanced Stacked-Capacitor
withEngraved Storage Ele
ctrode for DeepSubmicron
As shown in a paper entitled "DRAMs", resist particles are mixed into the SOG film and applied to the polysilicon surface, and then the SOG is etched to etch the polysilicon surface using the resist particles as a mask. Attempts have been made to increase the surface area. However, this method has three problems. In other words, (I) the particle size of the resist must be properly controlled, (II) resist particles must be applied at a uniform density on the wafer when applied, and (III) the process is complicated. There is a point.

An object of the present invention is to provide a method of manufacturing a semiconductor device having a large silicon surface area without the problems (I), (II) and (III).

[0007]

A semiconductor device according to the present invention is characterized in that silicon having fine irregularities due to grains on at least a part of its surface is used as an electrode.

The method of manufacturing a semiconductor device according to the present invention is characterized in that a silicon film having a large surface area is deposited at a transition temperature at which the crystalline state of the deposited film changes from an amorphous phase to a polycrystal.

Further, as a manufacturing method of the present invention, there is a method of depositing a silicon film at the above-mentioned transition temperature and thereafter annealing this silicon film at the transition temperature or higher.

Further, as a manufacturing method of the present invention, there is also a method of depositing a silicon film at the above-mentioned transition temperature, and further depositing polysilicon on the silicon film at a temperature higher than the above-mentioned transition temperature.

Further, as a manufacturing method according to the present invention, a first silicon film is deposited, a second silicon film having a large surface area at a transition temperature is deposited thereon, and then dry etching is performed on the first silicon film. There is also a method of transferring irregularities on the surface of the second silicon film.

(Function) When the present inventor deposits silicon by LPCVD or the like, if the deposited film is grown at a transition temperature at which the crystalline state of the deposited film changes from an amorphous phase to a polycrystal, a minute surface caused by silicon grain growth is formed on the surface. It has been found that unevenness occurs at a high density and the surface area of the film can be increased.

It is considered that a silicon film grown at a transition temperature at which an amorphous phase changes to a polycrystal is not sufficiently dense. This is presumed from the fact that, for example, when a silicon film grown at a transition temperature is subjected to wet etching, the etching rate is higher than that of a polysilicon film deposited at a normal deposition temperature (higher than the transition temperature).

If an extremely thin capacitive insulating film having a thickness of 50 Å is formed on the surface, pinholes may be generated. To be precise,
The silicon film deposited at the above temperature may be heat-treated at a temperature higher than the transition temperature, for example, at 600 ° C. or higher. The heat treatment does not significantly change the irregularities. Then, if a capacitor insulating film is formed, the occurrence of pinholes can be prevented. This heat treatment may be combined with the heat treatment at the time of impurity addition. Instead of heat-treating at a temperature higher than the transition temperature, dense polysilicon may be deposited on top of such a thickness that fine irregularities do not occur, and a capacitive insulating film may be formed on the polysilicon. Dense polysilicon can be deposited above 560 ° C. According to such a method, the manufacturing process is simple, and a silicon film having a large surface area and a small variation can be formed. If this silicon film is used, for example, as an electrode of a capacitance portion of a semiconductor memory, the volume occupied by the capacitance portion is the same and the surface area, that is, the capacitance value can be increased.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION

Example 1 FIGS. 5 to 7 show the surface state and crystallinity of silicon films formed at various deposition temperatures. FIG. 8 shows the dependence of the capacitance and the surface area of the silicon film on the deposition temperature.
The deposition is performed by the LPCVD method, and the gas used is SiH ₄ + He.
(SiH ₄ : 20%, He: 80%), pressure is 1 torr
r. Deposition, as shown in FIG. 9, the thick SiO ₂ film 5
2 was performed on the Si substrate 50 on which was formed. FIG. 5 (a),
(C), (e), (g), and (i) of FIG.
Film thickness of 250 at 10,540,550,560,610 ° C
A scanning electron microscope (SEM) photograph of the surface of the deposited film when only 0 angstrom is deposited has a magnification of 100,000.
30 nm between dots arranged at the bottom of the photo, 11
The distance from one end to the other of the arranged dots is 300 nm. The acceleration voltage is 20 kV. 5 (b), 5 (d), 6
(F), (h) and FIG. 7 (j) correspond to FIG. 5 (a) and FIG.
It is a reflection high-speed electron beam diffraction (RHEED) photograph corresponding to (c), FIG.6 (e), (g), and FIG.7 (i).

820 ° C., 60 ° C.
Then, phosphorus diffusion is performed under the conditions described above, a capacitor insulating film 56 is formed on the surface, and a polysilicon film 58 serving as an upper electrode is formed thereon. Capacitance forming insulating film firstly the Si ₃ N ₄ film is formed by LPCVD on the silicon film, after which Si ₃
The surface of the N ₄ film is oxidized. The temperature of the Si ₃ N ₄ film is 780
° C, working gas SiH ₄ + NH ₃ (SiH ₄ / NH ₃ = 1
/ 100) A 120 angstrom thick film was deposited at a pressure of 30 Pa, and the surface was oxidized by pyrogenic oxidation at 900 ° C. and wet 1: 1 to an extent that the thickness of the 120 angstrom increased by 20 angstrom in terms of an oxide film. Under these conditions, the capacitance insulating film is equivalent to 100 angstroms (expressed as “def”) in terms of a SiO ₂ film. If it is desired to form a thinner, for example, a capacitance insulating film having a def = 50 Å, a Si ₃ N ₄ film may be formed to 60 Å, and the film may be oxidized to an extent that increases by 10 Å in terms of an oxide film. deff =
After forming a 100 angstrom capacitive insulating film,
Polysilicon was deposited thereon at 600 ° C., and then phosphorus was diffused. Thereafter, the substrate was divided into 1 mm × 1 mm sizes by a lithography technique and a dry etching technique to obtain a stacked capacitor as shown in FIG.

As shown in FIG. 5A, the surface of the silicon film deposited at 510 ° C. is very smooth, no grain growth is observed, and the surface area is as small as 1 mm ² . The capacitance of the capacitor was 3.5 nF as shown in FIG. RHE
The ED photograph FIG. 5 (b) shows no pattern, indicating that the film is amorphous. Figure 5 deposited at 540 ° C
In the case of (c), grains grow partially and are mixed with amorphous. The RHEED photograph FIG. 5 (d) also shows that a ring-shaped pattern appears and crystals are partially formed. At this time, the capacitance of the capacitor was 3.8 nF, which was slightly increased due to the partial growth of the grains. When the deposition temperature is slightly increased to 550 ° C., hemispherical grains having a diameter of about 700 angstroms are formed densely and uniformly, as shown in FIG. I do. As can be seen from FIG. 8, the capacitance is 7.3 nF, the surface area is 2.1 mm ^2, which is more than double that at 510 ° C. In the RHEED photograph FIG. 6 (f), an annular pattern is seen, and it can be seen that the crystal is crystallized.

When the deposition temperature is further increased to 560 ° C., as shown in FIG. 6 (g), the diameter of the grains becomes large and the surface irregularities become gentle. Reflecting this, the capacitance surface area was reduced to 3.6 nF, 1.07 m as shown in FIG.
m ² , which is not much different from the case of 510 ° C. R
In the HEED photograph of FIG. 6 (h), speckles of the backscattered electron diffraction can be seen, and the polysilicon is highly oriented. By further increasing the deposition temperature to 610 ° C., which is close to the deposition temperature of normal polysilicon used for LSIs and the like, FIG.
As shown in (i), the diameter of the grains is further increased,
The surface is also smooth, and as shown in FIG. 7 (j), speckles of the backscattered electron diffraction are observed, and the polysilicon is formed. capacity,
The surface area hardly changes from that at 560 ° C.

As described above, at the temperature (transition temperature) in the region where the crystalline state of the deposited silicon film transitions from amorphous to polycrystal, very fine irregularities occur on the film surface as compared with other temperatures, and the surface area increases. You can see that Under the conditions of the present example, the transition temperature was between 540 and 560 ° C. However, the measured value of the deposition temperature changes slightly depending on the position of the thermocouple for temperature measurement in the LPCVD apparatus.
It is advisable to calibrate each device.

The surface state of the silicon film on which the irregularities have been formed does not change significantly by the subsequent heat treatment. 5
The film of FIG. 6E deposited at 50 ° C.
FIG. 10 shows an SEM photograph of the surface state when phosphorus has been diffused for 0 minutes.

FIG. 11 shows the surface area distribution (representative point) in a 4-inch wafer when a silicon film is formed at 550 ° C. and then subjected to a phosphorus diffusion process under the conditions of FIG.
Is shown. The measurement was performed using the stacked capacitor described with reference to FIG. The numerical value in the figure indicates how many times the surface area when formed at 510 ° C., but it can be seen that it is very uniform. Also, the reproducibility is good. Similarly, wafer-to-wafer and lot-to-lot are uniform and reproducibility is good.

FIG. 12 shows the leakage current characteristics of the stacked capacitor (the structure of FIG. 9) when the deposition temperatures are 550 ° C. and 600 ° C. Although the temperature is slightly deteriorated at 550 ° C., when used in a semiconductor memory, the voltage applied to the capacitor is up to 5 V (3.3 V in recent years).
There is almost no difference in the leakage current at both 600 ° C. and 600 ° C., and if the well-known Ｖ Vcc cell plate technology is used,
There is practically no problem because the applied voltage is halved.

Here, the leakage current characteristics when the same capacitance is secured will be compared. 64MDR with normal stacked structure
Considering the fabrication of AM, 6
It is said that when polysilicon deposited at about 00 ° C. is used, a capacitance insulating film thickness of about 50 Å in oxide film equivalent film thickness (def) is required. However, the use of the silicon film of the present invention makes it possible to use a capacitance insulating film of 100 Å. Therefore, FIG. 13 shows these two typical leak current characteristics. As you can see,
The voltage that can be used as a device and is suppressed to a leak current of 1 × 10 ⁻⁸ A / cm ² or less is 2.0 V in the conventional type.
It is. On the other hand, when silicon at 550 ° C. is used, this voltage becomes 5.4 V, and the leakage current characteristics can be greatly improved.

FIG. 14 shows the breakdown voltage distributions at 550 ° C. and 600 ° C. The upper part of the figure is 600 ° C and the lower part is 550.
At ° C., measurements were made on several wafers using a stacked capacitor having the same structure as in FIG. 9 as a capacitor. At this time, the capacitance insulating film thickness is 100 Å.
Although the planar dimensions of the capacitor are the same, the surface area of the silicon film 54 at 550 ° C. is approximately twice that of 600 ° C. at 550 ° C., so the capacitor area is also twice as large. The withstand voltage at 600 ° C. was 9.5 MV / cm, 55
At 0 ° C., the peak value is 8.7 MV / cm,
Although it is deteriorated by V / cm, there is no particular problem in actual use. Also, the variation in the withstand voltage is almost the same as that at 600 ° C., which is very good.

[Embodiment 2] Although the surface area can be increased by forming a silicon film by the method shown in Embodiment 1, it is considered that the formed silicon film does not have a dense film quality. Therefore, it is preferable to perform annealing at a temperature higher than the transition temperature before forming the capacitance insulating film. FIG. 15 shows 550 ° C. (FIG. 6)
An SEM photograph of the surface of the silicon film deposited under the condition (e) when the silicon film was annealed in a nitrogen atmosphere at 700 ° C. is shown. Thereafter, phosphorus was diffused in the same manner as in Example 1, a capacitor insulating film was formed, polysilicon serving as an upper electrode was deposited, and a stacked capacitor similar to that of FIG. 9 was formed. The capacitance and the surface area of the capacitor are twice those at 600 ° C. as in the first embodiment, and the distribution within the wafer, between the wafers and between the lots is very uniform as in the first embodiment, and the reproducibility is good. In addition, the same good results as in the case where the deposition temperature was 600 ° C. were obtained with respect to the leak current characteristics and the breakdown voltage.

Although the annealing is performed at 700 ° C. in this embodiment, the annealing may be performed at a low temperature such as 600 ° C. for a long time to densify, or the annealing may be performed at a high temperature such as 800 ° C.

[Embodiment 3] In this embodiment, a dense polysilicon film is deposited on the silicon film formed at the transition temperature at a temperature higher than the transition temperature, instead of the annealing of the second embodiment. Here, a polysilicon film was deposited at 300 Å at 600 ° C., which is a commonly used temperature. FIG. 16 is an SEM photograph showing the surface state after deposition. There is no significant change in the surface condition.

Thereafter, a stacked capacitor was formed in the same manner as in Example 2, and the capacitance and surface area were measured. Was very uniform and the reproducibility was good. In addition, good results were obtained in which the leak current characteristics and the breakdown voltage were almost the same as those at a deposition temperature of 600 ° C.

If the polysilicon is deposited too thick, the fine irregularities on the surface of the underlying silicon film will be buried.

[Embodiment 4] In this embodiment, a stacked capacitor having a capacitance portion formed on the side surface will be described.

First, as shown in FIG.
An oxide film 2 is formed thereon, a resist 3 is applied thereon and patterned, and the oxide film 2 is etched by dry etching (FIG. 1B).

Thereafter, as shown in FIG. 2C, a polysilicon film 4 is deposited, and impurities such as phosphorus and arsenic are added by thermal diffusion. The polysilicon film 4 was deposited by LPCVD under normal conditions. The conditions are as follows: temperature: 600 ° C, gas: SiH <sub>4
+ He (SiH 4: 20%</sub> , He: 80%), pressure 1T
orr. An oxide film 8 is formed on the polysilicon film 4 by a CVD method, and a polysilicon film 9 is further formed thereon under the same conditions as the polysilicon film 4. A resist 10 is applied thereon and patterned (FIG. 2C), and dry etching is performed to the polysilicon 4 using the resist as a mask (FIG. 2C).
(D)). After removing the resist 10, a silicon film 11 having fine irregularities on the surface was deposited at 555 ° C. (FIG. 3).
(E)). Conditions other than the temperature are the same as those of the polysilicon film 4.

Thereafter, annealing was performed at 700 ° C. in a nitrogen atmosphere for 30 minutes. Next, phosphorus or arsenic is added to the silicon film 11 by thermal diffusion.

Thereafter, RIE (Re) is performed using Cl ₂ gas.
active Ion Etching)
The stacked capacitor of (f) is formed. The top and side surfaces of this silicon reflect R
After the IE, the surface area is large. That is, in the upper part, the irregularities of the silicon film 11 are transferred to the polysilicon film 9. Without the polysilicon film 9, the upper portion of the stacked capacitor is lost during RIE, and only the side surface remains.

Next, a capacitor insulating film 12 is formed under the same conditions as in the first embodiment, and a phosphorus-doped polysilicon 13 is further deposited (FIG. 4G).

In this way, a capacitance portion is also formed on the side surface, and a stacked capacitor having a very large capacitance value can be formed. If the oxide film 8 is made thicker, the area of the side surface becomes larger and the capacitance value increases accordingly. FIG. 17 (a),
(B) SEM of the stacked capacitor actually formed
The picture is shown. (A) is 40,000 times and (b) is 25,000 times. One of the foremost capacitors is exposed in cross section. From this, it can be seen that the silicon film surface has sufficient irregularities even after dry etching.

The oxide film 8 is replaced by phosphorus oxide glass (PSG) or boron phosphorus oxide glass (BP).
SG), an impurity-doped polysilicon, a silicon nitride film, a laminated film thereof, or the like. In this embodiment, FIG.
The silicon film 11 having fine irregularities in FIG.
When the IE is performed, but there is a possibility that the unevenness on the side surface may be lost at the time of etching, for example, HTO (Hig
h Temperature Oxidation) C
When the SiO ₂ film is formed on the entire surface slightly with VD and RIE is performed, the side walls can be surely protected. S left on the side after RIE
The iO ₂ film may be removed by wet etching or the like.

In the above-described embodiment, the polysilicon film 9 formed at 600 ° C. is used as a film for transferring the unevenness of the silicon film 11, but a silicon film deposited at a transition temperature or a lower temperature may be used. Examples 1 to 4
In the above, thermal diffusion was used for all doping of the silicon film, but ion implantation may be used, or PH may be used as a source gas at the time of deposition.
₃ , a method of containing a dopant gas such as AsH ₃ may be used. The dopant may be boron or the like in addition to phosphorus and arsenic. Further, in the first to fourth embodiments, the example in which the unevenness is formed on the entire surface of the silicon films 11 and 54 in the portion to be the capacitor is shown. The capacitance value is larger than that of a simple polysilicon film, which is also included in the present invention.

The present invention is not limited to a stacked capacitor, but may be a BSCC (Buried Stacked Cap).
activator Cell) and IVEC (Isolati)
on-merged Vertical Capaci
tor Cell). Not only DRAM, but also EEPROM
Can be applied to the floating gate.

[0040]

According to the present invention, the surface area of silicon, which is the electrode of the capacitor, can be greatly increased with the same volume of the conventional capacitor. In addition, a silicon film having a large surface area and a small variation can be easily formed.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view illustrating an embodiment of the present invention.

FIG. 2 is a schematic sectional view illustrating an embodiment of the present invention.

FIG. 3 is a schematic sectional view illustrating an embodiment of the present invention.

FIG. 4 is a schematic sectional view illustrating an embodiment of the present invention.

FIGS. 5 (a) and 5 (c) are scanning electron micrographs showing the change in the particle structure of the silicon surface depending on the deposition temperature, and FIGS.
(D) is a high-speed reflection electron beam diffraction photograph showing the change in the crystal structure of silicon depending on the deposition temperature.

FIGS. 6 (e) and (g) are scanning electron micrographs showing changes in the particle structure of the silicon surface with the deposition temperature, and FIGS.
(H) is a high-speed reflection electron beam diffraction photograph showing a change in the crystal structure of silicon depending on the deposition temperature.

FIG. 7 (i) is a scanning electron micrograph showing the change in the particle structure of the silicon surface depending on the deposition temperature, and FIG. 7 (j) is a high-speed reflection electron diffraction photograph showing the change in the crystal structure of silicon depending on the deposition temperature.

FIG. 8 is a diagram showing changes in the surface area of a silicon film and the capacitance of a capacitor depending on the deposition temperature.

FIG. 9 is a cross-sectional view showing the structure of the stacked capacitor of the example.

FIG. 10 is a scanning electron micrograph showing the particle structure of a silicon surface when phosphorus diffusion is performed.

FIG. 11 is a diagram showing a distribution of a surface area of a silicon film in a 4-inch wafer.

FIG. 12 is a diagram showing leakage current characteristics.

FIG. 13 is a diagram showing leakage current characteristics.

FIG. 14 is a diagram showing a distribution of breakdown voltage.

FIG. 15 is a scanning electron micrograph showing the particle structure of the silicon surface when annealed at 700 ° C.

FIG. 16 is a scanning electron micrograph showing a grain structure of a silicon film surface when polysilicon is formed on the surface.

FIG. 17 is a scanning electron micrograph showing a particle structure of a silicon surface when a stacked capacitor is formed.

FIG. 18 is a schematic cross-sectional view showing a conventional method for manufacturing a stacked capacitor.

FIG. 19 is a schematic cross-sectional view showing a method for manufacturing a conventional stacked capacitor.

[Explanation of symbols]

 Reference Signs List 1 silicon substrate 2 oxide film 3 resist 4 polysilicon 5 resist 6 capacitance insulating film 7 upper electrode 8 oxide film 9 polysilicon 10 resist 11 silicon film 12 capacitance insulating film 13 phosphorus-doped polysilicon 50 silicon substrate 52 oxide film 54 silicon film 56 Capacitive insulating film 58 Polysilicon film

Continuation of the front page (51) Int.Cl. ⁷ identification code FI H01L 27/115 29/788 29/792 (58) Investigated field (Int.Cl. ⁷ , DB name) H01L 27/108 H01L 21/822 H01L 21/8242 H01L 21/8247 H01L 27/04 H01L 27/115 H01L 29/788 H01L 29/792

Claims (24)

(57) [Claims] 1. A step of depositing a first silicon film on an insulating layer formed on one main surface of a semiconductor substrate, and forming a second silicon film having an uneven surface on the surface of the first silicon film. A method of manufacturing a semiconductor device, comprising: a step of depositing; and a step of transferring irregularities on a surface of a second silicon film to a first silicon film by anisotropic etching. 2. A step of depositing a first silicon film on an insulating layer formed on one main surface of a semiconductor substrate, and a transition of changing a crystalline state from amorphous to polycrystal on the surface of the first silicon film. A method for manufacturing a semiconductor device, comprising: a step of depositing a second silicon film at a temperature; and a step of transferring irregularities on the surface of the second silicon film to the first silicon film by anisotropic etching. 3. A core including a surface and a side surface substantially horizontal to the semiconductor substrate on at least an insulating layer formed on one main surface of the semiconductor substrate, and at least the horizontal surface portion is covered with a first silicon film. And depositing a second silicon film having irregularities on the surface of the first silicon film,
The second silicon film having the irregularities on the surface of the second silicon film transferred to the first silicon film on the horizontal surface of the core by anisotropic etching, and at least a part of the side surface of the core has irregularities on the surface. And a step of leaving a part of the film. 4. A core including a surface and a side surface substantially horizontal to the semiconductor substrate and at least a horizontal surface portion covered with a first silicon film is formed on an insulating layer formed on one main surface of the semiconductor substrate. And a step of depositing a second silicon film on the surface of the first silicon film at a transition temperature at which a crystalline state changes from amorphous to polycrystal. Transferring the irregularities on the surface of the second silicon film to the film and leaving at least a part of the second silicon film having irregularities on the surface on at least a part of the side surface of the core. A method for manufacturing a semiconductor device. 5. A plurality of cores are formed on an insulating layer formed on one main surface of a semiconductor substrate, the plurality of cores including a surface and a side surface substantially horizontal to the semiconductor substrate and at least the horizontal surface portion being covered with a first silicon film. And depositing a second silicon film having irregularities on the surface of the first silicon film by a thickness smaller than the height of the side surface of the plurality of cores facing the region separating the cores from each other. And transferring the unevenness of the surface of the second silicon film to the first silicon film in the horizontal plane portion of the core by anisotropic etching, and at least part of the side surface of the core has unevenness on the surface. Leaving a part of the second silicon film. 6. A plurality of cores are formed on an insulating layer formed on one main surface of the semiconductor substrate, the plurality of cores including a surface and a side surface substantially horizontal to the semiconductor substrate and at least the horizontal surface portion is covered with a first silicon film. And a step of forming a second silicon film on a surface of the first silicon film facing a region separating the cores from each other at a transition temperature at which a crystalline state changes from amorphous to polycrystal on the surface of the first silicon film. Depositing only a thickness smaller than the height, and transferring the irregularities of the second silicon film surface to the first silicon film in the horizontal surface portion of the core by anisotropic etching, and at least a part of the side surface portion of the core Leaving a portion of the second silicon film having irregularities on its surface. 7. The method for manufacturing a semiconductor device according to claim 2 , further comprising, after the step of depositing the second silicon film, a step of forming irregularities including a heat treatment step. A method of manufacturing a semiconductor device. 8. The method of manufacturing a semiconductor device according to claim 1 , wherein said first silicon film contains an impurity in advance. 9. The method for manufacturing a semiconductor device according to claim 5 , wherein at least a part of said second silicon film in said plurality of core isolation regions is removed in said anisotropic etching step. A method of manufacturing a semiconductor device, comprising separating the plurality of cores. 10. A method for manufacturing a semiconductor device according to claim 1 , wherein a step of depositing a silicon oxide film after said step of depositing said second silicon film;
A method for manufacturing a semiconductor device, comprising a dry etching step. 11. The method for manufacturing a semiconductor device according to claim 10 , further comprising a step of removing the silicon oxide film on the second silicon film by wet etching after the dry etching step. A method for manufacturing a semiconductor device. 12. The method of manufacturing a semiconductor device according to claim 1 , wherein a step of depositing a dielectric film on said first and second silicon film surfaces is performed. A method for manufacturing a semiconductor device, comprising a step of forming a third electrode layer on a film. 13. The method of manufacturing a semiconductor device according to claim 1 , wherein at least a part of said first silicon film is formed through an opening formed in said insulating layer. A method for manufacturing a semiconductor element, wherein the method is electrically connected to a substrate. 14. A method comprising: depositing a silicon film on a semiconductor substrate at a transition temperature at which a crystalline state changes from amorphous to polycrystal; and heat-treating the silicon film at a temperature higher than the transition temperature. A method for manufacturing a semiconductor device. 15. The method according to claim 14 , wherein the heat treatment does not involve impurity introduction. 16. The method according to claim 14 , further comprising a step of introducing an impurity into the silicon film after the heat treatment step. 17. The method according to claim 14 , further comprising: attaching a dielectric film on the surface of the silicon film; and forming an electrode layer on the dielectric film. A method for manufacturing a semiconductor device. 18. A semiconductor device comprising: a step of forming a silicon film having an uneven surface on a semiconductor substrate; and a step of depositing a polysilicon film having a thickness that does not allow the unevenness to be formed on the silicon film. Semiconductor device manufacturing method. 19. A step of depositing a silicon film having an uneven surface on a semiconductor substrate at a transition temperature at which a crystalline state changes from amorphous to polycrystal, and forming a poly film having a thickness such that the unevenness is not formed on the silicon film. Depositing a silicon film. 20. The method according to claim 18 , wherein the polysilicon film is deposited at a temperature higher than the transition temperature. 21. The method according to claim 18 , further comprising: attaching a dielectric film on the surface of the polysilicon film; and forming an electrode layer on the dielectric film. Of manufacturing a semiconductor device. 22. A step of forming a second silicon film having an uneven surface on the first silicon film, and forming an uneven surface of the second silicon film on the first silicon film by anisotropic etching. Transferring a semiconductor device. 23. depositing a second silicon film having irregularities on the surface at a transition temperature at which a crystalline state changes from amorphous to polycrystal on the first silicon film;
Transferring the irregularities on the surface of the second silicon film to the first silicon film by anisotropic etching. 24. The method according to claim 22 , further comprising the steps of: depositing a dielectric film on the surface of the second silicon film onto which the irregularities have been transferred; and forming an electrode layer on the dielectric film.
A method for manufacturing a semiconductor device according to claim 23 .