JP3231925B2 - Semiconductor input circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a complementary field effect transistor (hereinafter, referred to as CMOS.), BiCMOS walk is having both a bipolar transistor and a CMOS
The present invention relates to a semiconductor input circuit used in a semiconductor integrated device or the like configured as described above and converting the level of an input signal and supplying the converted signal to the semiconductor integrated device or the like.

[0002]

2. Description of the Related Art FIG. 2 is a circuit diagram showing a conventional semiconductor input circuit. This semiconductor input circuit has a first power supply potential V
dd and the second power supply potential Vss, and converts the level of the potential applied to the input terminal In ₁ to the output terminal O 1.
This is an input circuit supplied from ut ₁ to the semiconductor integrated device.
The semiconductor input circuit shown in FIG. 2 is configured such that P is controlled to be conductive based on the potential applied to each gate from the input terminal In _1.
Type channel field effect transistor (hereinafter, referred to as PMOS) 1 and an N type channel field effect transistor (hereinafter, referred to as PMOS) .
It is called NMOS . 2). The source of the PMOS1 is connected to the first power supply potential Vdd,
The drain is connected to the output terminal Out ₁ via the node N1. The source of the NMOS2 is connected to the second power supply potential Vss, and the drain of the NMOS2 is connected to the drain of the PMOS1 at the node N1. next,
The operation of the semiconductor input circuit of FIG. 2 will be described. The second power supply potential Vss is set to 0 volt of the ground potential and the second power supply potential Vss
Is set to the first power supply potential Vdd using 0 volts as a reference potential,
For example in a state in which applied by setting the 5 volts, applying 0 volts ground potential to the input terminal an In _1. At this time,
NMOS2 cutoff state, PMOS1 becomes conductive, the output terminal Out _1, 5 volt same potential as the first power supply potential Vdd is output. When the potential of the input terminal In ₁ is lower than a threshold potential (hereinafter, referred to as a threshold potential ) Vtn of the NMOS 2, the NMOS 2 is in a cutoff state, and the PMOS 1 is in a conductive state. Therefore, from the output terminal Out _1, the first power supply potential Vdd
The same 5 volts is output.

Next, a first power supply potential V is applied to an input terminal In ₁ .
When the same voltage of 5 volts as dd is applied, the PMOS 1 is cut off and the NMOS 2 is turned on. As a result, from the output terminal Out _1, second power supply potential Vs
The same 0 volts as s is output. When the potential of the input terminal In ₁ is between the first power supply potential Vdd and a potential lower than the first power supply potential Vdd by the threshold potential Vtp of the PMOS 1,
From immediately Chi 5 volts 5-| Vtp | For potential between the bolt, PMOS1 is cut off, NMOS 2 is rendered conductive. Therefore, the potential of the output terminal Out ₁ becomes
It becomes 0 volt, the same as the second power supply potential Vss. The potential applied to the input terminal In ₁ is equal to the threshold potential Vtn.
If the above, and it is less than the first power supply potential Vd d or et threshold potential Vtp content becomes lower potential, PMOS
1 and the NMOS 2 are turned on. At this time, each PM
The OS1 and resistance during conduction of NMOS 2, the potential of the output terminal Out ₁ is determined. Figure 3 is a diagram showing input and output characteristics of FIG. 2, an example of the potential output terminals Out ₁ for being applied to the input terminal In ₁ potential is shown. Here, the normal number of TTL (transistor-transistor logic) level used, for example, "H" level 2 Bo <br/> belt, "L" level is to configure the interface to 0.8 volt signal In this case, the threshold potential of the semiconductor input circuit of FIG. 2 is set to about 1.4 volts. In order to set the threshold potential of the semiconductor input circuit of FIG.
, The resistance ratio at the time of conduction may be set to about 2.5: 1. This makes it possible to configure an interface for a signal having a TTL level lower than the power supply potential Vdd .

[0004]

However, the conventional semiconductor input circuit has the following problems. P
The resistance ratio of the MOS1 and the NMOS2 when conducting is about 2.5: 1, and the threshold potential of the semiconductor input circuit is about 1.
By setting it to 4 volts, an interface can be configured for TTL level signals.
Since the resistance ratio during conduction of S1 and NMOS2 different, delay times of the rise and fall in the output signal from the output terminal Out ₁ is different. That is, the capacitance of the circuit in the next stage and the resistance of the PMOS 1 and the NMOS 2 when the PMOS 1 and the NMOS 2 are conductive constitute a delay circuit, and the delay time between the rise and the fall is the same as the resistance ratio when the PMOS 1 and the NMOS 2 are conductive. 2. In the conventional semiconductor input circuit of FIG.
At 5: 1, the delay is delayed with respect to the falling delay time. For this reason, it has been difficult to design an input circuit that interfaces with a TTL level signal at a high speed operation and is well balanced with respect to delay. Conversely, when changing the delay time of the rise and fall of the output signal, the interface level for the TTL level signal cannot be set appropriately. The present invention has a problem that the prior art has a problem that there is a difference between a delay time of a rise and a fall of an output signal, and a case of an interface configuration for a TTL level signal. It is an object of the present invention to provide a semiconductor input circuit which solves a problem that a delay time of rising and falling cannot be set independently.

[0005]

To solve the previous SL problems SUMMARY OF THE INVENTION The first aspect of the present invention, contact the semiconductor input circuit
Input an input signal that transitions between the first potential and the second potential.
Input terminal, and transition between the third potential and the fourth potential
An output terminal for outputting an output signal, and a first power supply potential node
Between the input terminal and the output terminal.
Becomes non-conductive when the input signal is at a first potential.
And becomes conductive when the input signal is at the second potential.
A first transistor of a first conductivity type,
A second power supply potential node connected to the input terminal;
Conductive when the input signal input to the first input terminal is at the first potential.
In the non-conductive state when the input signal is at the second potential.
A second transistor of a second conductivity type that is in the active state;
Terminal, and the output signal is changed from a fourth potential to a third potential.
Passes a predetermined threshold potential when transitioning to a potential
Then, a first logic signal is generated and output, and the output signal is output.
When the signal transitions from the third potential to the fourth potential,
When the threshold voltage of the second logic signal is passed,
And a logic signal generation unit for generating and outputting. Sa
In addition, the first power supply potential node or the output terminal
Connected and the input signal input to the input terminal is
At a potential of 1, the transistor is turned off and the input signal
The third transistor of the first conductivity type which becomes conductive at the potential of 2
A transistor , the third transistor, and the output terminal
Or connected between the first power supply potential node and
The second logic signal output from the logic signal generator is
Becomes more conductive, and is output from the logic signal generator.
The fourth logic signal is turned off by the first logic signal.
And a transistor. And the first and second
Resistance when the second, third and fourth transistors are in a conductive state.
Resistance value according to the delay time at the time of transition of the output signal.
Thus, the configuration is such that the desired value is set. Second invention
Are the first potential and the second potential in the semiconductor input circuit.
And an input terminal for inputting an input signal that transitions to
And an output terminal for outputting an output signal transitioning to the fourth potential
Connected between a first power supply potential node and the output terminal
And the input signal input to the input terminal is a first input signal.
Becomes non-conductive at the time of the potential, and the input signal
A first transformer of the first conductivity type, which becomes conductive when at the potential
Between the output terminal and the second power supply potential node
And the input signal input to the input terminal is
It becomes conductive at the first potential, and the input signal
2 of the second conductivity type which becomes non-conductive at the potential of 2
A transistor connected to the output terminal;
When the signal transitions from the fourth potential to the third potential,
When the signal passes the threshold potential, the first logic signal is generated.
The output signal is changed from the third potential to the fourth potential.
Pass through the specified threshold potential when transitioning to
Then, a logic signal generator that generates and outputs the second logic signal
And a part. Further, the second power supply potential node
Connected to the input terminal or the input terminal.
Becomes conductive when the input signal is at a first potential.
Becomes non-conductive when the input signal is at the second potential.
A third transistor of the second conductivity type, and the third transistor
A transistor and the output terminal or the second power supply potential node;
Connected to the logic signal generator and output from the logic signal generator.
The first logic signal is turned on by the
From the second logical signal output from the logical signal generating unit
A fourth transistor that is turned off.
You. And the first, second, third and fourth transistors.
The resistance value when the star is in the conductive state is determined by the transition of the output signal.
Configuration to set a desired value according to the delay time at the time
I have to. The third invention is a half of the first or second invention.
In a conductor input circuit, first, second and third transistors
The star is a field effect transistor (eg, a MOS transistor).
And the fourth transistor is a field-effect transistor.
Transistors (eg, MOS transistors) or
It is composed of polar transistors.

[0006]

According to the first and third aspects, the input signal is the second signal.
Potential (for example, “L” level) to a first potential (for example,
(“H” level), the first and third traffic
Transistor is non-conductive, the second transistor is conductive
From the output terminal to the second transistor through the second transistor.
Current flows to the power supply potential node of
Potential (for example, “H” level) to a fourth potential (for example,
(For example, “L” level). The output signal changes
When the voltage falls below the threshold potential of the logic signal generator,
A second logic signal is output from the logic signal generation unit,
The transistor 4 becomes conductive. Therefore, the output signal
From the third potential when the second transistor is conducting
After a delay time determined by the resistance value of
Move. When the input signal is at the first potential (eg, “H” level)
) To a second potential (for example, “L” level)
Then, the first and third transistors are turned on, and the second
The transistor becomes non-conductive. At this time, the fourth tiger
Since the transistor is in a conductive state, the first power supply potential
From the node, the path of the first transistor, the third and
Current to the output terminal through the path of the transistor 4
Flow, the output signal is at a fourth potential (eg, "L" level)
To a third potential (for example, “H” level)
Good. The output signal changes and the threshold of the logic signal generator
When the potential exceeds the first potential, the first logic
Signal is output and the fourth transistor is turned off.
Accordingly, the paths of the third and fourth transistors are cut off.
Therefore, the output signal changes from the fourth potential to the first transistor.
Resistance value and third and fourth transistors when the star is conducting
The resistance in parallel with the resistance when the
After a complete delay time, a transition is made to the third potential. 2nd and 2nd
According to the third aspect, the input signal is set to the first potential (for example,
From the “H” level to the second potential (eg, “L” level)
When changes Le), the second and third tiger Njisuta is non
Conduction state, the first transistor becomes conductive, and the first transistor
Output terminal from power supply potential node through first transistor
Current flows to the element, and the potential of the output signal becomes the fourth potential (for example,
For example, from the “L” level to the third potential (eg, the “H” level).
Bell). The output signal changes and the logic signal is
When the threshold voltage of the component is exceeded, this logic signal
The first logic signal is output from the component and the fourth transistor
Is turned on. Therefore, the output signal has the fourth potential
From the resistance value of the first transistor in the conductive state.
After a delay time determined by the above, the potential changes to the third potential. Input signal
Signal from the second potential (for example, “L” level) to the first potential.
(For example, “H” level), the second and
The third transistor is conductive, and the first transistor is non-conductive.
It becomes conductive. At this time, the fourth transistor is conductive.
The second transistor from the output terminal.
Through the path of the third transistor and the path of the third and fourth transistors.
Then, a current flows to the second power supply potential node, and the output signal
From a third potential (for example, “H” level) to a fourth potential
(For example, “L” level). Output signal
To fall below the threshold potential of the logic signal generator.
Then, the second logic signal is output from the logic signal generation unit.
And the fourth transistor is turned off, and the third and third transistors are turned off.
The path of the fourth transistor is cut off. Therefore, output
The signal is output from the third potential by turning on the second transistor.
Value and the conduction state of the third and fourth transistors in the active state
Delay time determined by the parallel combined resistance value with the resistance value at the time
Later, the potential changes to the fourth potential.

[0007]

EXAMPLES (First Embodiment) FIG. 1 is a circuit diagram showing a semiconductor input circuit of the first embodiment of the present invention. This semiconductor input circuit has a first power supply potential Vdd and a second power supply potential Vss, as in the prior art FIG.
TTL level input signal applied to the input terminal In ₂ is converted to a MOS level, and the output terminal Out 2
Input circuit supplied from ₂ to the semiconductor integrated device. FIG.
The semiconductor input circuit of FIG.
Based on the potential level of the input signal applied to each gate from n ₂ , PMOS 11 as the first transistor and NMOS as the second transistor are turned on, respectively.
12 are provided. The source of the PMOS11 is connected to the first power supply potential Vdd, the drain of the PMOS11 is connected to the output terminal Out ₂ via the node N2. The source of the NMOS 12 is connected to the second power supply potential Vss.
, And the drain of the NMOS 12 is connected to the drain of the PMOS 11 at the node N2. Furthermore, this semiconductor input circuit is provided with a conducting means 20 which conducts being controlled by the potential level of the input signal and the first power supply potential Vdd between the output terminal Out _2. Conducting means 20
Is a third transistor connected in series to the first power supply potential Vdd and between the output terminal Out ₂ PMOS 21
A and fourth a transistor PMOS 22, an inverter 23 for inverting the potential of the output terminal Out _2, and an inverter 24 for inverting the output of the inverter 23, and. The gate of the PMOS 21 is connected to the input terminal In _2, and the source of the PMOS 21 is connected to the first power supply potential Vdd. The drain of the PMOS 21 is connected to the source of the PMOS 22. PMOS
The drain 22 is connected to the output terminal Out _2, PM
OS22, the system is in the configuration that is controlled by the output potential of the inverter 24 is input to the gate. That is, the two inverters 23 and 24 are a logic signal generation unit that generates a control logic signal from the output signal of the semiconductor input circuit, and the PMOS 22 is configured to be in a conductive state based on the control logic signal. Tei Ru.

Next, the operation of the semiconductor input circuit of FIG. 1 will be described. The semiconductor input circuit of FIG. 1 has a second power supply potential Vss.
And the first power supply potential Vdd is set to, for example, 5 volts, which is higher than the ground potential. In this state, when the ground potential, that is, the “L” level is applied to the input terminal In ₂ , the PMOS 11 is turned on and the NMOS 12 is cut off. As a result, from the output terminal Out _2, the first power supply potential Vdd
"H" level of the same potential as is output. In response to this, the output of the inverter 23 goes low and the output of the inverter 24 goes high.
2 is in a cutoff state. When the input potential at the terminal In ₂ changes to "H" level from the "L" level, the threshold potential of the semiconductor input circuit, P MOS 11 及
And the resistance ratio when the NMOS 12 is conducting. for that reason,
For example, the “H” level is 2 volts, and the “L” level is 0.2 volt.
8 volts to configure the interface with TTL-level input signal is, P MOS 11 and NMOS12
May be set to 2.5: 1 during conduction. When the TTL level “H” level is applied to the input terminal In ₂ , the potential of the output terminal Out ₂ becomes the PMOS 11 and NM
It is at the “L” level determined by the resistance ratio when the OS 12 is conducting. At this time, the output of the inverter 23 becomes “H” level, the output of the inverter 24 becomes “L” level,
The OS 22 is turned on. PMOS22 even conductive state, since the gate of the PMOS 21 is the "H" level is applied, PMOS 21 is cut off walk is in the high resistance state. When the TTL level input signal applied to the input terminal In ₂ changes from “H” level to “L” level, the NMOS 12 is cut off, and the PMOS 11 and the PMOS 21 are turned on.
Further, at the time of this change, since the PMOS 22 is also in the conductive state, the potential of the output terminal Out ₂ becomes the PMOS 11,
The signal is set to “H” level by the PMOS 21 and the PMOS 22 and output.

Next, the delay time will be described. TTL
When the input signal of the level changes from the "L" level to the "H" level, that is, when the output signal falls, the delay time is determined by the resistance value of the NMOS 12 when it is conductive, and is the same as that of the conventional semiconductor input circuit. This is the delay time. On the other hand, when the TTL level input signal changes from “H” level to “L” level, which has been a problem in the past,
At the time of the rise of the output signal, until the potential of the output terminal Out ₂ exceeds the threshold potential of the inverter 23, P
The MOS 22 is conducting and the PMOS 21 is also conducting. At this time, the conduction resistance value of the PMOS that determines the delay time is not only the PMOS 11 but also the PMOSs 21 and 22.
Becomes Therefore, the rise delay time of the output signal in the semiconductor input circuit of FIG. 1 is reduced by reducing the conduction resistance of the PMOSs 21 and 22. As described above, in the present embodiment, the first signal is controlled by the level of the input signal.
A conduction means 20 for conducting between the power supply potential Vdd and the output terminal Out ₂ is provided in a conventional semiconductor input circuit. Therefore, for example, even if an interface is configured for a TTL level input signal having an “H” level of 2 volts and an “L” level of 0.8 volts, a balance is provided for the rise and fall delays of the output signal. A good semiconductor input circuit can be formed.

( Second Embodiment ) FIG. 4 is a circuit diagram showing a semiconductor input circuit according to a second embodiment of the present invention. This semiconductor input circuit operates based on the voltage between the first power supply potential Vdd and the second power supply potential Vss, as in the first embodiment of FIG. 1, and operates at the TTL level applied to the input terminal In _3. an input circuit for supplying to the semiconductor integrated device from varying <br/> conversion to the output terminal Out ₃ the input signal to the MOS level. As in FIG. 1, the semiconductor input circuit of FIG. 4 has a PMOS transistor 11 of a first transistor and a PMOS transistor 11 of a second transistor, each of which is controlled to be conductive based on the potential level of an input signal applied to each gate from an input terminal In ₃ . N
MOS 12. The source of PMOS 11 is
The PMOS 11 is connected to the first power supply potential Vdd, and the drain of the PMOS 11 is connected to the output terminal Out ₃ via the node N2. The source of the NMOS 12 is connected to the second power supply potential V
ss, and the drain of the NMOS 12 is connected to the node N
2 is connected to the drain of the PMOS 11. Further, in this semiconductor input circuit , the first power supply potential Vdd and the output terminal Ou are controlled by the potential level of the input signal.
A conducting means 30 for conducting between t ₃ is provided. Conducting means 30 is a third transistor connected in series between the first power supply potential Vdd and the output terminal Out ₃ PMOS
An NPN transistor 32 as a fourth transistor and a fourth transistor, and an inverter 33 for inverting the potential of the output terminal Out ₃ are provided. The gate of the PMOS 31 whose drain is connected to the output terminal Out ₃ is connected to the input terminal In _3.
The source of the PMOS 31 is connected to the emitter of the NPN transistor 32. The collector of the NPN transistor 32 is connected to the first power supply potential Vdd.
Is connected to, NPN type transistor 32, the system is in the configuration that is controlled by the output potential of the inverter 33 is input to the base. That is, the inverter 33 is a logic signal generation unit that generates a control logic signal from the output signal of the semiconductor input circuit, and the NPN transistor 32 has a configuration in which conduction is controlled based on the control logic signal.
Tei Ru.

Next, the operation of the semiconductor input circuit of FIG. 4 will be described. The semiconductor input circuit of FIG. 4 has the second power supply potential Vss.
And the first power supply potential Vdd is set to, for example, 5 volts, which is higher than the ground potential. In this state, when the ground potential, that is, the “L” level is applied to the input terminal In ₃ , the PMOS 11 is turned on and the NMOS 12 is cut off. As a result, from the output terminal Out _3, the first power supply potential Vdd
"H" level of the same potential as is output. In response to this, the output of the inverter 33 becomes "L" level, NP
N-type transistor 32 is cut off. When the input potential at the terminal In ₃ changes to "H" level from the "L" level, the threshold potential of the semiconductor input circuit is determined by the resistance ratio at the time of conduction of P MOS 11 and NMOS 12. For example, in order to configure an interface with an input signal of a TTL level in which the “H” level is 2 volts and the “L” level is 0.8 volts , the PMOS 11 and the NMO
The resistance ratio at the time of conduction in S12 may be set to 2.5: 1. When the TTL level “H” level is applied to the input terminal In ₃ , the potential of the output terminal Out ₃ becomes
"L" determined by the resistance ratio of the NMOS 1 and the NMOS 12 when conducting.
Level. At this time, the output of the inverter 33 is
It goes to the “H” level, and the NPN transistor 32 is turned on. Even NPN type transistor 32 is conductive, because the gate of the PMOS 31 is the "H" level is applied, PMOS 31 is cut off walk is in the high resistance state. When the TTL level input signal applied to the input terminal In ₃ changes from “H” level to “L” level, the NMOS 12 is cut off, and the PMOS 11 and the PMOS 31 are turned on. In addition, in this change process, the NPN transistor 32 is also in a conductive state, so that the potential of the output terminal Out ₃ is set to “H” level by the PMOS 11, the PMOS 31, and the NPN transistor 32 and output.

Next, the delay time will be described. TTL
When the input signal of the level changes from the “L” level to the “H” level, that is, when the output signal falls, the delay time is determined by the resistance value of the NMOS 12 when the NMOS 12 is turned on. The same delay time results. On the other hand, when the input signal at the TTL level changes from the “H” level to the “L” level, which is a conventional problem, that is, when the output signal rises, the potential of the output terminal Out ₃ becomes the threshold of the inverter 33. to over voltage, NPN type transistor 32 is in conduction state, and PM
The OS 31 is also in a conductive state. At this time, the conduction resistance of the PMOS that determines the delay time is the conduction resistance of the PMOS 31 and the NPN transistor 32 in addition to the PMOS 11. Therefore, the rising delay time of the output signal in the semiconductor input circuit of FIG. 4, PMOS 31 and NPN
By lowering the resistance of the type transistor 32 when conducting,
Can be shortened. As described above, in the present embodiment, the conduction means 30 which is controlled by the level of the input signal and conducts the first power supply potential Vdd and the output terminal Out ₃ is connected to the conventional semiconductor input circuit using the NPN transistor 32. Is provided. As a result, as in the first embodiment, the resistance between the first power supply potential Vdd and the output terminal Out ₃ is lowered. Therefore, for example, even if an interface is configured for a TTL level input signal having an "H" level of 2 volts and an "L" level of 0.8 volts, the delay of the rising and falling of the output signal is balanced. A good semiconductor input circuit can be formed.

( Third Embodiment ) FIG. 5 is a circuit diagram showing a semiconductor input circuit according to a third embodiment of the present invention. The semiconductor input circuit of FIG.
1 and 4, the first power supply potential Vdd
And the second power supply potential Vss, and the input terminal In
TTL level input signal applied to ₄ is MOS level
This is an input circuit that converts the input signal into an output signal and supplies the output terminal Out ₄ to the semiconductor integrated device. This semiconductor input circuit
The delay time when falls, is used as an input circuit of a semiconductor device or the like need to be fast with respect to the delay time when standing up. The semiconductor input circuit of FIG. 5 has a PMOS transistor 11 and a second transistor 12 that are turned on based on the potential level of an input signal applied to each gate from the input terminal In ₄ , as in the conventional circuit of FIG. And an NMOS 12, which is a transistor of PMO
The source of S11 is connected to the first power supply potential Vdd,
The drain of the PMOS11 is connected to the output terminal Out ₄ through the node N2. The source of the NMOS 12 is connected to the second power supply potential Vss, and the drain of the NMOS 12 is connected to the drain of the PMOS 11 at the node N2. Further, in this semiconductor input circuit , the second power supply potential V is controlled by the potential level of the input signal.
The conducting means 40 for conduction between ss output terminal Out ₄ are provided. Conducting means 40, the third transient which are connected in series between the second power supply potential Vss and the output terminal Out ₄
NMOS 41 and a fourth transistor
And NMOS 42, an inverter 43 for inverting the potential of the output terminal Out _4, and an inverter 44 for inverting the output of the inverter 43, and. The gate of the NMOS 41 is connected to the input terminal In _4, and the source of the NMOS 41 is connected to the second power supply potential Vss. NMO
The drain of S41 is connected to the source of NMOS. The drain of the NMOS 42 is connected to the output terminal Out ₄
Is connected to, NMOS 42 is turned configured to be controlled by the output potential of the inverter 44 which is input to the gate
There Ru. That is, the two inverters 43 and 44 are a logic signal generation unit that generates a control logic signal from the output signal of the semiconductor input circuit, and the NMOS 42 is configured to be in a conductive state based on the control logic signal. Tei Ru.

Next, the operation of the semiconductor input circuit of FIG. 5 will be described. The semiconductor input circuit of FIG. 5 has the second power supply potential Vss.
And the first power supply potential Vdd is set to, for example, 5 volts, which is higher than the ground potential. Ground potential to the input terminal In ₄ in this state, i.e., if the "L" level is applied, similarly PMOS11 conductive state in the first embodiment of FIG. 1, NMOS 12 is cut off. As a result, the output terminal Out ₄ outputs the “H” level of the same potential as the first power supply potential Vdd.
Is output. In response to this, the output of the inverter 43 becomes "L" level, and the output of the inverter 44 becomes "H".
Level, and the NMOS 42 is turned on. On the other hand, since the input terminal In ₄ is at “L” level, the NMOS 4
1 is in a cutoff state. When the potential of the input terminal In ₄ changes from “L” level to “H” level, the threshold potential of this semiconductor input circuit is the PMOS 11
And the resistance ratio of the NMOS 12 during conduction. For example,
"H" level 2 volts, in order to "L" level constitutes the interface with TTL level input signal of 0.8 volts, the resistance ratio during conduction of P MOS 11 and NMOS 12 2.5: 1 Just set it.

[0015] the TTL level to the input terminal In ₄ "H" Les
If the bell is marked pressurized, the potential of the output terminal Out ₄ is, P
It is at the “L” level determined by the resistance ratio when the MOS 11 and the NMOS 12 are conducting. At this time, the output of the inverter 43 becomes " H" level, the output of the inverter 44 becomes "L" level, and the NMOS 42 is cut off. When the potential of the input terminal In ₄ changes from “L” level to “H” level, the NMOS 12 is turned on and
MOS 41 becomes conductive. At the time of this change, the NMOS 42 is also in the conductive state, so that the output terminal Out ₄
From "L" determined by NMOS12, 41, 42
The level is output. By reducing the resistance value of the NMOSs 41 and 42 at the time of conduction, the delay at the time of falling of the output signal can be reduced. That is, the interface level with respect to the TTL level input signal is the PMOS 11
And the resistance ratio when the NMOS 12 is conducting.
The delay time at the time of falling of the output is NMOS12,4.
It is determined by the resistance values of the transistors 1 and 42 when conducting. Therefore, it is possible to set the threshold voltage of the semiconductor input circuit, and a delay time of the delay time and fall time at the output of the rising, independently. In this embodiment, TTL
While maintaining the interface level for the level input signal, the delay time when the output falls is reduced.

( Fourth Embodiment ) FIG. 6 is a circuit diagram showing a semiconductor input circuit according to a fourth embodiment of the present invention. The semiconductor input circuit of FIG. 6 is connected between the first power supply potential Vdd and the second power supply potential Vss, similarly to FIGS . 1 , 4, and 5 of the first, second, and third embodiments.
TTL level input signal applied to input terminal In ₅
It is converted to MOS level which is the input circuit is supplied from the output terminal Out ₅ in the semiconductor integrated device. The semiconductor input circuit, a delay time when an output signal falls, is used as an input circuit of a semiconductor device or the like need to be fast with respect to the delay time when standing up. The semiconductor input circuit of FIG. 6, like the conventional 2, based from the input terminal In ₅ to the potential level of the input signal applied to the gates, PMOS 11 and a second of the first transistor serving as the respective conductive state And an NMOS 12 of a transistor. P
The source of MOS11 is connected to the first power supply potential Vdd, the drain of the PMOS11 is connected to the output terminal Out ₅ through the node N2. The source of the NMOS 12 is connected to the second power supply potential Vss.
Is connected to the drain of the PMOS 11 at the node N2. Furthermore, this semiconductor input circuit is provided with a conducting means 50 for conduction between the second power supply potential Vss and the output terminal Out ₅ is controlled by the potential level of the input signal. Conducting means 50, the third Trang connected in series between the second power supply potential Vss and the output terminal Out ₅
An NPN type transistor 52 is NMOS51 and fourth transistors is a register, an inverter 53 for inverting the potential of the output terminal Out _5, and an inverter 54 for inverting the output of the inverter 53, and. NM
The gate of the OS 51 is connected to the input terminal In _5.
The source of the MOS 51 is connected to the second power supply potential Vss. The drain of the NMOS 51 is connected to the emitter of the NPN transistor 52. The collector of the NPN transistor 52 is connected to the output terminal Out _5, NPN type transistor 52, configured to be controlled by the output potential of the inverter 54 input to the base
Ttei Ru. That is, the two inverters 53 and 54 are a logic signal generation unit that generates a control logic signal from the output signal of the semiconductor input circuit, and the NPN transistor 52 is turned on based on the control logic signal. configuration I to
Ttei Ru.

Next, the operation of the semiconductor input circuit of FIG. 6 will be described. The semiconductor input circuit of FIG. 6 has a second power supply potential Vss.
And the first power supply potential Vdd is set to, for example, 5 volts, which is higher than the ground potential. In this state, when the ground potential, that is, the “L” level is applied to the input terminal In ₅ , the PMOS 11 is turned on and the NMOS 12 is cut off as in the first embodiment of FIG. As a result, the output terminal Out ₅
From, "H" level of the same potential as the first power supply potential Vdd is output. In response, the output of inverter 53 goes to "L" level and the output of inverter 54 goes to "H" level, and NPN transistor 52 is turned on. On the other hand, since the input terminal In ₅ is at the “ L” level, the NMOS 51 is cut off. Input terminal I
when the potential of the n ₅ is changed to the "H" level from the "L" level, the threshold potential of the semiconductor input circuit,
Determined by the resistance ratio at the time of conduction of P MOS 11 and NMOS 12. For example, to configure an interface with a TTL level input signal having an “H” level of 2 volts and an “L” level of 0.8 volts , the PMOS 11 and NMOS 1
The resistance ratio at the time of conduction of 2 may be set to 2.5: 1. When the TTL level “H” level is applied to the input terminal In ₅ , the potential of the output terminal Out ₅ is
It is at the “L” level determined by the resistance ratio when the MOS 12 is conducting. At this time, the output of the inverter 53 becomes “H” level, the output of the inverter 54 becomes “L” level, and NP
N-type transistor 52 is cut off.

When the potential of the input terminal In ₅ changes from “L” level to “H” level, the NMOS 12 is turned on and the NMOS 51 is turned on. Also,
At the time of this change, the NPN transistor 52 is also in a conductive state, so that the output terminals Out ₅ output the NMOSs 12 and _5.
1 and the “L” level determined by the NPN transistor 52 are output. By reducing the resistance value of the NMOS 51 and the NPN transistor 52 when conducting, the delay at the time of falling of the output signal can be reduced. That is, the interface level with respect to the TTL level input signal is set by the resistance ratio when the PMOS 11 and the NMOS 12 are turned on, but the delay time when the output falls is determined by the NMOS 12, 51 and the NPN transistor 52.
Is determined by the resistance value during conduction. Therefore, it is possible to set the threshold voltage of the semiconductor input circuit, and a delay time of the delay time and fall time when the falling of the output is Ri, independently. In the present embodiment, the delay time when the output falls is reduced while maintaining the interface level for the TTL level input signal.

It should be noted that the present invention is not limited to the above embodiment, and various modifications are possible. For example, there are the following modifications. (1) Even when the PMOS 11 and the NMOS 12, which are the first and second transistors used in the first to fourth embodiments, are constituted by bipolar transistors, the same operation as in the first to fourth embodiments is performed at high speed. A semiconductor input circuit having an effect can be configured. (2) The fourth transistor used in the second and fourth embodiments
The NPN transistors 32 and 52, which are the transistors,
A P-type transistor may be used. In such a case, if the wirings of the emitter and the collector are reversed, the operation is the same as in the second and fourth embodiments. (3) Each of the logic signal generators 20, 30, 40, and 50 used in the first to fourth embodiments may generate a logic signal according to the level of an output signal, and is not limited to an inverter.

[0020]

As described above in detail, according to the first aspect, the conductive state / non-conductive state depends on the potential of the input signal.
Output from the third transistor and the logic signal generator
State / non-conduction state by the first and second logic signals
Connected in series with the fourth transistor
The column circuit is connected in parallel with the first transistor
In, for example, when configuring the interface to TTL level input signal, only when the first transistor is in a conductive state, to the configuration to reduce the resistance value between the output terminal a first power supply potential node. Therefore, for example, while fixing the threshold potential of the semiconductor input circuit, it becomes possible to shorten the on the rising edge of the delay time of the output signal, good fast of equal balance of rise delay time and the fall delay time of the output signal It is possible to realize a semiconductor input circuit. Furthermore, Ru possible der to set the interface level, the delay time of the rising and falling of the output signal independently. According to the second invention, the first
The third and fourth transistors are substantially the same as those of
Connected in parallel with the second transistor.
Therefore, for example, for a TTL level input signal,
When configuring the interface, the second transistor
Only during the conduction state, the second power supply potential node is connected to the output terminal.
The resistance value between them can be reduced. So, for example,
With the threshold potential of the semiconductor input circuit fixed,
Possible to reduce the delay time of output signal fall
become. Further, similarly to the first invention, the interface
Level, delay of rise and fall of output signal
It is also possible to set the time independently. Therefore, for example, after having an appropriate interface level for a TTL level input signal, an input circuit having a short delay time when the output signal falls can be configured, and a high-speed input circuit corresponding to an edge trigger signal can be configured. Can be realized. According to the third invention, the first or second invention
The first, second and third transistors of the
And the fourth transistor is constituted by a field-effect transistor or a bipolar transistor , so that the semiconductor input circuit has a circuit configuration suitable for a semiconductor integrated circuit.
After realizing the circuit and ensuring high-speed operation,
A semiconductor input circuit having a small circuit scale can be provided .

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a semiconductor input circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a conventional semiconductor input circuit.

FIG. 3 is a diagram showing input / output characteristics of FIG. 2;

FIG. 4 is a circuit diagram showing a semiconductor input circuit according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a semiconductor input circuit according to a third embodiment of the present invention.

FIG. 6 is a circuit diagram showing a semiconductor input circuit according to a fourth embodiment of the present invention.

[Explanation of symbols]

1, 11, 21, 22, 31 PMOS 2, 12, 41, 42, 51 NMOS 20, 30, 40, 50 Conducting means 23, 24, 33, 43, 44, 53, 54 Inverter 32, 52 NPN transistor Vdd , Vss First and second power supply potentials In _{1 to} In ₅ input terminals Out _{1 to} Out ₅ output terminals

Claims (3)

(57) [Claims] 1. An input for transitioning between a first potential and a second potential.
An input terminal for inputting a signal; and an output signal which transitions to a third potential and a fourth potential.
An output terminal connected between a first power supply potential node and the output terminal;
And the input signal input to the input terminal is a first power supply.
The input signal is in the non-conductive state when the
A first transistor of a first conductivity type, which becomes conductive when
Connection is between the static, and the output terminal and a second power supply potential node
And the input signal input to the input terminal is a first power supply.
When the input signal is at the second potential,
A second transistor of the second conductivity type, which becomes non-conductive when
And the output terminal is connected to the output terminal and the output signal is a fourth potential.
Pass a predetermined threshold potential when transitioning from the third potential to the third potential
Then, a first logic signal is generated and output, and the output signal
When the signal transits from the third potential to the fourth potential,
Generates and outputs a second logic signal when it passes the threshold potential
It is connected to the logic signal generation unit, to the first power supply potential node or the output terminal
And the input signal input to the input terminal is a first power supply.
The input signal is in the non-conductive state when the
A third transistor of the first conductivity type, which becomes conductive when
And the third transistor and the output terminal or the first transistor.
Between the power supply potential node and the logic signal generation
Into a conductive state by the second logic signal output from the section
And the first theory output from the logic signal generator.
And a fourth transistor which is turned off by a logical signal.
A conductive state of the first, second, third and fourth transistors.
Resistance in the active state, the delay at the transition of the output signal.
That the desired value is set according to the delay time
Characteristic semiconductor input circuit. 2. An input for transitioning between a first potential and a second potential.
An input terminal for inputting a signal; and an output signal which transitions to a third potential and a fourth potential.
An output terminal connected between a first power supply potential node and the output terminal;
And the input signal input to the input terminal is a first power supply.
The input signal is in the non-conductive state when the
A first transistor of a first conductivity type, which becomes conductive when
Connection is between the static, and the output terminal and a second power supply potential node
And the input signal input to the input terminal is a first power supply.
When the input signal is at the second potential,
A second transistor of the second conductivity type, which becomes non-conductive when
And the output terminal is connected to the output terminal and the output signal is a fourth potential.
Pass a predetermined threshold potential when transitioning from the third potential to the third potential
Then, a first logic signal is generated and output, and the output signal
When the signal transits from the third potential to the fourth potential,
Generates and outputs a second logic signal when it passes the threshold potential
It is connected to the logic signal generation unit, to the second power supply potential node or the output terminal
And the input signal input to the input terminal is a first power supply.
When the input signal is at the second potential,
The third transistor of the second conductivity type, which becomes non-conductive at the time of
And the third transistor and the output terminal or the second transistor.
Between the power supply potential node and the logic signal generation
Into a conductive state by the first logic signal output from the section
And the second theory output from the logic signal generation unit.
And a fourth transistor which is turned off by a logical signal.
A conductive state of the first, second, third and fourth transistors.
Resistance in the active state, the delay at the transition of the output signal.
That the desired value is set according to the delay time
Characteristic semiconductor input circuit. 3. The first, second and third transistors comprise:
A fourth transistor composed of a field-effect transistor
Is a field-effect transistor or bipolar transistor
3. The method according to claim 1, wherein the first and second parts are constituted by
Semiconductor input circuit.