JP3269727B2 - Solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a charge coupled device (CC).
The present invention relates to a solid-state imaging device using D), and more particularly to an improvement in a parallel-serial conversion unit that transfers signal charges from a plurality of vertical transfer channels to a horizontal transfer channel of the solid-state imaging device.

[0002]

2. Description of the Related Art An example of a conventional solid-state imaging device will be described with reference to FIG. FIG. 1 schematically illustrates an example of a solid-state imaging device using an interline transfer CCD, in which a plurality of photosensitive units 101 are arranged in a matrix. Photosensitive section 10
Reference numeral 1 denotes a photodiode which accumulates signal charges corresponding to the pixels of the received light image. A plurality of vertical transfer units 103 formed by CCDs along each row of the photosensitive units 101
Are arranged. The signal charges of the photosensitive unit 101 are transferred to the adjacent vertical transfer unit 103 via the transfer gate 102 during the vertical blanking period of the video signal. Each signal charge travels down one pixel at a time in the vertical transfer section 103 during the horizontal retrace period, and the horizontal transfer section 10 formed by the CCD.
Reach 4 The horizontal transfer unit 104 supplies signal charges corresponding to one horizontal scan, which are simultaneously transferred from the plurality of vertical transfer units 103, to the amplifier 105 in series, and causes the amplifier 105 to output a video signal corresponding to the signal charge.

FIG. 4 partially shows a portion for transferring signal charges from the plurality of vertical transfer units 103 to the horizontal transfer unit 104 and performing parallel-serial conversion of the signal charges. In the figure, a plurality of columns of vertical transfer channels 5 formed by epitaxial growth or buried channels on a silicon substrate, and vertical transfer electrodes 1 and 2 repeatedly arranged in the column direction so as to intersect with the vertical transfer channels 5.
This forms a vertical transfer unit 103. The vertical transfer electrode 2 is a first layer electrode. The vertical transfer electrode 1 is a second layer electrode, and a part of both ends in the column direction overlaps with both ends of the vertical transfer electrode 2.

[0004] The lower end of the vertical transfer channel 5 is connected to a horizontal transfer channel 6 formed in the row direction by epitaxial growth or a buried channel at the bottom of the figure. A higher bias electric field is applied to the horizontal transfer channel 6 than to the vertical transfer channel 5, and signal charges flow from the vertical transfer channel 5 to the horizontal transfer channel 6.
A comb-shaped horizontal storage electrode 3 is arranged along the horizontal transfer channel 6 between the horizontal transfer channel 6 and the final vertical transfer electrode 1n. The horizontal storage electrode 3 has a plurality of comb-shaped portions each extending from the vertical transfer channel 5 and temporarily stores a signal charge group transmitted from the vertical transfer channel 5 below the final vertical transfer electrode 1n. In order to transfer the signal charges stored in the horizontal storage electrodes 3 in the row direction, a first-layer horizontal transfer electrode 8 and a second-layer horizontal transfer electrode 7 are arranged repeatedly in the row direction. Further, a comb-shaped horizontal barrier electrode 4 is provided in order to suppress undesired diffusion of signal charges. The comb-shaped portion of the horizontal barrier electrode 4 is between the final vertical transfer electrode 1n and the horizontal storage electrode 3, and the tooth portion of the horizontal barrier electrode 4 is the tooth portion of the comb-shaped horizontal storage electrode 3 and the horizontal transfer electrode 7. And placed between. As described above, the horizontal storage electrode 3, the horizontal barrier electrode 4, the horizontal transfer channel 6,
The second layer horizontal transfer electrode 7 and the first layer horizontal transfer electrode 8
It corresponds to the horizontal transfer unit 104.

The operation of the solid-state imaging device will be described with reference to FIGS. FIG. 7 shows the drive voltage applied to each transfer electrode, and 4 is applied to the vertical electrodes 1 and 2.
Phase vertical drive clocks V1 to V4 are applied, respectively. A horizontal drive clock H1 is applied to the horizontal storage electrode 3 and the horizontal barrier electrode 4. A horizontal drive clock H2 is applied to the horizontal transfer electrodes 7 and 8. The horizontal drive clocks H1 and H2 are two-phase drive clocks.

FIG. 8 shows signal waveforms of the respective drive clocks. For example, the "H" level of the four-phase vertical drive clocks V1 to V4 is 0 to 12V, and the "L" level is -6 to -8.
V. The two-phase horizontal drive clocks H1 and H2 are:
"H" level is 3-5V, "L" level is 0 ± 0.5V
It is.

FIG. 9 schematically shows the movement of the signal charge at the timings t1 to t10 of the driving clock shown in FIG. 8 along the transfer channel I-II-III in FIG. The potential of the transfer channel is controlled by the vertical drive clocks V1 to V4, and the signal charges transferred from the photosensitive unit 101 to the vertical transfer channel 5 are sequentially moved toward the horizontal storage electrodes 3 (t1 to t4). By controlling the applied voltage H1 of the horizontal barrier electrode 4 and the horizontal storage electrode 3 to H level, signal charges are transferred from the vertical transfer channel under the final vertical transfer electrode 1n to which the drive clock V4 is applied to the horizontal storage electrode 3 below. Capture (t4 to t9). Next, the horizontal drive clock H1 applied to the horizontal storage electrode 3 and the horizontal barrier electrode 4 and the horizontal drive clock H2 applied to the horizontal transfer electrode 7 and the horizontal transfer electrode 8 are controlled in a complementary manner. The signal charge taken into the transfer channel is moved toward the amplifier 105. The operation of the CCD forming the vertical transfer channel and the horizontal transfer channel described above is a known operation, and is not a main part of the present invention, and will not be described in further detail.

[0008]

In a parallel-serial conversion section for transferring signal charges from a vertical transfer section to a horizontal transfer section, in a conventional configuration, as shown in FIG. It is formed narrower than the width B of the electrode 3, and has a shape in which the channel width A is enlarged below the comb-like portion of the horizontal storage electrode 3. Therefore, even if the horizontal storage electrode 3 and the vertical transfer channel 5 are slightly displaced from each other, the vertical transfer channel 5 falls within the lower part of the comb-like portion of the horizontal storage electrode 3. As a result, when a shift occurs in the pattern alignment between the vertical transfer channel 5 and the horizontal storage electrode 3, the vertical transfer channel 5 protrudes from below the horizontal storage electrode 3 to transfer the signal charge under the horizontal storage electrode 3. It is possible to prevent the width of the channel from becoming narrower, so that a barrier due to a so-called narrow channel is generated, a transfer failure is generated, and vertical streaks are generated on a reproduced screen.

However, increasing the number of pixels of the solid-state imaging device,
With the miniaturization, the patterns of the vertical transfer channel 5 and the horizontal transfer channel 6 are both miniaturized. When the size is reduced, the width A of the vertical transfer channel cannot be made smaller than the width B of the electrode of the horizontal storage electrode 3 as shown in FIG. This is shown in FIG. 5, parts corresponding to those in FIG. 4 are denoted by the same reference numerals, and description of such parts will be omitted.

In the above-mentioned parallel-serial converter, as shown in FIG. 5, the width A of the vertical transfer channel 5 and the width B of the horizontal storage electrode 3 must be substantially the same. In this case, as shown in FIG. 6, if a misalignment occurs in the alignment of the two patterns, a barrier is generated due to the above-described narrow channel in the portion of FIG. Brings noise that appears as streaks.

Therefore, according to the present invention, even if the circuit pattern is miniaturized, the transfer capacity of the signal charge of the channel is ensured,
It is another object of the present invention to provide a solid-state imaging device that does not generate vertical streaks.

It is another object of the present invention to provide a parallel-to-serial converter device which secures a transfer capacity for signal charges in a channel and does not generate vertical stripes even if a circuit pattern is miniaturized. I do.

[0013]

In order to achieve the above object, a solid-state imaging device according to the present invention comprises a plurality of photoelectric conversion elements formed on a semiconductor substrate in a matrix and generating signal charges corresponding to the amount of received light. And a plurality of signal charges stored in the photoelectric conversion elements of each column are taken into a vertical transfer channel formed along each column of the photoelectric conversion elements, and the plurality of signal charges are transferred in the column direction. A vertical transfer unit and a plurality of signal charges corresponding to one horizontal scan output in parallel from each vertical transfer channel of the plurality of vertical transfer units are temporarily held in a horizontal storage electrode extending across the vertical transfer channels, and each held charge is held. A horizontal transfer section that takes in signal charges in a horizontal transfer channel formed in a row direction and transfers each signal charge in series; and a horizontal transfer channel from a region where the vertical transfer channel and the horizontal storage electrode overlap. To And an impurity diffusion layer having a shape extending from the vertical transfer channel to the horizontal transfer channel and formed from the vertical transfer channel to the horizontal transfer channel. .

Further, the parallel-serial converter of the present invention comprises a plurality of vertical transfer channels formed on a semiconductor substrate in a column direction for transferring signal charges in the column direction, and a plurality of vertical transfer channels for each of the plurality of vertical transfer channels. A plurality of signal charges output in parallel are temporarily held in a horizontal storage electrode straddling the vertical transfer channel, and each held signal charge is taken into a horizontal transfer channel formed in a row direction, and each signal charge is taken out. A horizontal transfer unit that transfers serially, a shape in which the width of the vertical transfer channel and the horizontal storage electrode overlaps toward the horizontal transfer channel from the overlapping area and extends from the vertical transfer channel to the horizontal transfer channel. And an impurity diffusion layer formed from the vertical transfer channel to the horizontal transfer channel.

[0015]

According to the present invention, a concentration gradient is formed in a region under the horizontal storage electrode where charges are transferred from the vertical transfer channel to the horizontal transfer channel so that the concentration increases from the vertical transfer channel to the horizontal transfer channel. Since an additional layer is formed to form a region for guiding signal charges, even if there is a slight misalignment between the horizontal storage electrode and the vertical transfer channel, no barrier that prevents the flow of signal charges does not occur. ,
The signal charges are smoothly transferred to the horizontal transfer channel. As a result, the transfer capacity of each vertical transfer channel can be ensured, and it is possible to prevent a video signal formation defect that causes vertical stripes on the screen.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. In FIG. 1, portions corresponding to those in FIG. 4 are denoted by the same reference numerals, and description of such portions will be omitted.

In this embodiment, a solid-state image pickup device is formed in the same manner as in the conventional structure. However, a region below the comb-shaped horizontal storage electrode 3 where the transfer from the vertical transfer channel 5 to the horizontal transfer channel 6 is performed is shown in FIG. An n-type impurity diffusion layer 10 is additionally formed as shown in FIG.

That is, as shown in FIG. 2, n-type impurity diffusion is performed by ion implantation into a p-type silicon substrate,
Alternatively, a buried channel is formed by epitaxial growth, and a plurality of vertical transfer channels 5 and horizontal transfer channels 6 are formed. The impurity concentration of the buried channel is, for example,
It is formed to have a ^{thickness of} about 0.5 to 10 × 10 ¹⁷ / cm ⁻³ . Further, an electrode portion (a portion corresponding to a comb-shaped pattern) extending in the row direction of the comb-shaped horizontal storage electrode 3 indicated by an imaginary line in FIG.
In the region 3a where the vertical transfer channel 5 overlaps with the horizontal transfer channel 6 from the approximate center of the width of the vertical transfer channel 5.
The width is gradually increased from the region 3a as shown in the drawing to the region 3b where the horizontal storage electrode 3 and the horizontal transfer channel 6 intersect with each other. Layer 10 is formed. The impurities used for forming the added impurity diffusion layer 10 include:
For example, phosphorus P, arsenic As, or the like can be used. The impurity concentration is, for example, about 0.5 to 5 × 10 ¹⁶ / cm ⁻³ .

The reason why the impurity diffusion layer 10 is formed so as to increase in width from the center of the width of the vertical transfer channel 5 toward the horizontal transfer channel 6 is that when ion implantation is performed using the mask of the impurity diffusion layer 10, In the portion of the narrow region 3a, the impurity concentration becomes relatively low due to the diffusion of the n-type impurity to the periphery. In the part of the wide region 3b, n
Since the diffusion of the type impurity is small, the impurity concentration becomes relatively high. Therefore, a gradient of the impurity concentration from the region 3a to the region 3b is formed. An energy gradient is formed along this gradient. As described above, the energy order of the horizontal transfer channel 6 is set higher than that of the vertical transfer channel 5 by the bias voltage, so that the impurity diffusion layer 10 has a smooth signal path from the vertical transfer channel 5 to the horizontal transfer channel 6. A potential gradient is forcibly formed to promote the passage of signal charges. Such a signal charge by the impurity diffusion layer 10 is guided toward the horizontal transfer channel 6 to promote the passage (flow) of the signal charge and to increase the signal charge passing capacity. Even if a narrow channel is generated, it is possible to prevent a barrier from being generated at this portion and preventing the passage of signal charges.
Other configurations are the same as those of the solid-state imaging device shown in FIG. 4 or FIG. 5, and description thereof will be omitted. The control of each electrode of the vertical transfer channel and the horizontal transfer channel by the CCD is the same as that of the conventional configuration. Known one-phase drive, two-phase drive, three-phase drive, four-phase drive, and the like can be applied to drive the CCD.

As the pattern of the impurity diffusion layer 10, in addition to the pattern that expands stepwise as in the embodiment, it is possible to apply various shapes such as a fan shape, a ginkgo leaf shape, and the like, which spread out at the end. Although the impurity diffusion layer 10 uses an n-type impurity in the embodiment, the polarity is determined to be the same as the impurity of the buried layer. For example, if the silicon substrate is n
If the buried channel is p-type, a p-type impurity can be used. Although the above embodiment is an example in which the present invention is applied to a so-called interline transfer type solid-state imaging device, the present invention can also be applied to a so-called frame transfer type solid-state imaging device. Further, the present invention is applicable to a parallel-serial conversion unit of a device using a CCD. For example, it is possible to additionally form the impurity diffusion layer 10 in the parallel-serial conversion unit of the CCD memory to secure the capacity of the vertical transfer channel and prevent the generation of noise.

[0021]

As described above, in the solid-state imaging device and the parallel-serial conversion device according to the present invention, the vertical portion is provided below the horizontal storage electrode in the region where the charge is transferred from the vertical transfer channel to the horizontal transfer channel. An impurity diffusion layer having a concentration gradient formed so as to increase the concentration from the transfer channel to the horizontal transfer channel is additionally formed to form a region for guiding signal charges, so that a slight misalignment occurs. However, no barrier is generated that hinders the flow of the signal charges, and the signal charges are smoothly transferred to the horizontal transfer channel.
Therefore, the transfer capacity of each vertical transfer channel can be secured,
This makes it possible to prevent a video signal from being poorly formed on the screen as a vertical stripe.

[Brief description of the drawings]

FIG. 1 is a circuit pattern diagram illustrating an embodiment of a solid-state imaging device according to the present invention.

FIG. 2 is an explanatory diagram for explaining formation of an additional diffusion layer 10;

FIG. 3 is a block diagram illustrating a schematic configuration of a solid-state imaging device.

FIG. 4 is a circuit pattern diagram illustrating a conventional configuration of a solid-state imaging device.

FIG. 5 is a circuit pattern diagram showing another conventional configuration of the solid-state imaging device.

FIG. 6 is an explanatory diagram for explaining a defect in a conventional configuration.

FIG. 7 is an explanatory diagram showing a voltage applied to each electrode in a conventional configuration.

FIG. 8 shows a four-phase drive clock V applied to the vertical transfer device.
1 is a timing chart showing waveforms of 1 to V4 and two-phase drive clocks H1 and H2 applied to horizontal transfer electrodes.

FIG. 9 is an explanatory diagram illustrating transfer of signal charges in a conventional configuration.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Vertical transfer electrode 3 Horizontal storage electrode 4 Horizontal barrier electrode 5 Vertical transfer channel 6 Horizontal transfer channel 7 Horizontal transfer electrode 8 Horizontal transfer electrode 101 Photosensitive section 103 Vertical transfer section 104 Horizontal transfer section 105 Amplifier

Claims (3)

(57) [Claims] A plurality of photoelectric conversion elements which are formed in a matrix on a semiconductor substrate and generate signal charges corresponding to the amount of received light; A plurality of vertical transfer units that take in the vertical transfer channels formed along each column of the element and transfer each of the taken signal charges in the column direction, and in parallel from each vertical transfer channel of the plurality of vertical transfer units. A plurality of signal charges corresponding to one horizontal scan to be output are temporarily held in a horizontal storage electrode straddling the vertical transfer channel, and each held signal charge is taken into a horizontal transfer channel formed in a row direction. A horizontal transfer unit for transferring signal charges in series, from the region where the vertical transfer channel and the horizontal storage electrode overlap to the horizontal transfer channel, and from within the vertical transfer channel to the horizontal transfer channel. A shape widens, the solid-state imaging apparatus characterized by comprising, an impurity diffusion layer formed over on the horizontal transfer channel from said vertical transfer channels. 2. The solid-state imaging device according to claim 1, wherein said impurity diffusion layer is an n-type impurity. 3. A plurality of vertical transfer channels formed on a semiconductor substrate in a column direction to transfer signal charges in a column direction, and a plurality of signal charges output in parallel from each of the plurality of vertical transfer channels. A horizontal transfer unit that temporarily holds the signal charges on a horizontal storage electrode straddling the vertical transfer channel, takes in the held signal charges into a horizontal transfer channel formed in the row direction, and transfers each signal charge in series, The vertical transfer channel extends from the vertical transfer channel to the horizontal transfer channel from the area where the vertical transfer channel overlaps with the horizontal storage electrode, and extends from the vertical transfer channel to the horizontal transfer channel. A parallel-to-serial converter for signal charges, comprising: an impurity diffusion layer formed over the impurity diffusion layer.