JP3332036B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device having a ferroelectric material such as a ferroelectric capacitor applicable to a nonvolatile memory or the like.

2. Description of the Related Art In a nonvolatile memory using a ferroelectric material whose polarization can be inverted by the polarity of an applied voltage, information writing time and information reading time are equal in principle. Further, in the stationary state (at the time of backup), polarization (remanent polarization) is maintained even when no voltage is applied, so that it is considered promising as an ideal nonvolatile memory.

Conventionally, as a semiconductor non-volatile memory using a ferroelectric capacitor, a structure in which a ferroelectric capacitor is integrated on a silicon (Si) substrate as disclosed in US Pat. As described above, a structure in which a ferroelectric film is disposed on a gate electrode of a MIS transistor has been proposed.

A non-volatile memory cell generally has a gate electrode G connected to a word line W, a drain electrode D connected to a bit line B, and one of a ferroelectric capacitor C, as shown in FIG. N with source electrode S connected to the electrode
This is a circuit configuration having a type transistor TR and the other electrode of a ferroelectric capacitor C connected to a plate line P.
As a realistic semiconductor structure of such a memory cell,
Recently, the one shown in FIG. 9 has been proposed. The semiconductor structure shown in FIG. 9 includes a gate oxide film 2 on a P-type silicon substrate 1.
(Polycrystalline silicon) gate electrode 3 formed through the silicon substrate 1 by self-alignment.
An N-type MOS transistor TR including a high-concentration N-type source region 4 and a drain region 5 diffused therein;
A ferroelectric capacitor C is formed on an interlayer insulating film 7 such as phosphor glass on a local oxide film (LOCOS) 6 for element isolation. The ferroelectric capacitor C on the interlayer insulating film 7 is made of platinum. (Pt) lower electrode 8, ferroelectric film 9 such as PZT, and upper electrode 10 such as gold (Au) or platinum (Pt).
Are sequentially laminated. The source region, which is a high-concentration diffusion region, and the upper electrode 10 are connected via the contact hole 11 with the Al wiring 12. Reference numeral 13 denotes a second interlayer insulating film such as phosphor glass.

[0004] Since gold (Au) or platinum (Pt) as the upper electrode 10 is a noble metal, it does not react with the ferroelectric film and good interface characteristics can be obtained. Often used as Also, platinum (P
Since t) has a lattice constant close to that of ferroelectrics such as PZT, the effect of improving crystallinity can be expected, and t) is widely used.

However, platinum (Pt) or gold (Au) as the upper electrode 10 is different from Al as the wiring electrode 12,
Reacts easily at around 300 ° C. Therefore, the wiring electrode 12
If you try to anneal after formation or if you want to form the final protective film (passivation film),
Al serving as a wiring electrode reacts with the upper electrode 10 and reaches the interface between the upper electrode and the ferroelectric film. As a result, the residual polarization decreases, that is, the signal charge decreases, and the relative dielectric constant E decreases.
Deterioration of electrical characteristics such as a decrease in s has occurred.

In the structure in which the ferroelectric capacitor C is formed via the interlayer insulating film 7 on the local oxide film 6 as shown in FIG. However, the length of the wiring 12 from the source storage region 4 to the upper electrode 10 is made redundant, and the area occupied by the memory cell is increased. Therefore, the inventor prototyped a memory cell structure in which a ferroelectric film 9 was directly deposited on the source region 4 as shown in FIG. An upper electrode 14 of platinum (Pt) is formed on the ferroelectric film 9, and the upper electrode 14 is connected to the plate line P by an Al wiring electrode 16. Below the ferroelectric film 9, a lower electrode 17 of Pt or the like is formed via a contact opened in an interlayer insulating film 15 of phosphor glass or the like. Even in such a structure, if the annealing process is performed after the formation of the wiring electrode 16 to improve the characteristics of the ferroelectric capacitor, or if the final protection film (passivation film) is to be formed, the upper electrode 14 and the The wiring electrode 16 reacted, and a normal memory operation could not be performed.

For these reasons, the structure shown in FIGS. 9 and 10 improves the characteristics of the ferroelectric, as described above.
There was a problem that the formation of the final protective film could not be achieved at the same time.

In view of the above problems, the present invention provides a semiconductor device having a structure capable of forming a passivation film and performing an annealing process without impairing the function as a nonvolatile memory using a ferroelectric substance. Is to do.

[0009]

According to the present invention, there is provided a semiconductor device including a capacitor made of a ferroelectric film or a high dielectric constant film as an element element, wherein at least one of the electrodes of the capacitor is conductive. It is characterized by being connected by a sex reaction preventing film.

Further, a semiconductor device according to the present invention comprises an active element formed on or inside a main surface of a semiconductor substrate;
In a semiconductor device in which a capacitor made of a ferroelectric film or a high dielectric constant film formed via an electrode and a wiring electrode connecting the active element isolation oxide film and the capacitor are used as element elements, the wiring electrode includes At least a conductive reaction preventing film is formed, and the electrode and the conductive reaction preventing film are in contact with each other.

Further, the semiconductor device according to the present invention comprises: an active element formed on or inside a main surface of a semiconductor substrate;
In a semiconductor device in which a capacitor made of a ferroelectric film or a high dielectric film formed via an electrode and a wiring electrode connecting the active element isolation oxide film and the capacitor are element elements, the semiconductor device is connected to the wiring electrode. The electrode is characterized in that the electrode has a laminated structure of a conductive reaction preventing film in contact with the wiring electrode and an electrode in contact with the ferroelectric film or the high dielectric constant film.

Further, the semiconductor device according to the present invention comprises: an active element formed on or inside a main surface of a semiconductor substrate;
In a semiconductor device in which a capacitor made of a ferroelectric film or a high dielectric constant film formed through an electrode and a wiring electrode connecting the active element isolation oxide film and the capacitor are element elements, an electrode of the capacitor The semiconductor substrate is connected to a diffusion layer formed on the main surface or inside thereof through a conductive reaction preventing film.

Further, in the semiconductor device according to the present invention, a metal silicide is formed at an interface where the conductive reaction preventing film contacts a spreading layer formed on or inside the main surface of the semiconductor substrate. It is characterized by.

Further, in the semiconductor device according to the present invention, the conductive reaction preventing film may be made of Mo, W, Ti, Ta, Ru, Re.
Mo, W, Ti, Ta, Ru, Re
High melting point metal silicide film of Mo, W, Ti, Ta,
Ru, Re high melting point metal nitride film, Mo, W, Ti, T
a, Ru, Re high melting point metal oxide film, Mo, W, Ti,
It is characterized by being one of a refractory metal nitrided oxide film of Ta, Ru, and Re, and a composite film thereof.

Further, in the semiconductor device according to the present invention, the metal silicide is any one of a high melting point metal silicide film of Mo, W, Ti, Ta, Ru, Re, and a composite film thereof. I do.

Further, in the semiconductor device according to the present invention, the ferroelectric film or the high dielectric constant film may be made of PZT, PLZT, Sr.
It is one of TiO3 and Ta2O5.

The present invention basically provides a structure for forming a ferroelectric substance on the main surface or inside of a semiconductor substrate or semiconductor substrate. A typical semiconductor substrate is a silicon substrate, but a compound semiconductor such as gallium arsenide can be similarly applied to a substrate having an oxygen binding property. The region of the ferroelectric formation structure may be an intrinsic semiconductor region or an N-type or P-type impurity diffusion region. Representative examples of the impurity diffusion region include a source region or a drain region of a MIS transistor and a three-electrode diffusion region of a bipolar transistor. However, the impurity diffusion region is not limited to an active region of an active element, but may be a passive region such as a diffusion resistance layer or a stopper region. A ferroelectric formation structure can be realized on each region of the device. The ferroelectric capacitor structure can be realized in the trench as well as when the ferroelectric capacitor structure is realized in a stacked manner on the element isolation or the diffusion region. That is, the means adopted by the present invention lies in that a conductive reaction preventing film is formed between the upper electrode and the wiring electrode, or that the conductive reaction preventing film itself is used as the wiring electrode. In other words, the present invention employs a laminated structure of a lower electrode, a ferroelectric film, an upper electrode, a conductive reaction preventing film, and a wiring electrode in this order. Generally, as a ferroelectric film, PbTiO3, PZT (PbTi
3, PbZrO3) or PLZT (La, PbTiO)
3, PbZrO3) and the like. Such a ferroelectric film is formed by, for example, a sputtering method or a sol-gel method, and then requires an oxygen annealing treatment to improve a dielectric constant or the like. The electrodes of the ferroelectric film are, for example, Pt, Pd
Pt, which is close to the lattice constant of the crystal of the ferroelectric film in Au or Au, is desirable.

As the conductive reaction preventing film, for example, a Mo film, W
Film, refractory metal film such as Ti film, MoSi film, TiS
a refractory metal silicide film such as an i film, a conductive metal nitride film such as a TiN film, a conductive metal oxide film such as a RuO2 film and a ReO2 film, and a conductive metal nitride oxide film such as a TiON film. A composite film of these films may be used. Such a structure in which the conductive reaction prevention film is sandwiched between the upper electrode and the wiring electrode prevents the annealing process after the formation of the wiring electrode and the reaction between the wiring electrode and the upper electrode in the process of forming the final protective film. In addition, the diffusion of the wiring electrode material (Al) to the interface of the ferroelectric film is prevented, and the deterioration of the electrical characteristics such as a decrease in the relative dielectric constant and a decrease in the polarization charge is prevented. Therefore, a ferroelectric memory having a structure in which a passivation film can be formed or an annealing process can be performed without impairing the function as a memory using a ferroelectric.

According to a second aspect of the present invention, there is provided a structure using the above-mentioned conductive reaction preventing film as a wiring electrode as it is. Since the wiring electrode made of Al and the wiring electrode made of the conductive reaction preventing film become independent, they can be stacked two-dimensionally, greatly contributing to high integration of elements.

A diffusion layer formed on the semiconductor substrate;
To reduce the contact resistance with the conductive reaction preventing film, it is desirable to form a metal silicide film at the interface of the diffusion layer.
These silicide films include Ti, Pt, Ru, R
This is a silicide film containing any one of e, Mo, Ta, and W as a main component.

[0021]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a main plan view showing a semiconductor device provided with a ferroelectric capacitor according to Embodiment 1 of the present invention, and FIG. 2 is a main cross-sectional view showing a cross section taken along the line AA 'in FIG. It is.

This semiconductor device is a non-volatile memory, and has a memory cell shown in FIG. 8 in terms of an equivalent circuit.
In this embodiment, for example, 200 hm. cm P-type silicon substrate 21 as a wafer having a specific resistance of
The structure of the transistor Tr and the ferroelectric capacitor C is formed. As is well known, an N-type MOS transistor T
The semiconductor structure r includes a gate electrode 23 which is a phosphorus-doped polysilicon formed via a gate insulating film (silicon oxide film) 22 on a silicon substrate 21 and a gate electrode 2
Source region 2 as a high-concentration N-type impurity diffusion region in a substrate formed by ion-implanting phosphorus at 80 KV and 5E15 cm −2 by self-alignment (self-alignment) using mask 3 as a mask.
4 and the drain region 25. 26 is about 60 thickness
It is a local oxide film (LOCOS) for element isolation of 0 nm. Reference numeral 30 denotes a first interlayer insulating film. In this embodiment, a structure of a ferroelectric capacitor C as a ferroelectric forming structure is provided on the first interlayer insulating film. This structure has a basic ferroelectric film 29 and upper and lower electrodes 32 and 28 serving as electrode layers vertically sandwiching the ferroelectric film 29.
As the ferroelectric film 29, PbTiO3, PZT (PbT
iO3, PbZrO3) or PLZT (La, Pb
TiO3, PbZO3) or the like, and is formed with a thickness of, for example, 500 nm by, for example, a sputtering method. As the upper electrode, platinum (Pt), palladium (Pd) or gold (A
In u), it is formed to a thickness of 300 nm by a vapor deposition method or a sputtering method. The lower electrode 28 is made of platinum (Pt) or palladium (Pd).
It is formed with a thickness of nm. When platinum (Pt) is selected as the lower electrode 28 and the upper electrode 32, since the lattice constant is close to that of PbTiO3, PZT, or PLZT of the dielectric film 29, the ferroelectric film 29 is crystallized by oxygen annealing. Since the properties are improved, good electrical properties can be obtained. Reference numeral 33 denotes a second interlayer insulating film, which is, for example, phosphor glass having a thickness of about 400 nm formed by a vapor growth method. The connection between the upper electrode 32 and the source region 24 is performed by connecting a conductive reaction preventing film 35 such as TiN having a thickness of about 100 nm formed by a sputtering method and an Al film having a thickness of about 1000 nm formed by a sputtering method or an evaporation method. The wiring electrode 34 is formed by the laminated wiring. The drain region 25 is connected via a contact hole to a laminated film of a conductive reaction preventing film 35 and an Al wiring electrode 34, similar to the source region.

As a method of forming a semiconductor device including such a ferroelectric capacitor, first, after forming a first interlayer insulating film 30 covering the surface of the semiconductor substrate, platinum (Pt) is sputtered on the surface of the semiconductor substrate. Coat on top. Then, a predetermined pattern is formed by a photo technique as a conventional technique, and the lower electrode is etched by, for example, ion milling as a conventional technique to form a pattern of a predetermined lower electrode 28. Thereafter, PZT is coated as a ferroelectric film by a sputtering method or a sol-gel method, and a predetermined pattern is formed by a conventional photo technique. For example, the ferroelectric film is etched by a conventional ion milling to obtain a predetermined pattern. A pattern of the ferroelectric film 29 is formed. Next, platinum (Pt) is coated on the surface of the semiconductor substrate by a sputtering method, a predetermined pattern is formed by a conventional photo technique, and an upper electrode is etched by, for example, ion milling of a conventional technique to etch a predetermined upper electrode. 32 patterns are formed. In the step of forming a capacitor made of the above ferroelectric,
If appropriate, annealing in an atmosphere containing oxygen for improving crystallinity is effective for improving characteristics.

After forming the ferroelectric capacitor as described above, the second interlayer insulating film 33 is formed, and then the contact holes 38, 39, and 40 for the drain region, the source region, and the upper electrode are formed. Then, the conductive reaction preventing film 35 and the wiring electrode 34 are laminated, and a wiring is formed by a photo technique and an etching technique. When a TiN film is used as the conductive reaction preventing film, the TiN film can be formed by a sputtering method using a TiN target, a reactive sputtering method in an atmosphere containing nitrogen using a Ti target, or a sputtering method using Ti. Then, a method of forming a TiN film by annealing in an atmosphere containing nitrogen is cited.

As described above, the conductive reaction preventing film 35 is formed under the wiring electrode 34 made of Al. For this reason, even after forming the wiring electrode, the annealing process at about 500 ° C. can be performed. After the formation of the wiring electrode, a SiO2 film or Si
Vapor-phase growth at about 400 ° C. is used for forming a final protective film made of an N film or the like or for forming an interlayer insulating film such as a SiO 2 film in the case of a two-layer wiring electrode structure.
Since the conductive reaction preventing film 35 exists between the lower electrode 32 and the lower electrode 32, it can be realized without any deterioration in characteristics.

In fact, when the Al wiring electrode and the Pt upper electrode are in direct contact as in the conventional structure, the remanent polarization is 10 microcoulombs and the relative permittivity is 1000 before the formation of the final protective film. However, after the formation of the protective film made of the SiO2 film, the remanent polarization was significantly degraded to 2 microcoulombs and the relative dielectric constant was 250, whereas the conductive reaction preventing film was formed as in this example. A remanent polarization of 9.8 microcoulombs and a relative permittivity of 1000 resulted in a ferroelectric memory with almost no deterioration. Also,
Since plasma SiN and the like conventionally used for semiconductor ICs can be formed as the final protective film, long-term reliability such as moisture resistance can be improved. Furthermore, since a wiring structure of two or more layers can be realized, the degree of freedom in wiring arrangement is greatly increased, and a more sophisticated IC can be configured. The advantage of enabling the wiring structure of two or more layers not only increases the degree of freedom of wiring arrangement, but also contributes to the stabilization of the operation of the ferroelectric memory. That is, in FIG. 1, the plate line P is constituted by the lower electrode 28. When Pt is used for the lower electrode, the sheet resistance of Pt is about one digit larger than that of Al, so that the resistance is put on the plate line, and signal delay and potential instability in the plate line occur. The first layer wiring is used for connection between the source region 24 and the upper electrode 32 as shown in FIG.
By placing the second layer wiring in parallel with the plate line and connecting the plate line and the second layer wiring, the wiring resistance of the plate line is substantially equal to the resistance of the second layer wiring, that is, the Al wiring. The resistance of the plate wire can be reduced,
As a result, the potential of the plate line can be stabilized.

Further, since the conductive reaction preventing film 35 is also formed at the contact portion with the source region and the contact portion with the drain region, the conductive reaction preventing film 35 is formed between Al and the drain in the wiring electrode 34 or Si in the source region. It also blocks reactions. Therefore, Al and S
This is also effective in increasing the junction leakage current due to the reaction of i and increasing the contact resistance in which Si is deposited in the contact hole.

FIG. 3 is a main sectional view showing a semiconductor device according to a modification of the present embodiment. In the figure, the same parts as those shown in FIG. 1 are denoted by the same reference symbols, and the description thereof will be omitted. In the above embodiment, the ferroelectric capacitor is formed on the local oxide film for element isolation. In this modification, the ferroelectric capacitor C is stacked on the source region 24 in a stacked manner. ing. Therefore, the area occupied by the wiring plane between the source region 24 and the lower electrode 42 can be effectively saved, and the cell area can be reduced.

Further, since the conductive reaction preventing film 35 is formed between the upper electrode 41 and the wiring electrode 34, the reaction between the wiring electrode 34 and the upper electrode 41 can be prevented as in the above-described embodiment. In addition, annealing after formation of wiring electrodes and formation of an interlayer film and a final protective film can be performed.

As is clear from the comparison between FIG. 2 and FIG. 3, the upper electrode 32 of FIG.
Since the lower electrode 28 corresponds to the upper electrode 41 of this example in a topological manner, the upper electrode 41 serving as the plate line P and its wiring can be formed of Al. That is, the plate line P
Can be formed on the ferroelectric 29. For this reason, the variation of the plate potential for each cell is remarkably improved as compared with the related art. Further, conventionally, the ferroelectric capacitors C are vertically stacked on a thick LOCOS, and there is a problem in the step coverage of each film. In this example, the ferroelectric capacitors C are provided on both sides of the gate electrode 23. As a result, the step coverage is improved.

FIG. 4 is a main sectional view showing a semiconductor device provided with a ferroelectric capacitor according to the second embodiment of the present invention. In this embodiment, as in FIG. 2, the ferroelectric capacitor C is formed on a local oxide film 26 for element isolation. In this embodiment, in addition to the first embodiment, metal silicides 44 and 43 are provided at a contact portion between the conductive reaction preventing film 35 and the source region 24 and a contact portion with the drain region 25, respectively. The metal silicide is a silicide film containing any one of Ti, Pt, Ru, Re, Mo, Ta, and W as a main component. These metal silicides are composed of the conductive reaction preventing film 35 and the source,
This has the effect of reducing the contact resistance with the drain region.

As a method for forming metal silicide, Ti
In the case of silicide, after forming the opening 40 to the upper electrode, the opening 39 to the source region, and the opening 38 to the drain region, Ti is coated on the entire surface by a sputtering method, and an atmosphere containing nitrogen is formed. Ti silicides 43 and 44 are formed in portions that are in contact with Si by annealing in
A method of simultaneously forming a TiN film 35, which is a conductive reaction preventing film, on the Ti surface or a method of forming only Ti silicide by annealing, etching only unreacted Ti with a mixed solution of ammonia, acetic acid and water, There is a method of leaving only Ti silicide in the region 44 and the drain region 43.

Needless to say, the second embodiment can be applied to the case where the ferroelectric capacitors C are formed on the source region as shown in FIG.

FIG. 5 is a main sectional view showing a semiconductor device having a ferroelectric capacitor according to Embodiment 3 of the present invention. In this embodiment, as in FIG. 1, the ferroelectric capacitor C is formed on a local oxide film for element isolation. The conductive reaction preventing film 50 is laminated on the upper electrode 52. The conductive reaction preventing film 50 and the upper electrode 52 may be simultaneously formed when the upper electrode is etched. Since Al serving as the wiring electrode 51 is in contact with the conductive reaction preventing film 50 laminated on the upper electrode 52, the reaction between Al and Pt is stopped as in the first and second embodiments. In addition, since the wiring electrode is formed of Al as in the conventional case, it is not necessary to particularly provide a metal silicide or the like at a portion in contact with Si, and the process can be shortened. Needless to say, the contact resistance may be reduced by providing a metal silicide as in the second embodiment. Needless to say, the third embodiment can also be applied to the case where the ferroelectric capacitors C as shown in FIG. 3 are formed in a stacked manner on the source region.

FIG. 6 is a main plan view showing a semiconductor device having a ferroelectric capacitor according to Embodiment 4 of the present invention, and FIG. 7 is a cross-sectional view taken along the line BB 'of FIG. In this embodiment, the ferroelectric capacitor C is formed on the gate electrode, and the connection between the upper electrode 32 and the source region 24 is made by the conductive reaction preventing film 61. As the conductive reaction preventing film, a 150 nm TiN film is formed by a sputtering method. Since the wiring 61 made of the conductive reaction preventing film is separated from the Al wiring electrode 62 by the third interlayer insulating film 63, the Al wiring electrode 62 can be arranged above the ferroelectric capacitor C as shown in FIG. Therefore, the occupied area can be greatly reduced. Upper electrode 32 and source diffusion layer 24
Is connected by the conductive reaction preventing film 61,
The 1 wiring electrode is used only for the bit line, and the area occupied is half and the degree of integration is about twice that of the plan view of FIG. The advantage of connecting the upper electrode 32 and the source diffusion layer 24 with the conductive reaction preventing film 61 is not limited to the reduction of the occupied area. That is, the conductive reaction preventing film 6
1 is stable up to about 800 ° C., so that even if the ferroelectric capacitor C deteriorates during formation of the contact hole 64 to the upper electrode or formation of the conductive reaction preventing film 61, the subsequent annealing is performed as 800. It is possible to completely recover by performing annealing at ° C. Further, since the conductive reaction preventing film 61 and the Al wiring electrode 62 are completely separated by the interlayer insulating film 63, the depth of the contact portion where the Al wiring electrode is formed is the same everywhere, so that the contact etch has the same thickness. Therefore, there is also an advantage that the etching becomes easy and the step coverage of the Al wiring is excellent. In contrast, in FIG. 2, the upper electrode portion and the source,
The etching thickness is different in the drain region, which may hinder the detection of the end point of the etching. Further, Al, which is a conventional technique, can be used as the wiring electrode as in the case of the third embodiment, so that there is an effect of shortening the process. Of course, the above-described metal silicide may be formed at the interface between the wiring electrode 62 and the drain region 25 and at the interface between the conductive reaction preventing film 61 and the source region 24 to reduce the contact resistance.

As the above-described ferroelectric diffusion region or the formation structure on the substrate, a nonvolatile memory has been mainly described. However, the present invention is applied to a memory (DRAM) or the like utilizing the large relative dielectric constant of a ferroelectric film. Needless to say,
Further, the present invention can be applied to a circuit network requiring high capacitance. Also, a ferroelectric film has been described as a material forming the capacitor, but SrTiO3 or Ta having a large relative dielectric constant is used.
The present invention can be applied to a case where a memory is to be formed using an oxide film having a high dielectric constant such as 2O5, since these materials require platinum (Pt) or the like as an electrode.

In the embodiment of the present invention, the ferroelectric material and the electrode are formed in a stacked manner. However, the electrode and the ferroelectric film are arranged side by side and the electrode is formed by the conductive reaction preventing film as in the present invention. May be connected.

Furthermore, as an application example of the above-mentioned ferroelectric, a case where it is applied to a memory has been described. However, an element utilizing a pyroelectric effect or a piezoelectric effect of the ferroelectric, such as a pyroelectric sensor, a piezoelectric element, For example, it goes without saying that the present invention can be applied to a piezoelectric sensor and the like.

[0040]

As described above, the semiconductor device provided with a ferroelectric according to the present invention provides a structure for forming a ferroelectric on a main surface or inside a silicon substrate or the like. Even if the ferroelectric electrode and the wiring electrode have strong reactivity, it is possible to form a ferroelectric with no characteristic deterioration. The region of the ferroelectric formation structure may be an intrinsic semiconductor or an N-type or P-type region of an impurity diffusion region. Representative examples include a source region or a drain region of a MIS type transistor and an impurity diffusion region of three electrodes of a bipolar transistor, but are not limited to an active region of an active element, and each region of a passive element such as a resistance diffusion layer or a stopper region. A ferroelectric structure can be realized on the substrate. The ferroelectric capacitor structure can be realized not only in the case where the ferroelectric capacitor structure is realized by stacking on the diffusion region but also in the trench. It is suitable for use in a nonvolatile memory for which high-density integration is required.

[Brief description of the drawings]

FIG. 1 is a main plan view of a first embodiment of the present invention.

FIG. 2 is a main cross-sectional view of Embodiment 1 of the present invention.

FIG. 3 is a main cross-sectional view of a modification of the first embodiment of the present invention.

FIG. 4 is a main cross-sectional view of Embodiment 2 of the present invention.

FIG. 5 is a main cross-sectional view of Embodiment 3 of the present invention.

FIG. 6 is a main plan view of Embodiment 4 of the second means of the present invention.

FIG. 7 is a main sectional view of Embodiment 4 of the second means of the present invention.

FIG. 8 is a circuit diagram showing a nonvolatile memory.

FIG. 9 is a main cross-sectional view showing a semiconductor device including a ferroelectric capacitor according to the related art.

FIG. 10 is a main cross-sectional view showing another example of a semiconductor device including a ferroelectric capacitor according to the related art.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification code FI H01L 21/768 H01L 27/10 651 21/8242 21/88 R 27/108 21/90 A (58) Field surveyed (Int. (Cl. ⁷ , DB name) H01L 27/105 H01L 21/8242 H01L 27/108 H01L 21/28 H01L 21/3205 H01L 21/768

Claims (8)

(57) [Claims] 1. A semiconductor device provided with a capacitor having a ferroelectric film or a high dielectric constant film, wherein an upper electrode located above the ferroelectric film or the high dielectric constant film among electrodes constituting the capacitor. Has a conductive
A conductive reaction preventing film made of a conductive metal nitride film is formed; a wiring electrode is formed on the conductive reaction preventing film; and the conductive reaction preventing film, the upper electrode, and the wiring electrode are electrically connected. Wherein the conductive reaction preventing film and the wiring electrode are connected to a high concentration diffusion region. 2. The capacitor is disposed at a position avoiding the high concentration diffusion region, and the conductive reaction preventing film and the wiring electrode are disposed from the upper electrode to the high concentration diffusion region. 2. The upper electrode and the high concentration diffusion region are electrically connected via the conductive reaction preventing film and the wiring electrode.
13. The semiconductor device according to claim 1. 3. A method according to claim 1, wherein a wiring electrode covering the entire conductive reaction preventing film is disposed on the conductive reaction preventing film, and a wiring is formed by the conductive reaction preventing film and the wiring electrode. The semiconductor device according to claim 1, wherein: 4. The semiconductor device according to claim 1, wherein the capacitor is formed on the high concentration diffusion region. 5. The semiconductor device according to claim 4, wherein a metal silicide is formed at an interface where the conductive reaction preventing film contacts a diffusion layer formed on or inside a main surface of the semiconductor substrate. Semiconductor device. 6. The method according to claim 1, wherein the metal silicide is Mo, W, Ti,
6. The semiconductor device according to claim 5, wherein the semiconductor device is one of a refractory metal silicide film of Ta, Ru or Re and a composite film thereof. 7. The ferroelectric film or the high dielectric constant film is PZ.
2. The semiconductor device according to claim 1, wherein the semiconductor device is one of T, PLZT, SrTiO3, and Ta2O5. 8. A semiconductor device including a capacitor having a ferroelectric film or a high dielectric constant film as an element element, wherein the capacitor is arranged at a position avoiding a high concentration diffusion region, and The upper electrode located above the ferroelectric or high-k film has conductive
A conductive reaction preventing film formed of a conductive metal nitride film is formed in a state of being electrically connected to the upper electrode; and the conductive reaction preventing film extends from the upper electrode to at least one of the high concentration diffusion regions. A semiconductor device, wherein the upper electrode and at least one of the high-concentration diffusion regions are electrically connected via the conductive reaction preventing film.