JP3668246B2 - Field emission cold cathode and manufacturing method thereof - Google Patents

Description

  The present invention relates to a field emission cold cathode and a manufacturing method thereof.

  In recent years, field emission cold cathodes using Si semiconductor processing technology have been actively developed.

  The field emission cold cathode is formed of a conical or pyramidal emitter formed on the cathode electrode and a gate electrode for extracting electrons from the tip of the emitter electrode layer.

  There are roughly two methods of forming a field emission type cold cathode: Spindt method and transfer mold method. When formed by the Spindt method, a gate electrode is formed on an insulating layer formed so as to surround a conical emitter. When formed by the transfer mold method, a gate electrode is formed through an insulating film formed on the side surface of the emitter.

  If a voltage difference is applied between the gate electrode and the emitter in order to extract electrons from the conical emitter, abnormal discharge may occur due to non-uniform shape, etc., or an electric field induced stress between the gate electrode and the emitter. There is a problem in that the gate electrode and the emitter are electrically contacted and short-circuited, and electrons may not be emitted from the emitter.

  In addition, a technique for forming a small field emission array (FEA) in which field emission cold cathodes are two-dimensionally arranged in a row direction and a column direction by tiling on a substrate has been reported. However, there is a problem that it is difficult to electrically connect the gate electrodes formed on the small FEA.

  A technique has been reported in which adjacent gate electrodes are electrically connected using wire bonding to form a large area FEA. However, when wire bonding is used, the manufacturing cost is high.

  As described above, the conventional field emission cold cathode has a problem that the gate electrode and the emitter are brought into contact with each other due to electric field induced stress and short-circuited, and electrons are not emitted from the emitter.

  Further, conventionally, there has been a problem that a large area FEA cannot be manufactured at low cost.

  An object of the present invention is to prevent a short circuit between a gate electrode and an emitter, improve reliability, and make it possible to easily and inexpensively manufacture a large area FEA. And a manufacturing method thereof.

[Constitution]
The present invention is configured as follows to achieve the above object.

A field emission cold cathode according to an example of the present invention includes a plurality of cathode electrodes arrayed in the row direction on an insulating substrate, and electrically connected to any one of these cathode electrodes. A field emission type cold cathode comprising a plurality of emitter electrodes arranged two-dimensionally in the direction and a plurality of gate electrodes formed along the column direction and drawing electrons from the emitter electrodes, wherein the emitter electrode and the gate electrodes are respectively formed in a plurality of structural substrates that are closely arranged on the structure substrate, a gate electrode formed on the structure base adjacent in the column direction, are electrically connected by a film-like gate electrode connecting layer In the gap between adjacent structural bases, a first isolation insulator that closes the opening of the gap is formed .

  Preferred embodiments of the field emission cold cathode are shown below.

  Adjacent structural base joints are formed on a second isolation insulator formed on the insulating substrate.

A method of manufacturing a field emission cold cathode according to an example of the present invention includes a plurality of emitter electrodes arranged two-dimensionally in a row direction and a column direction, and a gate that is formed along the column direction and draws electrons from the emitter electrode. A step of forming a plurality of structural bases on which electrodes are formed and a plurality of cathode electrodes formed in the row direction on the respective structural bases and insulating substrates are adjacent to each other with the emitter electrode layer interposed therebetween. Arranging and adhering the structural bases so that the structural bases are in close contact with each other, forming a separation insulator that closes the openings of the gaps between the arranged structural bodies, and the adjacent structural bases in the column direction And a step of selectively forming a film-like gate electrode connection conductive layer for electrically connecting the gate electrodes on the structural substrate and the gate electrode.

[Action]
The present invention has the following operations and effects by the above configuration.

  A plurality of structural substrates on which a plurality of emitters are formed are two-dimensionally arranged in a tactile manner so as to attach a tile (tiling), and the gate electrode or the cathode electrode is formed, whereby the cathode electrode or the gate electrode is cut off. Therefore, the FEA having a large area can be easily formed. In addition, the productivity can be greatly improved.

  Further, since the insulating layer, the etching stopper layer, and the mold substrate are formed on the convex portion having a sharp tip at the time of tiling, the tip portion of the emitter is protected and each structural substrate can be easily handled.

  By tiling a plurality of structural bases on a substrate and forming a gate electrode or a cathode electrode, it becomes possible to form electrodes continuously, and the electrodes do not break between adjacent structural substrates, A field emission type cold cathode having a large area can be easily formed.

  Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment]
FIG. 1 is a sectional view showing the structure of a field emission cold cathode according to the first embodiment of the present invention.

  An emitter electrode layer 13 is formed on a glass substrate 11 via an ITO electrode layer (cathode electrode) 12. A part of the emitter electrode layer 13 is formed with a protrusion 20 protruding in a pyramid shape with respect to the plane. A silicon oxide film 14 is formed on the emitter electrode layer 13. The silicon oxide film 14 is formed except for the tip of the protrusion 20, and the tip of the protrusion 20 is exposed. A gate electrode 16 made of a tungsten film is formed on the silicon oxide film 14 via a diffusion layer 15 (etching stop layer) in which boron is doped in silicon.

  Next, the manufacturing process of the field emission cold cathode shown in FIG. 1 will be described with reference to the perspective views of FIGS.

  First, as shown in FIG. 2A, an inverted pyramid-shaped recess 18 having a pointed bottom is formed on one surface of a p-type (001) silicon single crystal substrate (mold substrate) 17. As a method for forming the recess 18 in the silicon single crystal substrate 17, there is a method using anisotropic etching of the silicon single crystal substrate.

That is, first, a silicon oxide film having a thickness of 0.1 μm is formed on the surface of a silicon single crystal substrate having a (100) crystal plane orientation by a dry oxidation method, and a resist is further applied by a spin coating method. Next, patterning is performed so that an opening of, for example, 0.8 μm □ is obtained in the resist, and then the silicon oxide film is selectively etched with an NH ₄ F / HF mixed solution using the resist as a mask. After the resist is removed, anisotropic etching is performed on the silicon single crystal substrate using a 30 wt% aqueous KOH solution using the silicon oxide film as a mask, so that an inverted pyramid-shaped recess having a depth of 0.56 μm is formed on the silicon single crystal substrate. Formed on the crystal substrate.

Next, boron is doped on the surface of the silicon single crystal substrate 17 using a thermal diffusion method so as to have a concentration of 3 × 10 ¹⁹ cm ⁻³ or more, and a 0.3 μm thick diffusion layer (etching stop layer) (Rigid layer) 15 is formed.

  Next, as shown in FIG. 2B, a silicon oxide film (insulating layer) 14 having a thickness of about 0.2 μm is formed on the surface of the diffusion layer 15 by using a dry oxidation method. The silicon oxide film 14 can also be formed by depositing silicon oxide by a CVD method or the like.

  Since the silicon oxide film formed by thermal oxidation is dense and easy to control the thickness, it is preferable to form the silicon oxide film by thermal oxidation. By controlling the thickness of the silicon oxide film, the distance between the gate electrode and the emitter to be formed later can be adjusted with high accuracy.

  Further, when the silicon oxide film 14 is formed by thermal oxidation, the bottom end of the recess 18 becomes sharper than the case where the silicon oxide film 14 is formed by deposition due to the growth action of the silicon oxide film 14 inside the recess 18. The tip of the emitter formed in the later process becomes even sharper.

  Next, as shown in FIG. 2C, an emitter electrode layer 13 is formed on the silicon oxide film 14 by depositing a W film to a thickness of 0.9 μm by sputtering. In addition to W, a material such as Mo or Ta can be used for the emitter electrode layer 13.

  Next, an ITO electrode layer 12 having a thickness of about 1 μm to be a cathode electrode is formed on the emitter electrode layer 13 by sputtering. Depending on the material of the emitter electrode layer 13, the formation of the ITO electrode layer 12 can be omitted. When the ITO electrode layer 12 is not formed, the emitter electrode layer 13 also serves as a cathode electrode.

  Next, as shown in FIG. 2D, a 1 mm thick quartz glass substrate 11 having an Al layer 19 having a thickness of 0.4 μm formed on one surface is prepared as an insulating substrate. The electrode layer 12 is bonded. For this bonding, for example, an electrostatic bonding method can be applied. The electrostatic bonding method contributes to reducing the weight and thickness of the cold cathode device.

Next, as shown in FIG. 2E, the Al layer 19 formed on the surface of the glass substrate 11 is selectively removed using a mixed acid solution of HNO ₃ · CH ₃ COOH · HF, and then ethylenediamine · The Si single crystal substrate 17 is selectively removed by etching using an aqueous solution composed of pyrocatechol / pyrazine (ethylenediamine: 75 cc, pyrocatechol: 12 g, pyrazine: 3 mg, water: 10 cc), and the diffusion layer 15 is exposed. Up to this step, a convex portion 20 is formed in which a part of the emitter electrode layer 13, the silicon oxide film 14, and the diffusion layer 15 protrudes in a pyramid shape with respect to the flat portion of the diffusion layer 15.

  When the Si single crystal substrate 17 is etched, the diffusion layer 15 having a thickness of 0.3 μm serves as an etching stop layer that terminates erosion by the etching solution described above, and at the same time, the emitter electrode layer 13 having a sharp tip. It plays the role which protects the convex part 20 from etching solution erosion. Therefore, even when the silicon oxide film 14 is thin, the emitter electrode layer 13 can be protected from the etching solution erosion, and the field emission efficiency from the tip of the convex portion 20 and its uniformity can be greatly improved.

Next, as shown in FIG. 3F, a tungsten layer is deposited on the diffusion layer 15 to a thickness of 0.5 μm by sputtering to form the gate electrode 16. Although depending on the current value at the time of driving, when the boron concentration of the diffusion layer 15 is as high as 10 ²⁰ to 10 ²¹ cm ⁻³ and the resistivity is as low as 10 ⁻⁴ Ω · cm, the diffusion layer 15 15 also serves as a gate electrode, which not only reduces the number of processes and costs, but also greatly contributes to the closeness of the gate-emitter distance.

  Next, as shown in FIG. 3G, a photoresist 21 is applied on the gate electrode 16 by using a spin coating method, and a photoresist 21 of about 0.9 μm is formed on the tip of the pyramidal projection 20. To be formed.

  Next, as shown in FIG. 3H, the surface layer of the resist layer 21 is removed by etching so that the tip of the convex portion 20 appears about 0.7 μm by dry etching using oxygen plasma. Then, the gate electrode 16 and the diffusion layer 15 at the tip of the convex portion 20 are etched using a reactive ion etching method.

Next, as shown in FIG. 3I, after the resist 21 is removed, the silicon oxide film 14 is selectively removed using an NH ₄ F / HF mixed solution. Up to the above steps, an opening is formed in the gate electrode 16 and the tip of the convex portion 20 of the emitter electrode layer 13 is exposed to form a pyramidal cold cathode, that is, an emitter.

  It is also possible to form the ITO electrode layer formed on the quartz glass and the emitter electrode layer by bonding them without forming the ITO electrode layer on the emitter electrode layer.

  According to this embodiment, since the gate electrode is formed of the diffusion layer made of a rigid body, the gate electrode and the convex portion of the emitter electrode layer are not short-circuited.

  The gate wiring is formed of two layers of a gate electrode and a diffusion layer, and its resistivity is lower than the conventional one. Therefore, signal delay can be suppressed when the area is increased.

[Second Embodiment]
FIG. 4 is a sectional view showing the structure of a field emission cold cathode according to the second embodiment of the present invention. 4, parts that are the same as those in FIG. 1 are given the same reference numerals, and explanation thereof is omitted.

  The feature of this embodiment is that the n-type diffusion layer 31 is formed up to the vicinity of the tip of the convex portion 20 formed in the pyramid shape of the emitter electrode layer 12, and the surface of the diffusion layer 31 is substantially flat. It is.

  In the present cold cathode, the diffusion layer 31 is thicker than the cold cathode of the first embodiment, the resistance of the gate wiring is further reduced, and signal delay hardly occurs even when a large area FEA is formed.

  A manufacturing process of the field emission cold cathode shown in FIG. 4 will be described with reference to process cross-sectional views of FIGS. First, as shown in FIG. 5A, an n-type diffusion layer 31 is formed on a surface layer of a p-type (001) silicon single crystal substrate 17 by using a thermal diffusion method or an ion implantation method.

  Next, as shown in FIG. 5B, an inverted pyramid-shaped recess 32 is formed on the diffusion layer 31 and the silicon substrate 17. When forming the recess 32, the opening of the recess 32 is formed in the diffusion layer 31, and the tip of the bottom of the recess 32 is formed in the silicon substrate 17. In order to form the recess 32 in the silicon substrate 17, it can be formed using the method described in the first embodiment.

  Next, as shown in FIG. 5C, a silicon oxide film 14 is formed on the surfaces of the diffusion layer 31 and the silicon substrate 17 by using a dry oxidation method. Next, as shown in FIG. 7D, an emitter electrode layer 13 and an ITO electrode layer 12 to be a cathode electrode are sequentially stacked on the silicon oxide film 14. The emitter electrode layer 13 is formed until the recess is filled.

  Next, as shown in FIG. 5E, a quartz glass substrate 11 having a thickness of 1 mm with an Al layer 19 having a thickness of 0.4 μm formed on the back surface is prepared, and the glass substrate 11 and the silicon single crystal substrate 17 are assembled. The emitter electrode layer 13 is bonded. For this bonding, for example, an electrostatic bonding method can be applied. The electrostatic bonding method contributes to reducing the weight and thickness of the cold cathode device.

  Next, as shown in FIG. 5F, after the Al layer 19 on the back surface of the quartz glass substrate 11 is removed, the silicon single crystal substrate 17 is selectively etched away using an electrochemical etching method, and the diffusion layer 31 is removed. While exposing, the front-end | tip part of the pyramid-shaped convex part 33 by the emitter electrode layer 13 covered with the diffusion layer 31 and the silicon oxide film 14 is exposed.

  In the electrochemical etching method, for example, in a KOH aqueous solution, a p-type silicon single crystal is applied by applying a reverse voltage to a pn junction generated at the interface between the n-type diffusion layer 31 and the p-type silicon single crystal substrate 17. This is a method of selectively etching a substrate.

  Next, as shown in FIG. 6G, the gate electrode 16 is formed on the diffusion layer 31 by electroplating. When the gate electrode 16 is formed using the electroplating method, the gate electrode 16 is selectively formed only on the surface of the conductive diffusion layer 31, so that the insulating silicon oxide film 14 at the tip of the projection 33 is formed. It is not formed on top.

Next, as shown in FIG. 6H, the silicon oxide film 14 is selectively removed using a NH ₄ F / HF mixed solution. Up to this step, openings are formed in the gate electrode 16, the diffusion layer 31, and the silicon oxide film 14, and the tips of the pyramidal protrusions 33 formed by the emitter electrode layer 13 are exposed to form pyramid cold cathodes, That is, an emitter is formed.

  It is also possible to form the ITO electrode layer formed on the quartz glass and the emitter electrode layer by bonding them without forming the ITO electrode layer on the emitter electrode layer.

[Third Embodiment]
FIG. 7 is a sectional view showing the structure of a field emission cold cathode according to the third embodiment of the present invention. In addition, the same code | symbol is attached | subjected to the part same as FIG. 1, and the description is abbreviate | omitted.

  The feature of this embodiment is that a core-like resistance layer 34 is formed between the ITO electrode layer 12 and the emitter electrode layer 35. The emitter electrode layer 35 is formed separately for each convex portion 33, and is electrically connected to the ITO electrode layer 12 by the core resistance layer 34.

  Since the shape of the emitter electrode layer 35 may be different due to variations in manufacturing, a large amount of current flows from the emitter electrode layer 35 having a short distance from the gate electrode 16, so that the gate electrode 16 and the emitter electrode layer 35 are separated from each other. There may be a short circuit between them. However, by inserting the core resistance layer 34 between the emitter electrode layer 35 and the ITO electrode layer 12, the current flowing from the ITO electrode layer 12 to the emitter electrode layer 35 is limited, and a short circuit can be suppressed.

  The manufacturing process of the cold cathode shown in FIG. 7 will be described with reference to the process cross-sectional view of FIG. 8A and 8B are the same as the steps shown in FIGS. 5A and 5B of the second embodiment, and a description thereof will be omitted. Then, an electrode material is deposited on the silicon oxide film 14 as shown in FIG. Then, after forming a resist (not shown) on the electrode material in the region including the recess 32, the electrode material is etched using the RIE method using the resist as a mask to form the emitter electrode layer 35, and the resist is removed.

  Next, as shown in FIG. 8D, a core resistance layer 34 is deposited on the silicon oxide film 34 and the emitter electrode layer 35.

  Next, as shown in FIG. 8E, after the ITO electrode layer 12 is formed on the core-like resistive layer 34, the quartz glass substrate 11 and the ITO electrode layer 12 are bonded to each other as in the second embodiment. The selective removal of the crystal substrate 17 and the formation of the gate electrode 16 are sequentially performed.

  Then, as shown in FIG. 8 (f), as in the second embodiment, by selectively etching the diffusion layer 31 and the silicon oxide film 14, the emitter electrode layer 35 is exposed and the field emission cold cathode is exposed. Is completed.

  Instead of forming the ITO electrode layer on the core-like resistive layer, it is also possible to bond the ITO electrode layer formed on the quartz glass and the emitter electrode layer in advance.

[Fourth Embodiment]
FIG. 9 is a cross-sectional view showing the configuration of the FEA according to the fourth embodiment of the present invention. 9, parts that are the same as those in FIG. 7 are given the same reference numerals, and explanation thereof is omitted.

  A feature of this embodiment is that a cathode base line 43a-d in which a plurality of emitter electrode layers 35 each having a convex portion with a sharp tip are formed on a quartz glass substrate 41 in the row direction. That is, they are two-dimensionally arranged in close contact in the row and column directions on 42a and b. Then, gate electrodes 44a and 44b are arranged on the structural bases 43a to 43d along the column direction.

  FIG. 7 is an enlarged view of the joint portions of the structural bases 43a to 43d. In each structural base 43, many emitter electrode layers 35 are formed in addition to the illustrated portions. Further, although it is illustrated that one structural base is disposed at the intersection between the cathode electrode 42 and the gate electrode 44, a plurality of intersections between the cathode electrode 42 and the gate electrode 44 are formed on one structural base. ing.

  The manufacturing process of this cold cathode is demonstrated using process drawing of FIGS.

  First, as shown in FIG. 10A, after forming the plurality of emitter electrode layers 35 using the steps shown in FIGS. 8A to 8D of the third embodiment, the core resistance layer 34 is formed. Structure bases 43a to 43d that have been formed and patterned are prepared. Further, a quartz glass substrate 41 having cathode electrodes 42a and 42b formed on the surface along the row direction is prepared.

  Next, as shown in FIG. 11B, the structure bases 43a to 43d and the surface on which the cathode electrodes 42a and 42b of the quartz glass substrate 41 are formed are bonded so that the emitter electrode layer 35 is interposed. That is, the core resistance layer 34 and the cathode electrodes 42a and 42b are bonded.

  Next, as shown in FIG. 11C, the silicon single crystal substrate 11 is selectively removed by etching in the same manner as in the third embodiment, so that the protrusions 33 of the diffusion layer 35 are exposed.

  Next, as shown in FIG. 12D, gate electrodes 44a and 44b are formed on the diffusion layer 31 along the column direction using a screen printing method. Since the surface of the diffusion layer 31 has only some protrusions and is flat, the gate electrodes 44a and 44b can be easily formed by screen printing.

  At this time, if the gap between adjacent structural bases 43 is large, the gate electrode 44 may be broken. Therefore, when the gate electrode 44 is formed so as to fill the gap, it is possible to prevent breakage. In addition, the gate electrode 44 may be formed on the glass substrate as long as it is insulated from the cathode electrode 42 when it is formed so as to fill the gap. Further, if the connection electrode is formed on the glass substrate at the position where the gate electrode 44 is formed and the gate electrode is formed on the connection electrode, the electrical connection of the gate electrode can be further ensured. it can.

  Then, as shown in FIG. 12E, after patterning the gate electrodes 44a and 44b to expose the diffusion layer 31, the diffusion layer 31 and the silicon oxide film 14 are sequentially etched, and the tip of the emitter electrode layer 35 is exposed. Exposes sharp convex parts. The FEA of this embodiment is formed by the process described above.

  According to this embodiment, after arranging the structure base on which the plurality of emitters are formed in advance on the quartz glass substrate on which the cathode electrode is formed in advance, the silicon single crystal substrate on the emitter is selectively removed, and the gate electrode By forming the FEA, a large area FEA can be formed without using wire bonding.

  Further, by using a printing method for forming the gate electrode, it is possible to easily form the gate electrode along the column direction.

  In addition, the structure base | substrate 43 was shown in the structure formed through the process shown to FIG. 2 (a)-(c) of 1st Embodiment, or FIG. 5 (a)-(d) of 2nd Embodiment. A structure formed through a process may be used.

[Fifth Embodiment]
FIG. 13 is a cross-sectional view showing the configuration of the FEA according to the fifth embodiment of the present invention. In FIG. 13, the same parts as those in FIG.

  The feature of the FEA of this embodiment is that the gate electrode connection conductive layer 51 (51a, b) is formed on the gate electrode 44 (44a, b). Each of the gate electrode connection conductive layers 51a and 51b is selectively formed on the gate electrode 44 located on the junction between adjacent structural bases 43. By forming the gate electrode connection layer 51, the gate electrode can be reliably connected between the adjacent structural bases 43.

  A manufacturing process of the FEA shown in FIG. 13 will be described with reference to the process diagram of FIG. First, as shown in FIG. 14A, the gate of the region including the joint portion of the adjacent structure base 43 with respect to the structure formed through the steps shown in FIGS. 10A to 12D. On the electrode 44, the gate electrode connection conductive layers 51a and 51b are formed by screen printing. It is also possible to form the gate electrode connection conductive layer 51 by depositing an electrode material on the entire surface and then patterning.

  Next, as shown in FIG. 14B, similarly to the process described in the previous embodiment, the gate electrode 44, the diffusion layer 31, and the silicon oxide film 14 are etched to thereby remove the tip of the convex portion of the emitter electrode layer 35. By exposing, the FEA of this embodiment is completed.

  It is also possible to form the gate electrode connection conductive layer after exposing the tip of the convex portion of the emitter electrode layer 35.

[Sixth Embodiment]
FIG. 15 is a cross-sectional view showing the configuration of the FEA according to the sixth embodiment of the present invention. In FIG. 15, the same parts as those of FIG.

  The feature of this embodiment is that an insulating layer 63 made of glass, SOG (Spin On Glass), silicon oxide, or silicon nitride is embedded in the gap 62 between adjacent structural bases 61a, 61b. Since the insulating layer 63 is embedded in the gap 62, when depositing the gate electrodes 44a and 44b, the gate electrodes 44a and 44b are formed on the ITO electrode layer 44a in the gap 62 at the joint of the structural base. This prevents the gate electrodes 44a, 44b and the ITO electrode layer 42a from being short-circuited.

  The manufacturing process of the FEA shown in FIG. 15 will be described with reference to the process diagrams of FIGS.

  First, the structure shown in FIG. 16A is formed through the steps shown in FIGS. 10A to 11C described above. As illustrated, a gap 62 is formed between the structural base 61a and the structural base 61b.

  Next, as shown in FIG. 16B, an insulating layer 63 is formed so as to fill a gap 62 between the substrates 61a and 61b.

  Next, as shown in FIG. 17C, the insulating layer 63 on the diffusion layer 31 is removed by using an etch back method or the like, and the insulating layer 63 is embedded in the gap 62. Note that it is not necessary to embed all the gaps 62 with the insulating layer 63, and it is sufficient that the gaps 62 are formed so as to close the openings.

  Next, as shown in FIG. 17D, after the gate electrodes 44a and 44b are formed as in the fourth embodiment, the gate electrode, the diffusion layer 31, and the silicon oxide film 14 are selectively removed to remove the FEA. Complete.

  In addition, the structure base | substrate 61 was shown in the structure formed through the process shown to FIG. 2 (a)-(c) of 1st Embodiment, or FIG. 5 (a)-(d) of 2nd Embodiment. A structure formed through a process may be used.

[Seventh Embodiment]
FIG. 18 is a perspective view showing the configuration of the FEA according to the seventh embodiment of the present invention. In FIG. 18, the same parts as those in FIG. 9 are denoted by the same reference numerals, and the description thereof is omitted.

  A feature of the FEA of the present embodiment is that an insulating layer 71 is formed under a region including a joint portion between adjacent structural bases 43. Since the insulating layer is formed under the joint portion between the adjacent structural bases 43, it is possible to prevent the gate electrode 44 and the cathode electrode 42 from being electrically connected.

  The manufacturing process of the FEA shown in FIG. 18 will be described with reference to the process diagrams of FIGS.

  First, as shown in FIG. 19A, structural bases 43a to 43d are prepared in which a core resistive layer 34 is patterned with respect to the structure formed through the steps shown in FIGS. 8A to 8D. To do. In addition, a structural substrate 70 is prepared in which cathode electrode lines 42 a and 42 b and an insulating layer 71 are formed on a quartz glass substrate 41. In addition, the insulating layer 71 is formed in a portion in contact with a region including a joint portion of the adjacent base body 43 when the structural base body 43 is tiled on the structural substrate 70 in a later process.

  Next, as shown in FIG. 20B, the surface of each structural substrate 43 on which the resistance layer 34 is formed is bonded to the surface of the substrate 70 on which the cathode electrodes 42a and 42b are formed. At this time, tiling is performed so that the joint portion of the adjacent structural base body 43 always exists on the insulating layer 71.

  Next, as shown in FIG. 20C, the silicon single crystal substrate 17 is removed, the gate electrodes 44a and 44b are formed, and the gate electrode 44, the diffusion layer 31, and the silicon oxide film 14 are sequentially etched. The FEA of the embodiment is completed.

  In addition, the structure base | substrate 43 was shown in the structure formed through the process shown to FIG. 2 (a)-(c) of 1st Embodiment, or FIG. 5 (a)-(d) of 2nd Embodiment. A structure formed through a process may be used.

[Eighth Embodiment]
21 and 22 are process cross-sectional views illustrating the manufacturing process of the field emission cold cathode according to the eighth embodiment of the present invention.

  First, as shown in FIG. 21A, a structural substrate in which a core resistive layer 34 is patterned on a support substrate 81 and a structure formed through the steps shown in FIGS. 8A to 8D. The silicon substrates 17 of 82a to 82d are temporarily bonded.

  Next, as shown in FIG. 21B, cathode electrodes 83a and 83b are formed on the core-like resistive layer 34 along the row direction using a screen printing method.

  Next, as shown in FIG. 22C, the cathode electrodes 83a and 83b and the quartz glass substrate 84 are bonded. Then, the structure shown in FIG. 11C is formed by removing the support substrate 81 and the silicon single crystal substrate 17. In the subsequent steps, the FEA of the present embodiment is completed by performing the same steps as those shown in FIGS.

[Ninth Embodiment]
FIG. 23 is a perspective view showing the configuration of the FEA according to the ninth embodiment of the present invention. In FIG. 23, the same parts as those of FIG. 9 are denoted by the same reference numerals, and the description thereof is omitted.

  A feature of this embodiment is that a cathode electrode connection conductive layer 92 (92a, 92b) is formed below the cathode electrode 83 in contact with the adjacent structural base and the joint. By forming the cathode electrode connection conductive layer 92, the electrical connection of the cathode electrode 83 between the adjacent structural bases 83 can be ensured.

  A manufacturing process of the FEA shown in FIG. 23 will be described with reference to the process diagram of FIG.

  First, a structure formed through the steps shown in FIGS. 21A and 21B is prepared. Then, a quartz glass substrate 91 having cathode electrode connection electrode layers 92a and 92b formed on the surface is prepared. The cathode electrode connecting conductive layer 92 on the quartz glass substrate 91 is formed on the glass substrate 91 facing the region including the intersection of the junction part of the adjacent structural base and the cathode electrodes 83a and 83b.

  Next, after the cathode electrode connection conductive layer 92 and the cathode electrode 83 are bonded together, the support substrate 81 and the silicon substrate 17 are removed, and the gate electrode 44 is formed, and the diffusion layer 31 and the silicon oxide film 14 are etched. Is completed.

  The present invention is not limited to the above embodiment. For example, an FED (Field Emission Display) or an electron beam exposure apparatus can be formed using the above-described FEA.

  The rigid layer (etching stop layer) is not limited to a diffusion layer in which impurities are doped in silicon, and any material can be used as long as it is harder than the gate electrode and is not displaced by electric field induced stress. Further, a rigid layer may be deposited on a silicon substrate (mold substrate).

  The material of the emitter electrode layer is not limited to tungsten, and various materials having a low work function can be used.

  Further, the FEA can be formed by appropriately combining the manufacturing methods shown in the fourth to ninth embodiments.

  In forming the gate electrode, an evaporation method, a sputtering method, or the like can be used.

  In addition, after the cold cathodes formed by the Spindt method or the like are two-dimensionally arranged and a plurality of structural bases in which the gate electrodes are formed in the column direction are closely arranged, the gate electrodes of the structural bases adjacent in the column direction are arranged. It is also possible to electrically connect with a film-like gate electrode connection layer. In addition, it is possible to similarly tile a structural substrate on which a planar cold cathode in which a gate electrode and a cathode electrode are formed in the same plane is formed.

  When the gate electrode connection layer is formed, breakage may occur at the junction between adjacent structural bases as described in the above-described embodiment. Therefore, when the gate electrode connection layer is formed so as to fill the gap, it is possible to prevent disconnection. Further, the gate electrode connection layer may be formed on the structure substrate as long as it is insulated from the cathode electrode when formed so as to fill the gap. Further, if the connection electrode is formed on the structure substrate at the position where the gate electrode is formed and the gate electrode connection layer is formed on the connection electrode, the electrical connection of the gate electrode is further ensured. Can do.

  It is also possible to form a larger area FEA by two-dimensionally arranging a plurality of structural substrates on which structural bases are arranged. In this case, it is possible to provide a through hole connected to the cathode electrode in the structural substrate, and to electrically connect the cathode electrode of the adjacent structural substrate using the through hole.

  In addition, the present invention can be variously modified and implemented without departing from the scope of the invention.

Sectional drawing which shows the structure of the field emission type cold cathode concerning 1st Embodiment. Process sectional drawing which shows the manufacturing process of the field emission type cold cathode shown in FIG. Process sectional drawing which shows the manufacturing process of the field emission type cold cathode shown in FIG. Sectional drawing which shows the structure of the field emission type cold cathode concerning 2nd Embodiment. Process sectional drawing which shows the structure of the field emission type cold cathode shown in FIG. Process sectional drawing which shows the structure of the field emission type cold cathode shown in FIG. Sectional drawing which shows the structure of the field emission type cold cathode concerning 3rd Embodiment. Process sectional drawing which shows the manufacturing process of the field emission type cold cathode shown in FIG. The perspective view which shows the structure of FEA concerning 4th Embodiment. Process drawing which shows the manufacturing process of FEA shown in FIG. Process drawing which shows the manufacturing process of FEA shown in FIG. Process drawing which shows the manufacturing process of FEA shown in FIG. The perspective view which shows the structure of FEA concerning 5th Embodiment. Process drawing which shows the manufacturing process of FEA shown in FIG. The perspective view which shows the structure of FEA concerning 6th Embodiment. Process drawing which shows the manufacturing process of FEA shown in FIG. Process drawing which shows the manufacturing process of FEA shown in FIG. The perspective view which shows the structure of FEA concerning 7th Embodiment. The perspective view which shows the manufacturing process of FEA shown in FIG. Process drawing which shows the manufacturing process of FEA shown in FIG. Process drawing which shows the manufacturing process of FEA concerning 8th Embodiment. Process drawing which shows the manufacturing process of FEA concerning 8th Embodiment. The perspective view which shows the structure of FEA concerning 9th Embodiment. FIG. 24 is a process chart showing a manufacturing process of the FEA shown in FIG.

Explanation of symbols

11 ... Glass substrate 12 ... ITO electrode layer (cathode electrode)
DESCRIPTION OF SYMBOLS 13 ... Emitter electrode layer 14 ... Silicon oxide film 15 ... Diffusion layer 16 ... Gate electrode 17 ... Silicon single crystal substrate 18 ... Concave 19 ... Al layer 20 ... Convex part 21 ... Resist 31 ... Diffusion layer 32 ... Concave part 33 ... Convex part 34 ... core resistance layer 35 ... emitter electrode layer 41 ... quartz glass substrate 42a, b ... cathode electrodes 43a-d ... structure base 44a, b ... gate electrode 51a, b ... gate electrode connection conductive layer 61 ... structure base 62 ... gap 63 ... Insulating layer 71 ... Insulating separation layer 81 ... Support substrate 83a, b ... Cathode electrode 91 ... Quartz glass substrate 92a, b ... Cathode electrode connecting conductive layer

Claims (3)

A plurality of cathode electrodes arrayed in the row direction on an insulating substrate; a plurality of emitter electrodes electrically connected to any one of these cathode electrodes and arranged two-dimensionally in the row direction and the column direction; A field emission type cold cathode comprising a plurality of gate electrodes formed along the column direction and including a gate electrode for extracting electrons from the emitter electrode;
The emitter electrode and the gate electrode are respectively formed on a plurality of structural bases arranged closely on a structural substrate,
The gate electrodes formed on the structural bases adjacent in the column direction are electrically connected by a film-like gate electrode connection layer ,
A field emission cold cathode characterized in that a first separation insulator for closing an opening of the gap is formed in a gap between adjacent structural substrates . 2. The field emission cold cathode according to claim 1, wherein a junction between adjacent structural bases is formed on a second isolation insulator formed on the insulating substrate. Forming a plurality of structural substrates formed with a plurality of emitter electrodes two-dimensionally arranged in a row direction and a column direction, and gate electrodes that are arranged along the column direction and draw electrons from the emitter electrodes;
Each structural substrate and a plurality of cathode electrodes formed in the row direction on the insulating substrate are aligned and bonded so that the emitter electrode layer is interposed and adjacent structural substrates are in close contact with each other. And a process of
Forming a separation insulator that closes an opening of a gap between the arranged structures; and
And a step of selectively forming a film-like gate electrode connection conductive layer electrically connecting the gate electrodes of the structural bases adjacent in the column direction on the structural base and the gate electrodes. Type cold cathode manufacturing method.

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