JP3818112B2 - Demodulator - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a demodulator that demodulates a received signal by down-converting the received signal into an intermediate frequency signal based on an oscillation signal of a local oscillator.
[0002]
[Prior art]
Conventionally, in mobile communication, in order to demodulate received radio waves, demodulation processing is often performed by down-converting to an intermediate frequency using a local oscillator.
[0003]
QPSK modulation in a conventional: FIG. 5 shows a configuration example of (Quadrature Phase Shift K eying 4 value phase modulation) system demodulator. 1 is a first local oscillator in the conventional example, 2 is a multiplier, 3 is a bandpass filter that removes unnecessary frequency components of the multiplier output, 4 is a limiter, and 5 is a harmonic component of the limiter output. A low-pass filter, 6 a second local oscillator that samples the limiter output signal from which harmonic components have been removed, 7 an AD converter, 8 a quadrature detector for quadrature detection of the AD converter output, and 9 a quadrature 10 is a phase detection unit that detects the phase of the detection output, 10 is a delay detection unit that performs delay detection from the phase detection data output from the phase detection unit, 11 is a subtractor, 12 is an integrator, and 13 is 11. 12 is a conventional AFC (Automatic Frequency Control) unit composed mainly of 12, and 14 is a data signal obtained by extracting and reproducing a clock signal in a bit-synchronized manner using a signal output from the AFC unit. By demodulating, and outputs a reception data reproduction clock BTR: it represents a (Bit Timing Recovery BTR) section.
[0004]
Conventionally, as shown in FIG. 5, the received radio wave having the frequency fc and the first local oscillator 1 having the frequency fLO1 are input to the multiplier 2 to generate an intermediate frequency signal having the frequency fif as the center frequency. At this time, the center frequency may be selected to be 2N times the transmission rate in consideration of ease of demodulation processing in the subsequent stage. For example, when the transmission rate is 2.048 Mbaud (symbol / second), 2N times 2.048 Mbaud is selected as the intermediate frequency signal. Unnecessary frequency components are removed from the multiplier output by the bandpass filter 3. The output of the bandpass filter 3 is input to the limiter 4 and the amplitudes are made uniform. However, in the case of the phase modulation method in which information is given to the phase, the amplitude information does not need to be considered, and the phase information is retained even when the limiter 4 is used. The output of the limiter 4 is input to the low-pass filter 5 to remove the harmonic component of the limiter output. The limiter output signal from which the harmonic component has been removed is input to the AD converter 7 and sampled by the second local oscillator 6. For example, considering the ease of quadrature detection using digital processing, the sampling frequency is set to four times the center frequency of the intermediate frequency signal. In FIG. 5, it is set to 4 fif. The sampled signal is subjected to quadrature detection by the quadrature detection unit 8, and phase information is detected by the phase detection unit 9 that detects the phase of the quadrature detection output. Based on the phase detection data output from the phase detector 9, the delay detector 10 performs delay detection. The conventional AFC unit 13 is mainly composed of a subtractor 11 and an integrator 12. The signal output from the delay detection unit 10 is input to the conventional AFC unit 13, and the frequency error is corrected by subtracting the phase error output from the integrator 12 using the subtractor 11. The signal whose frequency offset is corrected is further input to the integrator 12 to update the phase error and input to the subtractor 11. Thus, the conventional AFC unit 13 shown in FIG. 5 has a feedback structure. The corrected subtraction result is set as an AFC output and input to the BTR unit 14 to output received data and a recovered clock.
[0005]
[Problems to be solved by the invention]
By the way, when the transmission rate is 2.048 Mbaud in the conventional example, since 2N times the transmission rate is selected as the center frequency of the intermediate frequency signal, the center frequency fif is 8.192 MHz, 12.292 MHz, or the like. Will be selected. Therefore, for example, when a carrier wave of 5840 MHz is used as a received radio wave, a first local oscillator having a center frequency of 5831.808 MHz must be employed when down-converting to an intermediate frequency signal.
[0006]
However, when the frequency of the first local oscillator becomes 5831.808 MHz or the like, the number of digits increases and a high-accuracy local oscillator is required. If the accuracy is not sufficiently satisfied, phase noise increases and reception performance deteriorates. there's a possibility that.
[0007]
Accordingly, an object of the present invention is to obtain a demodulator that creates an intermediate frequency signal using a local oscillator that does not require sufficient accuracy and demodulates a received signal.
[0008]
[Means for Solving the Problems]
A demodulating device according to a first aspect of the present invention includes a local oscillator that outputs an oscillation signal that is offset from the center frequency of a received radio wave, a multiplier that down-converts the received radio wave to an intermediate frequency signal based on the output of the local oscillator, and the multiplier An AD converter that converts the output signal into a digital signal, and a controller that performs a frequency offset correction for a fixed frequency on the output of the AD converter .
[0009]
A demodulator according to a second aspect of the present invention includes a first local oscillator that outputs an oscillation signal that is offset by a fixed frequency, and a multiplier that down-converts the received radio wave into an intermediate frequency signal based on the output of the first local oscillator. , A filter for removing unnecessary frequency components or harmonic components of the intermediate frequency signal output from the multiplier, a second local oscillator, and an output signal from which the harmonic components have been removed to the second local oscillator An AD converter for sampling based on the digital signal, a quadrature detection unit for quadrature detection of the output of the AD converter, a phase detection unit for detecting the phase of the quadrature detection output, and an output from the phase detection unit A delay detector that performs delay detection based on the phase detection data, and an offset corresponding to the fixed frequency is added to the integral value of the output of the delay detector, and the output of the delay detector From those having a AFC unit for performing frequency offset correction by subtracting the phase error of the added value, and a BTR section for outputting received data and the reproduction clock from the output signal of the AFC unit.
[0010]
A demodulating device according to a third aspect of the invention includes a first local oscillator that outputs an oscillation signal that is offset by a fixed frequency, and a multiplier that down-converts the received radio wave into an intermediate frequency signal based on the output of the first local oscillator. , A filter for removing unnecessary frequency components or harmonic components of the intermediate frequency signal output from the multiplier, a second local oscillator, and an output signal from which the harmonic components have been removed to the second local oscillator An AD converter for sampling based on the digital signal, a quadrature detection unit for quadrature detection of the output of the AD converter, a phase detection unit for detecting the phase of the quadrature detection output, and an output from the phase detection unit A delay detector that performs delay detection from the phase detection data, an adder that adds an offset of the fixed frequency to the output of the delay detector, and an output of the adder And AFC unit that performs subtraction to the frequency offset correcting the phase error of the integrated value of Luo said adders, in which a BTR section for outputting received data and the reproduction clock from the output signal of the AFC unit.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1 FIG.
FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention. In the figure, 15 is a first local oscillator having a fixed frequency offset in the present invention, 16 is a bandpass filter in the present invention, 17 is an adder, 18 is a subtractor 11, an integrator 12 and an adder 17. The improved AFC portion mainly configured is shown, and the other reference numerals are the same as or equivalent to those of the conventional example.
[0012]
Next, the operation will be described. In FIG. 1, a received radio wave having a frequency fc and an oscillation signal from a first local oscillator 15 having a frequency fLO1 + Δf are input to a multiplier 2 to generate an intermediate frequency signal having a frequency fif−Δf as a center frequency. Here, Δf represents a fixed frequency offset, and is a frequency offset in which the number of digits of the center frequency of the first local oscillator is reduced by fLO1 + Δf. Hereinafter, as a specific example, an example in which the center frequency fc of a received radio wave used in DSRC (dedicated narrow area communication) such as a communication device for ETC ( Electronic Toll Collection System ) is 5840 MHz will be described. At this time, the transmission rate is set to 2.048 Mbaud, and the center frequency of the intermediate frequency signal is set to 8.192 MHz which is four times the transmission rate in consideration of ease of demodulation processing in the subsequent stage.
[0013]
At this time, in the apparatus of the conventional example, it is necessary to create an intermediate frequency signal with the frequency of the first local oscillator set to 5831.808 MHz. However, since the number of digits of the frequency is large, a fixed frequency offset of 192 kHz is provided, and the frequency of the first local oscillator is 5832 MHz. In this example, 192 kHz corresponds to Δf, and 5832 MHz corresponds to fLO + Δf. Therefore, the center frequency fif-Δf of the intermediate frequency signal which is the multiplier output is 8 MHz. Unnecessary frequency components are removed from the multiplier output by a band-pass filter 16 whose center frequency is fif−Δf. The processing from the output of the bandpass filter 16 to the delay detection unit 10 is the same as in the conventional example. The output of the delay detection unit 10 is input to the improved AFC unit. The improved AFC unit 18 is obtained by adding a function of correcting the fixed frequency offset to the conventional AFC unit 13. As shown in FIG. 1, an adder 17 is added between the integrator 12 and the subtractor 11, and a fixed frequency offset is subtracted by adding a fixed frequency offset Δf to the integrator output to subtract the fixed detection offset. The frequency offset including is corrected. In FIG. 1, it is assumed that a fixed frequency offset Δf is added to the adder, and that it operates at a symbol rate. The subtraction result after correction of the frequency offset including the fixed frequency offset is set as an AFC output, which is input to the BTR unit 14 to output received data and a recovered clock. By using this improved AFC unit 18, it is possible to demodulate even an intermediate frequency signal having a fixed frequency offset.
[0014]
Embodiment 2. FIG.
FIG. 2 is a block diagram showing the configuration of the second embodiment of the present invention. In the figure, 17 represents an adder, 13 represents a conventional AFC unit, and the rest is the same as in FIG.
[0015]
Next, the operation will be described. The operations from the multiplier 2 to the delay detection 10 are the same as those in the first embodiment. In the second embodiment, an adder 17 is inserted between the delay detection unit 10 and the conventional AFC unit 13. By inputting the delay detection output and the fixed frequency offset Δf into the adder 17, the fixed frequency offset Δf is corrected. In FIG. 2, it is assumed that the processing of the adder 17 is performed at the symbol rate. The adder output, which is a signal with the fixed frequency offset corrected, is input to the conventional AFC unit 13 and normal frequency offset correction is performed. The AFC output output from the conventional AFC unit 13 is input to the BTR unit 14 to output received data and a reproduction clock synchronized with the received data. Thus, by inserting the adder 17 in front of the conventional AFC unit 13 and correcting the fixed frequency offset, the same effect as in the first embodiment can be obtained, and the conventional AFC unit can be used as it is. It becomes possible.
[0016]
Embodiment 3 FIG.
Embodiment 1, and in 2 but using the limiter demodulator, as another embodiment, FIG. 3 or AGC as in Figure 4: may be used (Automatic Gain Control Automatic Gain Control) Absent. In addition to the configurations in the first and second embodiments, the first local oscillator has a fixed frequency offset, and an improved AFC unit to which a fixed frequency offset correction function is added as in the first embodiment is used. As long as the configuration can be demodulated by adding an adder to the previous stage of the conventional AFC unit and correcting the fixed frequency offset as shown in FIG.
[0017]
【The invention's effect】
According to the first aspect of the invention, it is possible to demodulate the intermediate frequency signal using the local oscillator that oscillates at a frequency having a smaller number of digits than the conventional one.
[0018]
According to the second invention, a first local oscillator having a fixed frequency offset, a multiplier, a filter for removing unnecessary frequency components or harmonic components, a second local oscillator, an AD converter, and quadrature detection Unit, phase detection unit, delay detection unit, AFC unit for correcting a fixed frequency offset, and BTR unit, using a local oscillator that oscillates at a frequency with a smaller number of digits than conventional ones. The signal can be demodulated.
[0019]
According to the third invention, a first local oscillator having a fixed frequency offset, a multiplier, a filter for removing unnecessary frequency components or harmonic components, a second local oscillator, an AD converter, and quadrature detection The same effect as that of the first invention can be obtained by providing the unit, the phase detection unit, the delay detection unit, the adder for correcting the fixed frequency offset, the AFC unit, and the BTR unit. The AFC unit can be used as it is.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a demodulator according to Embodiment 1 of the present invention.
FIG. 2 is a diagram showing a configuration of a demodulation device according to Embodiment 2 of the present invention.
FIG. 3 is a diagram illustrating a configuration of a demodulator according to another embodiment in which the limiter according to the first embodiment is replaced with AGC.
4 is a diagram illustrating a configuration of a demodulator according to another embodiment in which the limiter according to the second embodiment is replaced with AGC. FIG.
FIG. 5 is a diagram illustrating a configuration of a conventional demodulator.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 1st local oscillator 2 in a prior art example 3 Multiplier 3 Bandpass filter 4 in a prior art example 4 Limiter 5 Low pass filter 6 2nd local oscillator 7 AD converter 8 Quadrature detection part 9 Phase detection part 10 Delay detection part 11 Subtractor 12 Integrator 13 Conventional AFC unit 14 BTR unit 15 First local oscillator 16 used in the present invention 16 Band pass filter used in the present invention 17 Adder 18 Improved AFC unit 19 in the present invention AGC

Claims (3)

A local oscillator that outputs an oscillation signal offset from the center frequency of the received radio wave, a multiplier that down-converts the received radio wave to an intermediate frequency signal based on the output of the local oscillator, and converts the output signal of the multiplier into a digital signal A demodulator comprising an AD converter and a controller for correcting a frequency offset for a fixed frequency with respect to the output of the AD converter . A first local oscillator that outputs an oscillation signal offset by a fixed frequency, a multiplier that down-converts the received radio wave into an intermediate frequency signal based on the output of the first local oscillator, and an intermediate that is output from the multiplier A filter for removing unnecessary frequency components or harmonic components of a frequency signal, a second local oscillator, and an output signal from which the harmonic components have been removed are sampled based on the second local oscillator and converted into a digital signal An AD converter, a quadrature detection unit that quadrature-detects the output of the AD converter, a phase detection unit that detects the phase of the quadrature detection output, and delay detection from the phase detection data output from the phase detection unit Adding an offset for the fixed frequency to the integrated value of the output of the delay detector and the delay detector, and calculating the phase error of the added value from the output of the delay detector Demodulation apparatus comprising: a AFC unit for performing frequency offset correction is calculated, and a BTR section for outputting received data and the reproduction clock from the output signal of the AFC unit. A first local oscillator that outputs an oscillation signal offset by a fixed frequency, a multiplier that down-converts the received radio wave into an intermediate frequency signal based on the output of the first local oscillator, and an intermediate that is output from the multiplier A filter for removing unnecessary frequency components or harmonic components of a frequency signal, a second local oscillator, and an output signal from which the harmonic components have been removed are sampled based on the second local oscillator and converted into a digital signal An AD converter, a quadrature detection unit that quadrature-detects the output of the AD converter, a phase detection unit that detects the phase of the quadrature detection output, and delay detection from the phase detection data output from the phase detection unit A delay detector to perform, an adder for adding an offset corresponding to the fixed frequency to the output of the delay detector, and a phase of an integral value of the adder from the output of the adder Demodulation apparatus comprising: a AFC unit that performs subtraction to the frequency offset correcting the difference, and a BTR section for outputting received data and the reproduction clock from the output signal of the AFC unit.

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