JP4044112B2 - Multilayer wiring board, manufacturing method of multilayer wiring board, and electronic component package - Google Patents

Description

The present invention relates to a multilayer wiring board , a method for manufacturing a multilayer wiring board , and an electronic component package , and more particularly to a multilayer wiring board in which interlayer connection of conductive wiring layers is performed using conductive pillars, a method for manufacturing a multilayer wiring board, and a semiconductor device, for example The present invention relates to an electronic component package in which highly integrated electronic components such as a chip size package (CSP) are mounted on a wiring board .

  With the miniaturization and high functionality of various electronic devices, the demand for high mounting density of electronic components is increasing. Correspondingly, a multilayer wiring board having a structure in which an insulating layer and a wiring layer are alternately laminated is widely used as the wiring board. The multilayer wiring board responds to the demand for higher density and higher functionality by increasing the number of wiring layers, and via connection is made between the wiring pattern layers.

  FIG. 24 is a sectional view showing an example of a sectional structure of a conventional multilayer wiring board. This multilayer wiring board 901 is formed by via-connecting wiring circuits formed over five layers. The first wiring circuit 901, the second wiring circuit 902, the third wiring circuit 903, the fourth wiring circuit 904, and the fifth wiring circuit 905 are each formed by patterning a conductor layer. The wiring circuits of these layers are insulated by insulating layers 906, respectively.

A general manufacturing method of the multilayer wiring board having the structure illustrated in FIG. 24 will be described.
First, in order to make a connection between layers of a double-sided laminated board in which a conductive layer such as a copper foil is bonded to both sides of the insulating layer, through holes 907 are formed in portions to be electrically connected to the double-sided laminated board. Then, chemical plating is applied to the inner wall surface of the through hole 907, and further electroplating is performed to thicken the conductor layer 907b on the inner wall surface of the through hole, thereby improving the reliability of interlayer connection.

  Next, the conductive layers on both sides are patterned into a predetermined circuit by, for example, a photoetching method.

Next, an insulating layer such as a prepreg layer is laminated on the patterned conductor layer, and further a conductor layer such as a copper foil is laminated and integrated by heating and pressing. Multilayering is performed by repeating the steps from formation of a through hole to circuit patterning.
A multilayer wiring board in which such interlayer connection of wiring layers is performed by via holes has a problem that it is difficult to cope with high-density mounting.

  For example, generally speaking, a wiring cannot be formed in a region provided with a through hole, and an electronic component cannot be mounted, so that an improvement in wiring density and mounting density is restricted. In recent years, the wiring of wiring boards has also been densified along with the high-density mounting of electronic components. In order to cope with such miniaturization of wiring, if it is attempted to reduce the diameter of the through hole, it becomes difficult to ensure the reliability of interlayer connection.

  In addition, the formation of the connection between the wiring layers by the through hole is redundant because it involves a through hole forming process and a plating process, and there is a problem from the viewpoint of productivity.

  For example, in the process of forming a through hole, a hole is drilled one by one, so that a lot of time is required for the drilling operation. Furthermore, after the through hole is made, a polishing process for deburring is required. Moreover, high accuracy is required for the formation position of the through hole, and it is necessary to take into consideration the plating adhesion on the inner wall surface of the through hole. For this reason, the precision of through-hole formation, management of formation conditions, etc. are also complicated.

  In addition, in the plating process for forming electrical connections between a plurality of wiring layers through through holes, process management such as chemical liquid concentration management and temperature management is complicated. Furthermore, the equipment for forming the through holes and the equipment necessary for plating become large.

  Such interlayer connection of the multilayer wiring board by the through hole reduces the productivity of the wiring board (PWB), and it is difficult to meet the demand for cost reduction.

  In order to simplify the electrical connection between the wiring layers of the multilayer wiring board, a method of connecting the wiring layers with conductive bumps has also been proposed. In this method, conductive bumps are formed on via lands, which are interlayer connection portions formed in a wiring circuit, and the conductive bumps are formed in opposing wiring layers by penetrating the interlayer insulating layer in the thickness direction. Establish a connection with Beerland.

  25A and 25B are diagrams showing an example of a method for manufacturing a multilayer wiring board in which wiring layers are connected using such conductive bumps.

  First, for example, a double-sided wiring board 913 in which wiring circuits 912 made of copper are formed on both sides of a paper-phenolic insulating resin base material 911 is prepared as an inner layer core. The wiring circuits 912 formed on both surfaces of the insulating resin base material 911 have via lands 912a for interlayer connection. On this via land 912a, for example, conductive bumps 914 formed by printing a conductive paste are formed.

  Next, the B-stage (semi-cure state) insulating resin sheet 915 and the copper foil 916 are laminated, and the wiring circuit 912 and the copper foil 916 are opposed to both sides of the double-sided wiring board 913 via the insulating resin sheet 915. (Fig. 25A).

  Then, by pressurizing and heating these laminates, the B-stage insulating resin sheet 915 is cured and all layers are integrated. At this time, the conductive bump 914 penetrates the B-stage (semi-cure) insulating resin sheet 915 by pressurization, and is integrally joined to the copper foil 916 while causing plastic deformation or the like. Thus, the connection between the conductor layers by the conductive bump is formed.

  Then, a through hole 917 is formed at a predetermined position, and the through hole 917 is filled with a conductive material such as silver paste 918 or the inner wall of the through hole 917 is coated with a conductive material such as silver paste. To connect the outer conductor layers. The outer layer copper foil 916 is patterned by, for example, a photoetching method to form a predetermined wiring circuit 916b including the via land 916a, thereby forming a multilayer wiring board in which conductive bumps and through holes are combined in the interlayer connection of the wiring circuit. (FIG. 25B).

  26A and 26B are diagrams showing another example of a method for manufacturing a multilayer wiring board in which wiring layers are connected using conductive bumps.

  First, for example, a double-sided wiring board 923 having a wiring circuit 922 formed by attaching a copper foil on both sides of a glass cloth and an epoxy resin base material 921 and curing and patterning is prepared as an inner layer core. The wiring circuits 922 formed on both surfaces of the double-sided wiring board 923 have interlayer connection via lands 922a.

  Meanwhile, a copper foil 925 on which conductive bumps 924 are formed and an epoxy resin prepreg 926 are prepared. The conductive bumps 924 are formed at positions corresponding to the via lands 922a when the copper foil 925 is laminated with the double-sided wiring board 923.

  Next, as shown in FIG. 26A, copper foil 925 is disposed on both sides of the double-sided wiring board 923 via prepreg 926, and then all layers are integrated by pressing and heating. At this time, the conductive bumps 924 face each other by pressurization. At this time, the conductive bump 924 penetrates the B-stage (semi-cure) prepreg 926 by pressurization, and is integrally joined to the via land 922a while causing plastic deformation or the like. Thus, the connection between the conductor layers by the conductive bump is formed.

Then, through holes 927 are formed at predetermined positions, and conductor layers 928 such as copper are plated on the through holes 927 to connect the conductor layers.
Thereafter, the outer layer copper foil 925 is patterned by, for example, a photoetching method to form a predetermined wiring circuit 926b including the via land 925a, so that a multilayer wiring in which conductive bumps and plated through holes are combined in the interlayer connection of the wiring circuit A substrate is formed (FIG. 26B).

  The wiring circuit interlayer connection employing such conductive bumps has advantages such as a simple configuration, a small number of processes and high productivity, and compatibility with high-density mounting. However, problems such as those described below are often recognized in a wiring board that employs conductive bumps to perform interlayer connection of wiring circuits.

  For example, in the case of the manufacturing method illustrated in FIG. 25, the insulating resin layer 915 and the copper foil 916 are laminated on the double-sided wiring board 913 in which the conductive bumps 914 are formed on the via lands 912a, and the outer sides thereof are arranged. Apply a hard metal press plate and press and heat from both sides to unify all layers.

  By this pressing step, the copper foil 916 exposed to the outer layer becomes substantially flat. However, since the conductive bumps 914 are generally harder than the insulating resin base material 911 of the double-sided wiring board 913, the via land 912a tends to be concave, and the via connection portion is damaged, for example, the via land 912a is cracked. Sometimes. Such a problem is particularly remarkable in the connection portion on the outer layer side.

  FIG. 27 is a diagram schematically illustrating the via connection portion of the multilayer wiring board described with reference to FIG. In the worst case, the via land 922a and the wiring circuit 922 may be disconnected and lose the function as a multilayer wiring board. The same problem is recognized also in the method illustrated in FIG.

  Such a problem greatly reduces the reliability of the multilayer wiring board and is one of the main causes for reducing the productivity of the wiring board.

The present invention has been made to solve the above circumstances, the multilayer wiring board with high via connections reliable, equipped with high their preparation and highly integrated electronic components productive on a wiring substrate An object of the present invention is to provide an electronic component package .

  As a problem of a conventional multilayer wiring board using conductive bumps, it is desired to further improve the reliability of interlayer connection when a thermal load or a mechanical load (stress) is applied.

  The reliability of the wiring board in which the wiring circuit is connected between the layers using the conductive bump as exemplified in FIGS. 25 and 26 is not particularly problematic under normal use conditions.

  However, when used in, for example, industrial electronics equipment that requires high reliability, further improvement in the reliability of interlayer connection is desired.

  A wiring board that requires high reliability must withstand severe thermal stress. For example, even when a cold / thermal cycle test is performed to cool to about −65 ° C. after exposure to a high temperature of about 125 ° C., conductive bumps that connect a plurality of wiring layers to each other may peel off from the wiring layers, The internal wiring circuit must not be damaged.

  However, the connection between the conductive bump and the wiring layer to which the conductive bump is connected may be peeled off due to thermal stress, and it is desired to improve the reliability so that it can sufficiently withstand more advanced industrial applications. Yes.

The present invention has been made to solve such problems. That is, an object of the present invention is to provide a multilayer wiring board and a method for manufacturing the same which maintain the merit of using conductive bumps and improve the reliability of interlayer connection.

In recent years, the integration of electronic components such as semiconductor elements has been remarkably increased, and a mounting problem has also occurred. For example, the number of connections between electronic components and external circuits has increased with higher integration. Establishment of a high-density mounting technique that can connect more electrodes with a smaller area is required .
The present invention has achieved also solve such a problem, also aims to provide an electronic component package equipped with highly integrated electronic components on the wiring board.

  The present invention has been made to solve such problems.

That is, the multilayer wiring board of the present invention according to claim 1 is a multilayer wiring board in which a wiring layer and an insulating layer are laminated, and includes a first insulating layer having a first surface and a first insulating layer. A first wiring layer formed on the first surface and having a first via land in which a through hole is formed; and a second insulation formed on the first insulating layer from above the first wiring layer. A layer, a second via land formed on the second insulating layer so as to face the first via land, the first via land and the second via land, and a through hole of the first via land. And a conductive pillar having a portion penetrating into the first insulating layer.
A multilayer wiring board according to a second aspect of the present invention is the multilayer wiring board according to the first aspect, wherein the rigidity of the conductive pillar is larger than the rigidity of the first insulating layer.
A multilayer wiring board according to a third aspect of the present invention is the multilayer wiring board according to the first aspect, wherein the conductive pillar is made of a conductive resin.
The multilayer wiring board of the present invention according to claim 4 is the multilayer wiring board according to claim 1, wherein the shape of the contact portion between the conductive pillar and the first via land and the second via land is The outer side surface of the conductive pillar and the surface of the first via land and the second via land have a smoothly continuous portion.
The multilayer wiring board of the present invention according to claim 5 is the multilayer wiring board according to claim 1, wherein the shape of the contact portion between the conductive pillar and the first via land and the second via land is It has a portion where the angle formed between the outer side surface of the conductive pillar and the surfaces of the first via land and the second via land is an acute angle.
According to a sixth aspect of the present invention, there is provided a method of manufacturing a multilayer wiring board according to the present invention, comprising: forming a first wiring layer having a first via land having a through hole on a first insulating layer; An upper conductive layer having a substantially conical shape in a region corresponding to the first via land of the first wiring layer, and the first insulating layer and the conductive layer are connected to the first via land and the conductive layer. A step of disposing through an uncured insulating resin layer so as to face the conductive pillar, and a part of the conductive pillar penetrates into the first insulating layer through a hole formed in the first via land. Thus, there is a step of pressing the first insulating layer and the conductor layer in the axial direction of the conductive pillar to connect the first via land and the conductive pillar.
According to a seventh aspect of the present invention, there is provided a method for manufacturing a multilayer wiring board according to the present invention, comprising: forming a first wiring layer having a first via land having a through hole on a first surface of a first insulating layer; A step of forming a conductive pillar having a substantially conical shape on the first via land of the first insulating layer, and a head of the conductive pillar exposed on the first surface of the first insulating layer. A step of laminating an uncured insulating resin layer, a step of disposing a conductor layer opposite to the first surface of the first insulating layer via the insulating resin layer, and one of the conductive pillars. The first insulating layer and the conductor layer are pressurized in the axial direction of the conductive pillar so that the portion penetrates into the first insulating layer through the hole formed in the first via land, A step of connecting via land and the conductive pillar.
The method for manufacturing a multilayer wiring board according to claim 8 includes the step of forming a first wiring layer having a first via land having a through hole on the first insulating layer, and the first wiring. Forming a first conductive pillar having a substantially conical shape on the first via land of the layer; and a substantially conical shape in a region corresponding to the first via land of the first wiring layer on the conductor layer. Forming a second conductive pillar having an uncured insulating property such that the first conductive pillar and the second conductive pillar face each other between the first insulating layer and the conductor layer. The first insulating layer and the conductor so that a part of the first conductive pillar penetrates into the first insulating layer through a through hole formed in the first via land; The first and second conductive pillars are pressed in the axial direction of the first and second conductive pillars. Characterized by a step of connecting the sex pillar.
An electronic component package according to a ninth aspect of the present invention is an electronic component package in which an electronic component is mounted on a wiring board, the electronic component having an electrode on the first surface, the first surface, and the second surface. A first insulating layer formed on the electronic component facing the first surface of the electronic component and a second surface of the first insulating layer. A first wiring layer having a first via land, and a first conductive pillar connecting the first via land and the electrode, wherein the first via land has a through hole. Features.
An electronic component package according to a tenth aspect of the present invention is the electronic component package according to the ninth aspect, wherein the contact portion between the first conductive pillar and the electrode is an outer surface of the first conductive pillar. The electrode surface has a smoothly continuous portion.
The electronic component package of the present invention according to claim 11 is the electronic component package according to claim 9, wherein the contact portion between the conductive pillar and the electrode is an outer surface of the conductive pillar and a surface of the electrode. It has the part which the angle | corner which forms is an acute angle.
An electronic component package according to a twelfth aspect of the present invention is the electronic component package according to any one of the ninth to eleventh aspects, wherein the electronic component is a semiconductor element.
An electronic component package according to a thirteenth aspect of the present invention is the electronic component package according to the twelfth aspect, wherein the semiconductor element is a bare chip.
An electronic component package according to a fourteenth aspect of the present invention includes an electronic component having a pad-like electrode on a first surface, a first surface and a second surface, and the first surface is the electronic device. A first insulating layer formed on the electronic component facing the first surface of the component, and a first wiring layer formed on the second surface of the first insulating layer and having a first via land And a first conductive pillar connecting the first via land and the electrode, a first surface and a second surface, the first surface being the second surface of the first insulating layer A second insulating layer formed on the first insulating layer opposite to the first insulating layer; a second wiring layer formed on the second surface of the second insulating layer and having a second via land; And a second conductive pillar connecting the second via land, and the first via land or the second via land has a through hole. And butterflies.
The electronic component package of the present invention according to claim 15 is the electronic component package according to claim 14, wherein the contact portion between the first conductive pillar and the electrode is an outer surface of the first conductive pillar. The electrode surface has a smoothly continuous portion.
The electronic component package according to a sixteenth aspect of the present invention is the electronic component package according to the fourteenth aspect, wherein the contact portion between the conductive pillar and the electrode includes an outer surface of the conductive pillar and a surface of the electrode. It has the part which the angle | corner which forms is an acute angle.
An electronic component package according to a seventeenth aspect of the present invention is the electronic component package according to any one of the fourteenth to sixteenth aspects, wherein the electronic component is a semiconductor element.
An electronic component package according to an eighteenth aspect of the present invention is the electronic component package according to the seventeenth aspect , wherein the semiconductor element is a bare chip.

  In the present invention, the method for forming the conductive pillar includes a step of disposing a mask having a substantially cylindrical through hole on the conductor layer, a step of filling the through hole of the mask with a conductive resin, and the conductive And a step of separating the conductor layer and the mask in parallel with the normal direction of the conductor layer so that the resin has a substantially conical shape on the conductor layer.

  In this case, in the step of separating the conductor layer and the mask, the conductive resin has a substantially conical shape on the conductor layer, and the contact portion between the conductive pillar and the conductor layer includes: The conductive pillar and the conductor layer are separated so as to have a shape that relieves stress concentration.

  The step of separating the conductor layer and the mask includes the step of separating the conductive resin from the conductive layer and having a contact portion between the conductive pillar and the conductive layer. The outer surface and the conductor layer surface are separated so as to have a smoothly continuous portion.

  Further, the step of separating the conductor layer and the mask includes the conductive resin having a substantially conical shape on the conductor layer, and a contact portion between the conductive pillar and the conductor layer of the conductive pillar. The outer surface and the surface of the conductor layer are separated so as to have an acute angle portion.

  In the filling step, in the step of separating the conductor layer and the mask, the conductive resin layer whose viscosity is adjusted so that a part of the conductive resin remains in the through hole of the mask is filled. It is characterized by that. The filling step is performed by screen printing.

  That is, the multilayer wiring board of the present invention employs via lands provided with stress dispersing means to disperse the stress acting on the via connection portion and prevent damage to the via lands and the connection between the via lands and the wiring circuit. .

  The stress distribution means included in the via land is, for example, a hole penetrating the via land. This hole is generally a hole having a smaller diameter than the maximum diameter of the conductive pillar. The shape of the hole only needs to reduce the stress, particularly the normal stress, acting on the via land and the wiring circuit connected to the via land when the conductive pillar is pressurized in the axial direction. For example, the shape may be any of a circle, an ellipse, a star, and a bowl, but a shape that can be drawn with a smooth continuous closed curve is preferable. This is because, if there is a notch (notch) portion, stress concentrates on that portion (notch effect), and the via land and the wiring layer are easily broken. The number of holes formed in the via land may be plural.

  The diameter of the hole formed in the via land may be set so that sufficient electrical connection is formed when the conductive pillar is pressed. For example, in the case where the conductive pillar is formed only on one via land, the diameter of the portion at the same height as the thickness of the second insulating layer from the bottom surface of the conductive pillar is about 0.3 mm, and the outer diameter of the via land is about 0.1 mm. In the case of 7 mm, the average diameter of the via land holes may be set to about 0.1 to 0.25 mm.

  The connection portion employing the conductive pillar of the multilayer wiring board according to the present invention can relieve the normal stress acting on the via land, in particular, by including the via land provided with such stress dispersion means. Further, although the conductive pillar penetrates into the cured first insulating layer, it cannot be penetrated easily, so that it also plastically deforms in the surface direction of the via land. Tangential stress is also relieved by plastic deformation in the surface direction of the via land of the conductive pillar. Therefore, the via land is not destroyed and its function can be maintained.

  It is preferable that the formation of the via land as a stress distribution means of the via land is simultaneously performed when the wiring layer to which the via land belongs is patterned into a predetermined wiring circuit. In other words, it is not necessary to increase the number of steps if they are formed simultaneously when patterning the wiring circuit. Of course, it is also possible to form holes in advance at predetermined positions of the conductor layer.

  Another feature of the multilayer wiring board according to the present invention is that the structure of the via connection portion employing the conductive pillar is such that the joint between the wiring layer and the conductive pillar does not peel off. In other words, the notch effect that acts on the connecting part between the conductive pillar and via land having the outer surface of a single hyperbolic surface (hyperboloid of one sheet) or hyperboloid of revolution of one sheet. It is formed so as to relax. By combining such a connection between the conductive pillar and the via land and the via land having the stress dispersing means as described above, the reliability of the multilayer wiring board is further improved.

  The present invention in which the structure of the via connection portion of the multilayer wiring board adopting the conductive pillar is prevented from peeling off at the joint portion between the wiring layer and the conductive pillar is based on the following knowledge obtained by the present inventor. It is a thing.

  In order to improve the reliability of the interlayer connection using the conductive pillar, the present inventor has analyzed the force acting on the connection portion using the conductive pillar.

  The conductive pillar formed through the insulating layer connects the first via land of the first wiring layer and the second via land of the second wiring layer separated by the insulating layer. For example, when solder is reflowed in the mounting process, a thermal load is applied to the interlayer connection portion having such a structure, and stress due to a difference in thermal expansion coefficient is generated.

For example, the thermal expansion coefficient of silver is 19.0 × 10 ⁻⁶ [° K ⁻¹ ], the thermal expansion coefficient of copper is 17.0 × 10 ⁻⁶ [° K ⁻¹ ], and the thermal expansion of aluminum is The coefficient is 23.0 × 10 ⁻⁶ [° K ⁻¹ ].
On the other hand, the thermal expansion coefficient of the insulating resin is, for example, FR-4 (NEMA standard), the thermal expansion coefficient in the longitudinal direction is α1 = 1.3 × 10 ⁻⁵ [° K ⁻¹ ], α2 = 1.5. × 10 ⁻⁶ [° K ⁻¹ ], the thermal expansion coefficient in the lateral direction is α1 = 1.8 × 10 ⁻⁵ [° K ⁻¹ ], α2 = 1.4 × 10 ⁻⁵ [° K ⁻¹ ], The thermal expansion coefficients in the thickness direction are α1 = 5.1 × 10 ⁻⁵ [° K ⁻¹ ] and α2 = 2.6 × 10 ⁻⁴ [° K ⁻¹ ]. Here, α1 is the coefficient of thermal expansion below the glass transition temperature Tg, and α2 is the coefficient of thermal expansion above the glass transition temperature Tg. The glass transition temperature of FR-4 is about 125 ° C.

  Here, the vertical direction is the direction of elongation of the glass fiber in the plane of the insulating resin layer, and the horizontal direction is the direction perpendicular to the direction of elongation of the glass fiber in the plane of the insulating resin layer.

  As described above, the thermal expansion coefficient of the resin material of the insulating layer is larger than the thermal expansion coefficient of the conductor metal constituting the main part of the wiring layer including the via land and the conductive pillar. In particular, the thermal expansion coefficient in the thickness direction of the insulating layer (the normal direction of the sheet), which is closely related to the reliability of the via connection, is much larger than the thermal expansion coefficient of a general conductor metal used for the wiring layer, 1 to 2 digits larger. Further, the thermal expansion coefficient in the thickness direction of this insulating resin layer is much higher at a temperature higher than the glass transition temperature Tg than at a temperature lower than the glass transition temperature Tg. Such a tendency is the same for insulating resin materials such as GPY, FR-5, CEM-3, CEM-1, FR-3, FR-2, XXXPC, FR-1, XPC, and G-10.

  That is, the coefficient of thermal expansion in the axial direction of the conductive pillar is not only when the material forming the conductive pillar is a metal, but also when it is a conductive resin composition in which conductive metal powder is dispersed in a binder resin. However, the thermal expansion coefficient is smaller than that of the resin material constituting the insulating layer as described above.

  Therefore, when a thermal load is applied to the via connection portion using the conductive pillar, the central direction of the conductive pillar (insulating layer) is caused by the difference between the thermal expansion coefficient of the conductive pillar and the thermal expansion coefficient of the insulating layer. A large stress is generated in parallel to the normal direction. Generally, this stress acts in the direction of peeling off the joint between the conductive pillar and the first via land and the second via land. That is, normal tension acts on the interface between the conductive pillar and the first via land, which is a plane perpendicular to the central axis of the conductive pillar, and on the interface between the conductive pillar and the second via land.

  In addition, the stress applied to the via connection portion employing the conductive pillar due to the thermal load is the largest at the point where the three portions of the insulating layer, the conductive pillar, and the wiring layer are in contact with each other. In other words, when a thermal load is applied to a via connection portion that employs a conductive pillar, the three parts of the insulating layer, the conductive pillar, and the wiring layer have different material properties such as thermal expansion coefficient and rigidity. The triple point where different materials come into contact (triple junction) is the point at which the stress acts most.

  The present inventor analyzed the stress generated in the via connection portion by simulation using the physical constants of the respective materials. As a result, the action of the stress acting to tear off the conductive pillar and the wiring layer is the wiring layer (via land). It was found that the portion where the conductive pillar is connected depends on the angle formed between the surface of the via land and the outer peripheral surface of the conductive pillar.

  That is, when the outer peripheral surface of the single-boloid curved surface of the conductive pillar and the surface of the via land are connected smoothly and continuously, the strength against the peeling is large, but the outer peripheral surface of the conductive pillar and the via land If there is a notch in this joint, stress concentrates on this part and the peel strength decreases. The sharper the notch, the greater the decrease in peel strength. It was also found that if the outer peripheral surface of the conductive pillar and the surface of the via land are smoothly connected as a whole, the peel strength can be maintained even if there is a microscopic notch. The connection portion between the outer peripheral surface of the conductive pillar and the via land surface draws a substantially circular closed curve, but the peel resistance is maximized when all portions on the closed curve are smoothly connected. In any case, if at least a part of this closed curve is connected smoothly, it is more resistant to delamination compared to the case where all parts of the closed curve are connected with a notch with a large stress concentration factor. The strength can be increased.

  The multilayer wiring board of the present invention has been made based on the above findings. Therefore, the multilayer wiring board of the present invention has a via connection portion that employs a conductive pillar, and at least a part of the connection portion between the outer peripheral surface of the conductive pillar and the via land surface is smoothly connected.

  In joining such conductive pillars and via lands, the tip of the conductive pillar is pressed once with, for example, a hard stainless steel plate and plastically deformed, and in this state, a metal foil or the like that becomes a wiring layer is pressure-bonded. Can be obtained. In addition, by setting the height at the time of formation of the conductive pillar appropriately with respect to the thickness of the insulating layer through which the conductive pillar penetrates, the conductive pillar and via land that further reduces the notch effect. Can be more easily achieved. Here, the notch effect refers to an effect that when an external force is applied to a solid with a notch, stress concentrates on the notch portion and deformation or breakage easily occurs. The multilayer wiring board of the present invention is formed by controlling the shape of the connecting portion between the conductive pillar and the conductor layer or via land so that the stress concentration factor becomes small.

  Here, as a wiring layer which comprises the multilayer wiring board of this invention, the metal material utilized as wiring materials including copper and aluminum can be used. A conductive resin can also be used. These conductor layers can be patterned by photoetching, or a conductive resin can be screen-printed to form a wiring layer having a wiring pattern having a predetermined pattern.

  The conductive pillar used for interlayer connection of the multilayer wiring board of the present invention can be formed of a conductive composition such as a conductive resin or a conductive paste. It is also possible to form with various metal materials.

  Here, examples of the conductive composition include a conductive resin in which a binder made of a resin material or the like is mixed or dispersed with conductive powders such as silver, gold, copper, and solder powder, and conductive fine particles as fillers. Can do. The conductive material can be used in combination of a plurality of metals and alloys.

  Examples of the resin of the binder component generally include thermoplastic resins such as polycarbonate resin, polysulfone resin, polyester resin, and phenoxy resin, and thermosetting resins such as phenol resin, polyimide resin, and epoxy resin. Besides these, for example, methyl methacrylate, diethyl methyl methacrylate, trimethylol propane triacrylate, diethylene glycol diethyl acrylate, methyl acrylate, ethyl acrylate, acrylic acid diethylene glycol ethoxylate, ε-caprolactone modified dipentaerythritol acrylate, etc. Examples thereof include ultraviolet curable resins such as acrylic acid esters and methacrylic acid esters, and electron beam irradiation curable resins. Moreover, you may make it use a solvent as needed.

  In order to form the conductive pillar using such a conductive resin, for example, the conductive resin may be screen-printed using a mask such as a metal mask. Adjusting the shape, opening diameter, and thickness of the metal mask, while forming the conductive pillar in the desired shape by adjusting the physical properties such as viscosity, thixotropy, surface tension, or mask surface tension of the conductive resin layer can do. In order to control the shape of the conductive pillar, it is preferable to set the viscosity of the conductive resin to be larger than the viscosity range of the conductive resin layer that is normally used. Further, a conductive resin material having thixotropy (thixotropy) may be used, and the thixotropy of the conductive resin may be adjusted and used by, for example, ultrasonic vibration.

  Thus, the conductive resin filled in the hole of the mask is deformed while being stretched between the conductor layer and the metal mask by separating the mask and the conductor layer in the normal direction of the conductor layer. A conductive pillar having a substantially conical shape is formed thereon. By such a method, it is possible to obtain a conductive pillar having a contact shape with a small contact angle θ with the surface of the conductor layer and having a joining shape that alleviates the notch effect.

  In order to form a conductive pillar having a higher aspect ratio, for example, the shape of the hole of the mask, the physical properties of the conductive resin, etc. may be adjusted. Printing may be repeated.

  The conductive pillars are not limited to screen printing, but may be formed by a stamping method in which a conductive paste is extruded into a hole in a mask. Also by such a method, a conductive pillar having a high aspect ratio can be formed from a conductive paste, a conductive resin, or the like, similarly to screen printing. Further, a conductive pillar made of metal may be formed by a plating method or the like.

  The conductive pillar may be formed on a conductor layer such as a copper foil, or may be formed on a patterned wiring layer. Further, it may be formed on an electrode of an electronic component such as a semiconductor element.

  Further, for example, conductive pillars are formed on a synthetic resin sheet having good peelability (for example, Teflon (registered trademark) resin such as polyvinylidene fluoride), and the conductive pillars are embedded in an insulating resin layer in a semi-cured state. The bottom surface may be crimped to a copper foil or a wiring layer.

  The conductive pillar is not limited to the interlayer connection of the multilayer wiring board, but can be formed, for example, on an electrode of an electronic component such as a semiconductor element and used to connect the electronic component and a wiring circuit on which the electronic component is mounted.

  For example, a general insulating resin material can be used as the insulating layer that electrically separates the wiring layers connected to the conductive pillars that constitute the multilayer wiring board of the present invention. The thickness may be set as necessary, and may be set to about 40 to 800 μm, for example. Further, the thickness of the insulating layer may be set together with the height of the conductive pillar.

  Here, examples of the thermoplastic resin material that can be used as the insulating layer include polycarbonate resin, polysulfone resin, thermoplastic polyimide resin, tetrafluoropolyethylene resin, hexafluoropolypropylene resin, and polyetheretherketone resin. . You may use what shape | molded these insulating resin materials in the sheet form.

Examples of the thermosetting resin material include epoxy resin, bismaleimide triazine resin, polyimide resin, phenol resin, polyester resin, melamine resin, butadiene rubber, and butyl rubber. Also, raw rubber sheets such as natural rubber, neoprene rubber, and silicone rubber can be used as the thermosetting resin material.
These insulating resin materials can be used alone or filled with an insulating inorganic or organic material. Further, it may be used in combination with a reinforcing material such as glass cloth, glass mat, synthetic fiber cloth, mat, or paper.

  The electronic component of the present invention is such that the conductive pillar having the above-mentioned substantially conical shape is formed on an electrode formed at a connection portion with an external circuit. In the electronic component package of the present invention, the electronic component is mounted by a conductive pillar.

  The contact portion between the conductive pillar and the electrode of the electronic component has a shape that relieves stress concentration acting between the conductive pillar and the electrode. The shape of the contact portion between the conductive pillar and the electrode may be, for example, a portion where the outer surface of the conductive pillar and the electrode surface are smoothly continuous. For example, you may make it have the part whose angle (theta) which the outer side surface of an electroconductive pillar and the electrode surface make is an acute angle.

  The electronic component of the present invention having such a connection shape with the external circuit is mounted on the multilayer wiring board in the same manner as the multilayering process of the multilayer wiring board of the present invention, and the electronic component package of the present invention is obtained. Can do.

  For example, first, a wiring layer having a predetermined pattern having via lands at positions corresponding to the electrodes of the electronic component and an electronic component having conductive pillars formed on the electrodes are arranged to face each other via an uncured insulating resin layer. . Then, by applying pressure from both sides, the conductive pillar penetrates the semi-cured insulating resin layer and is connected to the via land while being plastically deformed. The insulating resin layer is cured by heating at the same time.

  As described above, the electronic component and the electronic component package of the present invention have a great advantage that solder is not required for mounting. In addition, by mounting on the multilayer wiring board of the present invention, it is possible to route the lead wiring from the electronic component with a plurality of wiring layers, and the mounting density is remarkably improved. In this case, the electronic component mounted on the wiring board can be considered to be structurally equivalent to one of the outermost layers of the multilayer wiring board. Therefore, by connecting the via land of the wiring layer connected to the electrode of the electronic component via the conductive pillar to the via land of another wiring layer via the conductive pillar, the wiring of the lead wiring from the electronic component can be managed. It can be performed three-dimensionally with a plurality of wiring layers.

  FIG. 1 is a diagram schematically showing an example of the configuration of a multilayer wiring board according to the present invention, in which a wiring layer made of a conductor is laminated via an insulating layer.

In this multilayer wiring board 10, a first wiring layer 12 is formed on a first insulating layer 11a, and the first wiring layer 12 has a first via land 12a as a part of its circuit pattern. ing. The first and second insulating layer 11b is formed from the upper side of the wiring layer 12 toward the first insulating layers 11a, is on the second insulating layer 11b is formed second wiring layer 13 Yes.

  The second wiring layer has a second via land 13a at a position facing the via land 12a of the first wiring layer.

  Then, the first via land and the second via land arranged to face each other via the second insulating layer 11 b are connected by the conductive pillar 14. That is, the multilayer wiring board 10 performs interlayer connection of different wiring layers by the conductive pillars 14.

  As one of the features of the multilayer wiring board 10 of the present invention, the first via land 12a has means for dispersing stress applied in the axial direction of the conductive pillar 14, and in this case, the first via land 12a includes A through hole 12b is formed.

  FIG. 2 is a diagram schematically showing an example of the shape of the first via land, and shows a state in which the first via land is patterned on the first insulating layer 11a. The first via land 12a has one substantially circular through hole 12b, but the shape and number of the through holes 12b are not limited thereto. The shape of the through hole 12b may be, for example, an ellipse, a star, or a bowl other than a circle. In any case, it is preferable that the shape of the through hole 12b is a shape having no angular portion so that stress is not concentrated on a specific portion.

  The first via land 12a may include a plurality of through holes 12b. FIG. 3A is a diagram schematically showing another example of the shape of the first via land.

  4 is an enlarged view showing an interlayer connection portion of the multilayer wiring board of the present invention shown in FIG. The first via land 12 a and the second via land 13 b are via-connected by the conductive pillar 14. The conductive pillar 14 has a penetration portion 14b penetrating into the first insulating layer 11a in a region corresponding to the first via land 12a. Such an intrusion portion 14b is formed by connecting the first insulating layer and the second wiring layer in the axial direction of the conductive pillar, for example, with the conductive pillar sandwiched between the first via land and the second via land. It is formed by pressurizing. By adopting such a configuration, the multilayer wiring board of the present invention is formed on the first via land 12a even when a pressure load is applied in the interlayer connection direction of the multilayer wiring board, that is, the axial direction of the conductive pillar 14. A part of the conductive pillar penetrates from the through hole 14b, which is a stress dispersing means, to the first insulating layer side while being plastically deformed, thereby preventing the first via land 12a from being damaged. Therefore, the reliability of the interlayer connection of the multilayer wiring board is improved. Further, if the stress distribution means included in the first via land 12a is formed simultaneously with the patterning of the first wiring layer 12, it is not necessary to increase the number of steps. The rigidity of the conductive pillar is larger than that of the first insulating layer, but it is preferable to set it to such an extent that it deforms to some extent when penetrating.

FIG. 5 is a sectional view schematically showing another example of the configuration of the multilayer wiring board of the present invention. The multilayer wiring board 20 has four wiring layers made of conductors. Each wiring layer has a via land provided as a part of its circuit pattern, and a pair of via lands opposed to each other through an insulating layer 11b is connected by a conductive pillar 14, thereby providing an interlayer connection between the wiring layers. Is going.

A first wiring layer 12 having a first via land 12a is formed on both surfaces of the first insulating layer 11a . In the first via land 12a, a through hole 12b as exemplified in FIG. 3 is formed as a stress dispersing means. A second insulating layer 11b is formed on the first wiring layer 12, and a second wiring layer 13 having a second via land 13a is formed on the second insulating layer 11b. The first via land 12a and the second via land 13a are formed to face each other via the second insulating layer 11b insulating layer, and are connected to each other by the conductive pillar 14.

  Here, the wiring layers formed on both sides of the first insulating layer 11 a are described as the first wiring layers 12. In any case, as a matter of course, the circuit pattern of the first wiring layer 12 formed on both sides of the first insulating layer 11a may be different. Similarly, the circuit pattern of the second wiring layer 13 formed in the outer layer may be different. That is, each wiring layer has a via land at its interlayer connection, but its circuit pattern is formed as necessary. The same applies to cases where no particular mention is made.

  Next, an example of a method for manufacturing the multilayer wiring board 20 of the present invention illustrated in FIG. 5 will be described.

  6A, 6B, and 6C are views for explaining a manufacturing process of the multilayer wiring board of the present invention shown in FIG.

  First, a double-sided copper-clad laminate is prepared as a core base material in which a conductor layer is bonded to both sides of an insulating layer. Here, double-sided copper in which an electrolytic copper foil having a thickness of 35 μm to be patterned on the first wiring layer 12 is bonded to both surfaces of a 1.2-mm thick paper-phenolic resin-based insulating substrate that is the first insulating layer 11a. A tension laminate (trade name, paper phenol resin copper clad laminate R-8705E, manufactured by Matsushita Electric Works) was prepared.

Next, the copper foil as the first wiring layer 12 attached to the core substrate is patterned into a predetermined wiring circuit by, for example, a photoetching process. Here, a resist having a predetermined pattern is formed on the copper foil by screen printing, and the copper foil is selectively removed by etching using the ferric chloride solution as an etching solution, and then the resist is removed. The first wiring layer 12 having a predetermined circuit pattern was formed (FIG. 6A). At this time, the first via land 12 a was also formed as a part of the circuit pattern of the first wiring layer 12. The first via land 12a was formed in a substantially circular shape having a diameter of about 0.7 mm, and a hole 12b having a diameter of about 0.2 mm was formed at the center thereof.

  Here, both the wiring circuits formed on both sides of the first insulating layer 11a are described as the first wiring circuit, but the circuit pattern of the first wiring layer on both sides of the first insulating layer is as follows. Different patterns were formed.

  Next, the conductive pillar 14 having a substantially conical shape was formed on the first via land 12 a of the first wiring circuit 12. The conductive pillar 14 was formed by arranging a metal mask having pits at positions corresponding to the first via lands 12a and screen printing a conductive resin. The metal mask used was made of stainless steel having a thickness of about 300 μm with holes having a diameter of about 0.3 mm. In this example, a phenol resin conductive paste using silver powder as a filler is used as the conductive resin. However, a filler made of a conductor and a binder resin may be selected and used as necessary. After drying the printed conductive paste, the process of printing and drying at the same position using the same mask was repeated three times. Further, the conductive pillar 14 having a substantially conical shape and having a height of about 0.3 mm was formed on the first via land 12a (FIG. 6B). The shape of the conductive pillar 14 can be formed into a desired shape by adjusting various physical properties such as the pit diameter and thickness of the mask to be used or the viscosity of the conductive resin to be printed, and the number of times of printing, for example. .

After forming the conductive pillar 14, the second insulating layer 11b and the second wiring layer 13 are laminated on both sides of the core material. Here, for example, an epoxy resin sheet (B stage) having a thickness of about 70 μm is used as the second insulating layer 11b, and an electrolytic copper foil having a thickness of about 35 μm is used as the second wiring layer 13 (unpatterned). Using.

  The second insulating layer 11b and the second wiring layer 13 are arranged on both sides of the core base so that the second wiring layer 13 faces the first wiring layer 12 via the second insulating layer 11b. It arrange | positions (FIG. 6C), and it pressurizes from the outer side of the 2nd wiring layer 13 between the press plates, and heating. By heating and pressing, the second insulating layer 11b is cured and becomes a C stage. At this time, the substantially conical conductive pillar 14 penetrates the second insulating layer 11b in a semi-cured state and is connected to the opposing second via land 13a. Curing of the second insulating layer 11b starts after the core base material and the second wiring layer 13 are in contact with both sides of the second insulating layer 11b. The conductive pillar 14 can penetrate the second insulating layer 11b relatively easily.

  Here, as a backing plate used at the time of pressing, for example, a metal plate such as a stainless steel plate or a brass plate or a metal plate with little deformation and deformation, a polyimide resin plate (sheet), a polytetrafluoroethylene resin plate (resin sheet) It is preferable to use a heat-resistant resin plate with little change or deformation.

  In addition, when pressing is performed in a state where the insulating layer is heated and softened, the conductive pillar tip easily penetrates the insulating layer.

Next, the second wiring layer 13 is patterned to form a predetermined circuit. Here, a resist of a predetermined pattern is formed on the copper foil as the second wiring layer 13 by screen printing, and the copper foil is selectively removed by etching using the resist as a mask and a ferric chloride solution as an etchant. Then, the resist was removed to form a predetermined circuit pattern having a second via land. At this time, the second via land 13a was simultaneously formed as a portion of the wiring circuit pattern.
Through the steps as described above, a four-layer multilayer wiring board in which each wiring layer has 1000 via connections with conductive pillars was formed (see FIG. 5).

  The connection resistance of the wiring circuit of the multilayer wiring board manufactured in this way was about 2.1Ω. This connection resistance corresponds to the resistance when 1000 conductive pillars are connected in series via a wiring made of copper foil, and considering the pattern resistance of the copper foil, the connection resistance value per conductive pillar is The average was about 1 mΩ. Further, the connection resistance of the conductive pillar and the pattern resistance of the copper foil were less varied.

  Further, when this multilayer wiring board was cut along a plane parallel to the axial direction of the conductive pillar and the state of the interlayer connection portion was observed, as shown schematically in FIG. The via land and the second via land were closely connected, and the bonding state was also good. The second via land 12a is slightly recessed toward the first insulating layer, but no crack was observed. Further, a part of the conductive pillar 14 had a portion penetrating to the first insulating layer 11a side through a hole 12b formed in the second via land 12a.

  For comparison, a multilayer wiring having the same configuration as that of FIG. 5 was manufactured under the same conditions except that the stress distribution means was not formed on the first via land 12a. The connection resistance of the wiring pattern of the four-layer multilayer wiring board having 1000 via connections by this conductive pillar is 5.1Ω, which is about 3Ω larger than the connection resistance of the multilayer wiring board of the present invention illustrated in FIG. It was. In addition, when a multilayer wiring board not provided with stress distribution means was cut on the first via land and the state of via connection was observed, the first via land 12a portion was large and recessed toward the first insulating layer 11a. Cracks occurred in the first via land 12a.

As described above, the multilayer wiring board of the present invention can disperse the stress (pressure) applied to the via land in the axial direction of the conductive pillar by including the via land including the stress dispersing means. Further, the stress (tangential stress) applied in the tangential direction of the via land is relieved mainly by plastic deformation of the conductive pillar. Therefore, the wiring circuit including the via land is hardly damaged, and a highly reliable interlayer connection can be established. In addition, since interlayer connection by through holes can be suppressed to a necessary minimum, high-density mounting can be supported.
In addition, according to the method for manufacturing a multilayer wiring board of the present invention, while maintaining high productivity of the method for manufacturing a multilayer wiring board using conductive pillars, it is possible to suppress the occurrence of poor connection and further improve productivity. it can.

  FIG. 7A, FIG. 7B, FIG. 7C, and FIG. 7D are diagrams for explaining another example of the method for manufacturing a multilayer wiring board according to the present invention.

First, a double-sided copper-clad laminate is prepared as a core base material in which a conductor layer is bonded to both sides of an insulating layer. Here, a double-sided copper-clad laminate (trade name, paper) in which a 35-μm-thick electrolytic copper foil patterned on the first wiring layer 12 is laminated on both sides of a 1.2 mm thick paper-phenolic resin-based insulating substrate. Phenol resin copper clad laminate R-8705E (manufactured by Matsushita Electric Works) was prepared.
Next, the copper foil attached to the core substrate is patterned into a predetermined wiring circuit by, for example, a photoetching process. Here, a resist having a predetermined pattern is formed on the copper foil by screen printing, and the copper foil is selectively removed by etching using the ferric chloride solution as an etching solution, and then the resist is removed. The first wiring layer 12 having a predetermined circuit pattern was formed (FIG. 7A). At this time, the first via land was also formed as a part of the wiring circuit pattern of the first wiring layer 12. The first via land 12a was formed in a substantially circular shape having a diameter of about 0.7 mm, and a hole 12b having a diameter of about 0.2 mm was formed at the center thereof.
Here, both the wiring circuits formed on both sides of the first insulating layer 11a are described as the first wiring circuit, but the circuit pattern of the first wiring layer on both sides of the first insulating layer is as follows. Different patterns were formed.

  On the other hand, an electrolytic copper foil having a thickness of about 35 μm was prepared as the second wiring layer 13, and the conductive pillar 14 having a substantially conical shape was formed on the electrolytic copper foil.

The conductive pillar 14 was formed at a position corresponding to the first via land 12 a formed in the first wiring layer 12 when the second wiring layer 13 was overlapped with the first wiring layer 12.

  The conductive pillar 14 was formed by arranging a metal mask having pits and screen printing a conductive resin. The metal mask used was made of stainless steel having a thickness of about 300 μm with holes having a diameter of about 0.3 mm. In this example, a conductive paste of phenol resin using silver powder as a filler was used as the conductive resin. After drying the printed conductive paste, the process of printing and drying at the same position using the same mask was repeated three times. Further heating was performed to form a conductive pillar 14 having a substantially conical shape and a height of about 0.3 mm on the first via land 12a (FIG. 7B).

  As shown in FIG. 7C, after preparing a core material in which the first wiring layer 12 is formed on both surfaces of the first insulating layer 11a and a second wiring layer (unpatterned) in which the conductive pillar 14 is formed, respectively. The second wiring layer is disposed on both sides of the core material via the second insulating layer 11b. At this time, the first via land 12a and the conductive pillar 14 are arranged so as to face each other.

  As the second insulating layer 11b, a B-stage prepreg having a thickness of about 100 μm in which a glass cloth was impregnated with an epoxy resin was used.

  Then, the whole is pressed from the outside of the second wiring layer 13 while being sandwiched between press plates and heated. The second insulating layer 11b is cured to the C stage by heating and pressing.

  At this time, the substantially conical conductive pillar 14 penetrates the second insulating layer 11b in a semi-cured state and is connected to the opposing first via land 12a. Curing of the second insulating layer 11b starts after the core base material and the second wiring layer 13 are in contact with both sides of the second insulating layer 11b. The conductive pillar 14 can penetrate the second insulating layer 11b relatively easily.

  The leading end portion of the conductive pillar 14 is inserted into a through hole 12b which is a stress distribution means formed in the first via land 12a, and is in close contact with the first via land 12a while being plastically deformed. Here, although the conductive pillar 14 penetrates into the first insulating layer 11a while being plastically deformed, it is not hard enough to penetrate the first insulating layer 11a, so that the first via land is in close contact without being damaged. be able to.

Next, the second wiring layer is patterned to form a predetermined circuit. Here, a resist of a predetermined pattern is formed on the copper foil as the second wiring layer 13 by screen printing, and the copper foil is selectively removed by etching using the resist as a mask and a ferric chloride solution as an etchant. Then, the resist was removed to form a predetermined circuit pattern having a second via land.
Through the steps as described above, a four-layer multilayer wiring board in which each wiring layer has 1000 via connections with conductive pillars was formed (FIG. 7D).

  The connection resistance of the wiring circuit of the multilayer wiring board manufactured in this way was about 2.1Ω. This connection resistance corresponds to the resistance when 1000 conductive pillars are connected in series via a wiring made of copper foil, and considering the pattern resistance of the copper foil, the connection resistance value per conductive pillar is The average was about 1 mΩ. Further, the connection resistance of the conductive pillar and the pattern resistance of the copper foil were less varied.

  FIG. 8 is a view showing a state in which the state of the interlayer connection portion is observed by cutting the multilayer wiring board of FIG. 7D along a plane parallel to the axial direction of the conductive pillar. A part of the conductive pillar 14 has a portion 14c penetrating to the first insulating layer 11a through the hole 12b formed in the first via land 12a. However, the conductive pillar 14, the first via land, and the first via land The two via lands were closely connected and the bonding state was good.

  The second via land 12a is slightly recessed toward the first insulating layer, but no crack was observed. This is because the conductive bumps 14 penetrate into the first insulating layer 11a through the holes 12b provided in the first via land 12a and are plastically deformed along the first via land 12a.

  For comparison, a multilayer wiring having the same configuration as that of FIG. 7D was manufactured under the same conditions except that the stress distribution means was not formed on the first via land 12a. The connection resistance of the wiring pattern of the four-layer multilayer wiring board having 1000 via connections by this conductive pillar is 5.1Ω, which is about 3Ω larger than the connection resistance of the multilayer wiring board of the present invention illustrated in FIG. 7D. It was. In addition, when a multilayer wiring board not provided with stress distribution means was cut on the first via land and the state of via connection was observed, the first via land 12a portion was large and recessed toward the first insulating layer 11a. A crack occurred in the first via land 12a (see FIG. 27).

  Thus, the multilayer wiring board of the present invention can disperse the stress applied in the axial direction of the conductive pillar by including the via land including the stress dispersing means. Therefore, the wiring circuit including the via land is hardly damaged, and a highly reliable interlayer connection can be established. In addition, since interlayer connection by through holes can be suppressed to a necessary minimum, high-density mounting can be supported.

  In addition, according to the method for manufacturing a multilayer wiring board of the present invention, while maintaining high productivity of the method for manufacturing a multilayer wiring board using conductive pillars, it is possible to suppress the occurrence of poor connection and further improve productivity. it can.

  The present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the invention. For example, the wiring layer may be formed of a conductive composition, and the conductive pillar may be made of metal. Furthermore, the insulating layer is not limited to an epoxy resin, and a thermosetting resin, a thermoplastic resin, or the like can be selected and used as necessary.

  FIG. 9A is a diagram schematically showing a cross-sectional structure of an interlayer connection portion of the multilayer wiring board of the present invention. 9B is a diagram schematically showing the structure of the interlayer connection portion shown in FIG. 9A as seen through from the axial direction of the conductive pillar, and FIG. 9C is a diagram schematically showing the structure of the interlayer connection portion shown in FIG. 9A. It is a perspective view.

  This multilayer wiring board is formed on the insulating film 21, the first via land 22 formed on the first surface of the insulating film 21, and the second surface of the insulating film 21. 22 and a second via land 23 formed in a region opposite to the region 22.

  Here, the first via land 22 is formed as a part of the circuit pattern 22b of the first wiring layer, and the second via land 23 is formed as a part of the circuit pattern 23b of the second wiring layer (not shown). Yes.

  The interlayer connection between the first wiring layer and the second wiring layer is made of a conductor formed so as to penetrate the insulating film 21 so as to connect the first via land 22 and the second via land 23. Established by the conductive pillar 24. The shape of the portion where the outer surface of the conductive pillar 24 is in contact with the surfaces of the first via land 22 and the second via land 23 is the same as the shape of the conductive pillar 24 and the first via land 22 or the second via land 23. It is formed so that stress concentration does not occur at the solid-solid interface of the connecting portion.

  In order to prevent stress concentration from occurring at the interface between the connecting portions of the conductive pillar 24 and the first via land 22 and the second via land 23, for example, the outer surface of the conductive pillar 24 and the first via land 22 and The contact angle formed with the surface of the second via land 23 on the insulating film 21 side may be set so that the stress concentration factor is as small as possible.

  10A, 10B, and 10C are diagrams schematically showing an example of the shape of the connection portion between the conductive pillar 24 and the first via land 22 (or the second via land 23) included in the multilayer wiring board of the present invention. It is. 11A and 11B are examples of an undesirable shape of the shape of the connection portion between the conductive pillar 24 and the first via land 22 (or the second via land 23) shown for comparison.

  As a result of analyzing the stress generated in the via connection portion employing the conductive pillar by simulation using the physical constants of each material, the present inventor has found that the stress acts to peel off the conductive pillar 24 and the wiring layer or via land. It was found that the portion where the wiring layer (or via land) and the conductive pillar 24 are connected depends on the angle formed between the surface of the via land and the outer peripheral surface of the conductive pillar. Therefore, in the present invention, the contact angle θ between the outer peripheral surface of the conductive pillar having a substantially single hyperboloid shape and the via land surface is controlled so as to reduce the stress concentration factor.

  For example, if the contact angle θ is set small so that the outer surface of the conductive pillar 24 and the surface of the via land 22 are smoothly continuous, the bonding strength and the peel strength can be improved. For example, the via connection having the shape shown in FIG. 10B has a higher strength against peeling than the via connection having the shape shown in FIG. 10C. Similarly, the via connection having the shape shown in FIG. 10A has higher strength against peeling than the via connection having the shape shown in FIG. 10B. In any case, even with the via connection having the shape shown in FIG. 10C, the peel strength is much higher than the via connection having the shape shown in FIGS. 11A and 11B.

  That is, when the outer peripheral surface of the conductive pillar and the surface of the via land are connected smoothly and continuously, the strength against the peeling is high, but the notch is formed at the joint between the outer peripheral surface of the conductive pillar and the via land. If there is, stress concentrates on this part and the peel strength decreases, and the sharper the notch, the greater the decrease in peel strength.

  It was also found that if the outer peripheral surface of the conductive pillar and the surface of the via land are smoothly connected as a whole, the peel strength can be maintained even if there is a microscopic notch. 12A and 12B are diagrams schematically illustrating another example of the shape of the connection portion between the conductive pillar and the first via land or the second via land. The connection portion between the outer peripheral surface of the conductive pillar and the via land surface draws a closed curve, for example, a circle. When all the portions on the closed curve are smoothly connected, the peel resistance is maximized. In any case, if at least a part of this closed curve is connected smoothly, it is more resistant to delamination compared to the case where all parts of the closed curve are connected with a notch with a large stress concentration factor. The strength can be increased. For example, the shape shown in FIGS. 12A and 12B has a notch in the microscopic (contact angle ψ), but the outer surface of the conductive pillar 24 and the surface of the via land as a whole are smoothly continuous. Even when a connection is made (contact angle θ) and a thermal load is applied in a mounting process such as solder reflow, via connection between wiring layers can be stably maintained.

FIG. 13A is a diagram schematically illustrating an example of the structure of the multilayer wiring board of the present invention, and FIG. 13B is a diagram schematically illustrating a state when a thermal load is applied to the multilayer wiring substrate of FIG. 13A. This multilayer wiring board has 3000 via connections that employ conductive pillars 24.
The interlayer connection portion of the multilayer wiring board of FIG. 13A has the same structure as the multilayer wiring board of the present invention shown in FIG. 9A. The conductive pillar 24 formed through the insulating layer 21 connects the first via land 23 of the first wiring layer and the second via land 24 of the second wiring layer separated by the insulating layer 21. ing. The joints between the conductive pillar 24 and the first via land 22 and the second via land 23 both have a shape that relieves stress applied to the triple point 25. In this example, the angle formed by the outer peripheral surface of the conductive pillar 24 and the surface of the first via land 22 and the angle formed by the outer peripheral surface of the conductive pillar 24 and the surface of the second via land 23 are both formed at acute angles. Has been.

  When various electronic components are mounted on such a multilayer wiring board, particularly when solder is reflowed, a heat load is applied to the interlayer connection portion, resulting in a stress caused by a difference in thermal expansion coefficient. Stress will be concentrated on.

  The multilayer wiring board of FIG. 13A uses an FR-4 standard insulating resin base material as the insulating layer 21, copper foil as the wiring layer, and silver fine particles as a filler dispersed in the binder resin as the conductive pillar. Conductive resin is used.

The thermal expansion coefficient α1 in the normal direction of the insulating layer 21 at a temperature lower than the glass transition temperature Tg (about 125 ° C.) of FR-4 is 5.1 × 10 ⁻⁵ [° K ⁻¹ ]. The thermal expansion coefficient α2 in the thickness direction of FR-4 at a temperature higher than Tg is 2.6 × 10 ⁻⁴ [° K ⁻¹ ], which is much larger than α1.

On the other hand, the thermal expansion coefficient of silver constituting the main part of the conductive pillar is 17.0 × 10 ⁻⁶ [° K ⁻¹ ]. Therefore, when a thermal load is applied to the multilayer wiring board of FIG. 13A, the insulating layer 21 expands more than the conductive pillar 24. In particular, at a temperature higher than the glass transition temperature Tg, the thermal expansion coefficient of the insulating layer 21 is 15 times or more larger than the thermal expansion coefficient of silver. Since the eutectic temperature of a Pb—Sn eutectic solder alloy generally used as solder is 183 ° C., a thermal load of about 220 to 240 ° C. is also applied to the multilayer substrate when the solder is reflowed ( FIG. 13B).

  Therefore, a large stress is generated in the axial direction of the conductive pillar 24 (parallel to the normal direction of the insulating layer) due to the difference between the thermal expansion coefficient of the conductive pillar 24 and the thermal expansion coefficient of the insulating layer 21. . This stress acts as a tension on the junction between the conductive pillar 24 and the first via land 22 and the second via land 23. Such stress is greatest at the triple point where the three portions of the insulating layer 21, the conductive pillar 24, and the via lands 22 and 23 are in contact with each other.

  The multilayer wiring board shown in FIG. 13A was heated to 240 ° C. for 20 seconds to examine the interlayer connection. As a result, all the interlayer connection portions were kept conductive and the resistance value was maintained.

As the first via land 22 and the second via land 23, for example, a means for releasing the pressure applied between the conductive pillar and the via land as illustrated in FIG. 2 may be provided. For example, if the through hole 12b is formed in the first via land 22 or the second via land 23, the via connection is prevented from being damaged regardless of whether a pressure is applied between the conductive pillar and the via land or a tension is applied. The connection function can be stably maintained.

  9 to 13 show the interlayer connection of wiring layers formed on both surfaces of one insulating layer, but the above-described via connection is also applied to a multilayer wiring board having three or more wiring layers in the same manner. can do.

Next, a method for manufacturing a multilayer wiring board of the present invention having a shape that relieves stress applied to the joint between the conductive pillar, the first via land, and the second via land will be described.
FIG. 14A, FIG. 14B, FIG. 14C, FIG. 14D, FIG. 14E, FIG. 14F, and FIG. 14G are views for explaining an example of the method for manufacturing a multilayer wiring board according to the present invention.

  An electrolytic copper foil having a thickness of about 35 μm serving as the first wiring layer 22 was prepared, and conductive pillars 24 were formed at predetermined positions on the copper foil. The conductive pillar 24 is formed by screen-printing a conductive paste using silver fine particles (average particle size of about 10 μm) as a conductive filler, and has a substantially conical shape with a bottom diameter of about 250 μm and a height of about 250 μm. (FIG. 14A).

  After the conductive pillar 24 is dried, a thermosetting prepreg (trade name, glass epoxy prepreg HE, manufactured by Toshiba Chemical Co., Ltd.) having a thickness of about 115 μm in which a glass cloth is impregnated with an epoxy resin is prepared as the insulating layer 21. The first wiring layer 22 was laminated on the surface on which the conductive pillars 24 were formed. At this time, the insulating layer 21 of the B stage is heated to about 100 ° C. (<Tg), and the conductive pillar 24 is insulated by pressing the flexible pillar 26 so that the conductive pillar 24 does not deform. Layer 21 was penetrated (FIG. 14B). At this time, the insulating layer 21 is not completely cured and maintains a semi-cure state. This corresponds to the prefabricated material of the multilayer wiring board of the present invention. Here, the prefabricated material means a prefabricated material that constitutes the multilayer wiring board, and indicates, for example, the state shown in FIG. 14B or the state shown in FIG. 14C. By using such a prefabricated material for the multilayer wiring board of the present invention, the multilayer wiring board of the present invention can be easily configured. For example, by laminating the prefabricated material of FIG. 14C on both sides of a double-sided laminated board, the multilayer wiring board of the present invention having four wiring layers can be configured.

  Thereafter, the tip of the conductive pillar 24 protruding from the insulating layer 21 was pressed and deformed in the central axis direction of the conductive pillar 24. Here, a hard stainless steel plate having a thickness of about 1 mm was placed on the conductive pillar 24, and flat plate pressing was performed at room temperature to plastically deform the tip of the conductive pillar so as to collapse (FIG. 14C). At this time, the crushed head of the conductive pillar 24 was slightly raised and exposed from the surface of the insulating layer 21. Even in this state, it can be used as a prefabricated material for a multilayer wiring board.

  Next, an electrolytic copper foil having a thickness of about 35 μm serving as a second wiring layer was disposed on the surface of the insulating layer 21 where the tip of the conductive pillar 24 was exposed. This laminated body is pressed while being heated from the outside of the first wiring layer 22 and the second wiring layer 23, and the semi-cured insulating layer 21 is completely cured by heating, and the conductive pillar 24 and the second wiring layer are cured. The layers were crimped (FIG. 14D). Through the steps so far, a double-sided copper-clad plate in which the first wiring layer 22 and the second wiring layer 23 are interlayer-connected through the insulating layer 21 by the conductive pillar 24 is obtained. The conductive pillar 24 is formed by controlling its shape. First, the head protruding from the insulating layer 21 is crushed, and then is crimped to the second wiring layer 23 to be plastically deformed in multiple stages. In addition, it is possible to obtain a shape that does not concentrate stress at the joint between the conductive pillar 24 and the wiring layer.

  Next, the first wiring layer 22 and the second wiring layer 23 were patterned into a predetermined wiring circuit including the first via land 22a and the second via land 22b (FIG. 14E). In this manufacturing example, a general etching resist ink (PSR-4000H, manufactured by Taiyo Ink KK) is screen-printed to form a predetermined wiring circuit pattern, and a mask is formed. The resist mask was peeled off. When a multilayer wiring board having more wiring layers is manufactured using the two-layer wiring board having the first wiring layer 22 and the second wiring layer 23 shown in FIG. 14E as a core base material, Simultaneously with the patterning, it is preferable to form, for example, stress release means as shown in FIG. 2 on the first via land 22a and the second via land 23a (FIG. 14F). By forming the stress release means, the via land and the wiring circuit are prevented from being damaged when the interlayer connection with the outer wiring layer is formed, and the reliability of the multilayer wiring board can be improved.

  In the state shown in FIG. 14E, when the continuity test of the via connection portion was performed by a conventional method, no abnormality was found in the interlayer connection having all (3000) conductive pillars 24. No abnormality was found in the resistance value.

  Next, an example will be described in which a multilayer wiring board in the state shown in FIG. 14E is used as a core base material and a four-layer multilayer wiring board having third wiring layers 27a and 27b on both sides is manufactured.

  In the same manner as described above, a prefabricated material in which the third wiring layers 27a and 27b in which the conductive pillars 24 are formed at predetermined positions and the insulating layer 21b are laminated as shown in FIG. 14C is prepared. Here, a prepreg made of the same material as that of the insulating layer 21 is used for the insulating layer 21b. However, if necessary, an insulating material of a different material can be used.

  Then, using the double-sided wiring board shown in FIG. 14E as a core base material, the third wiring layers 27a and 27b and the insulating layer 21b are arranged on both sides thereof. At this time, the via connection portions of the first wiring layer 22 and the second wiring layer 23 and the third wiring layers 27a and 27b are arranged to face each other (FIG. 14G).

  Next, this laminated body is pressed while being heated from the outside of the third wiring layers 27a and 27b to completely cure the semi-cured insulating layer 21b by heating, and the conductive pillar 24 and the third wiring layer 27a. 27b was crimped.

  Then, by patterning the third wiring layers 27a and 27b into a predetermined wiring circuit, the first wiring layer 22 and the second wiring layer 23 and the third wiring layers 27a and 27b are insulated by the conductive pillar 24. A multilayer wiring board having four wiring layers interconnected via the layer 21b is obtained (FIG. 14H).

  The method for producing the multilayer wiring board of the present invention having such a bonded shape having a high peel strength will be described in more detail. First, the bonding between the first wiring layer 22 and the conductive pillar 24 will be described, and then the bonding shape between the second wiring layer and the conductive pillar 24 will be described.

In the example of FIG. 14, the bonding shape between the first wiring layer 22 and the conductive pillar 24 is substantially determined when the conductive pillar is formed on the first wiring layer 22 such as a copper foil. For example, when a conductive pillar is formed by screen printing a conductive resin or conductive paste using a mask such as a metal mask, the shape, opening diameter, and thickness of the metal mask are adjusted, The conductive pillar can be formed into a desired shape by adjusting physical property values such as the viscosity, thixotropy, surface tension, or mask surface tension of the conductive resin layer.
Here, a method for forming the conductive pillar will be described. Here, a method of forming conductive pillars will be described taking a multilayer wiring board as an example.

  FIG. 15A, FIG. 15B, FIG. 15C, FIG. 15D, and FIG. 15E are diagrams for explaining an example of the formation process of the conductive pillar 24.

  A metal mask 31 in which a through hole (pit) 31 a having a substantially cylindrical shape is formed on the first wiring layer 22 is disposed. Here, the metal mask was made of stainless steel having a thickness of 300 μm, and the diameter of the through hole 31a was set to 3.00 μm.

  Then, the conductive resin 33 is filled into the hole 31a of the metal mask 31 through the screen 32 with the squeegee 34 (FIGS. 15A and 15B). FIG. 15C is a diagram for explaining an example of screen printing.

  Here, as the conductive resin 33, silver fine particles kneaded with an epoxy binder resin and a solvent are further mixed. In general, the conductive resin 33 is generally used by adjusting the viscosity to about several hundred poise. However, in the present invention, the viscosity is adjusted to be much larger than this in order to control the shape of the conductive pillar. Using. If necessary, the thixotropy of the conductive resin 33 may be adjusted by, for example, ultrasonic vibration (when the conductive resin 33 has thixotropy).

  In this way, when the conductive resin 33 with adjusted viscosity is filled in the hole 31a of the metal mask 31, the metal mask 31 and the first wiring layer 22 are separated from each other in the normal direction of the first wiring layer 22 ( FIG. 15D). At this time, the conductive resin 33 is deformed while being stretched between the first wiring layer 22 and the metal mask 31, and the conductive pillar 24 having a substantially conical shape is formed on the first wiring layer 22 ( 15E). The diameter r of the bottom surface of the formed conductive pillar 24 having a substantially conical shape was about 300 μm, and the height h was about 250 μm. A part of the conductive resin 33 was attached to the hole 31 a of the metal mask 31. By such a method, the contact angle θ between the conductive pillar 24 and the surface of the first wiring layer 22 is small, and a joining shape that reduces the notch effect can be obtained. Further, when it is desired to form the conductive pillar 24 having a high aspect ratio (height (h) / bottom diameter (r)), for example, the shape of the through hole 31a and the physical properties of the conductive resin 33 are adjusted. Alternatively, the metal mask 31 may be arranged at the same position and the screen printing may be repeated.

  The conductive pillars 24 are not limited to screen printing, but may be formed by a stamping method in which a conductive paste is extruded into a hole in the mask. Also by such a method, the conductive pillar 24 having a high aspect ratio can be formed from a conductive paste, a conductive resin, or the like, similarly to screen printing. Further, a conductive pillar made of metal may be formed by a plating method or the like. In either case, the height and diameter of the conductive pillar 24 may be set according to the configuration of the via connection portion to be formed, as will be described later.

Although the above-described method for forming the conductive pillar has been described by taking the interlayer connection of the multilayer wiring board as an example, it can be formed on the electrode of an electronic component such as a semiconductor element by the same method.
Next, a method for controlling the joint shape between the conductive pillar 24 formed in this way and the second wiring layer 23 will be described.

  FIG. 16 is a diagram schematically showing the relationship between the conductive pillar 24 and the insulating layer 21 and corresponds to the state of FIG. The inventor has determined that the bonding shape of the conductive pillar 24 and the second wiring layer 23 is the ratio of the mass of the portion embedded in the insulating layer 21 of the conductive pillar 24 and the portion protruding from the surface of the insulating layer 21. It has been found through experiments that it is related to physical properties such as plastic deformability of the conductive pillar 24.

  For example, when electrolytic copper foil is used as the wiring layer and silver fine particles are used as the conductor filler constituting the main part of the conductive pillar 24, the conductive pillar 24 has a thickness d of the insulating layer 21. By setting the height h to be 1 to 5 times larger, more preferably 1.6 to 4 times larger, the notch effect with a small contact angle θ between the conductive pillar 24 and the surface of the second wiring layer 23 is mitigated. It was found that such a joining shape can be obtained.

  Here, the reason why the height h of the conductive pillar 24 is set larger than the thickness d of the insulating layer 21 is based on the following reason. For example, when the insulating layer 21 is a thermosetting resin, the thickness d shrinks by about 0 to 30% when it is cured from the B stage to the C stage, and when it is a thermoplastic resin, it is solidified from a softened state. As a result, the thickness d shrinks by about 0 to 15%. Therefore, if the height h of the conductive pillar 24 exceeds 1.2 times the thickness of the insulating layer 21, at least the tip portion protrudes from the surface of the insulating layer 21. This protruding portion is a portion that is plastically deformed to form a joint shape when being crimped to the second wiring layer 23. If the height h of the conductive pillar 24 is 1.2 to 5 times, preferably about 1.6 to 4 times the thickness d of the insulating layer 21, the second wiring layer 23 is not destroyed. In addition, it is possible to obtain a joint shape having a small contact angle θ and relaxing the notch effect.

  The above description is applied to the case where the conductive pillar 24 is formed in either one of the two wiring layers connected between the layers.

  For example, when forming an interlayer connection by making the conductive pillars 24 face each other from both sides of the insulating layer 21 in the semi-cured state, the height h of the conductive pillar 24 is set to 0. It is preferable to set the height to about 8 to 2 times.

  FIG. 17 is a view showing a state in which the first wiring layer 22 and the second wiring layer 23 are arranged with the conductive pillars 24 facing each other from both sides of the insulating layer 21, and FIG. It is a figure which shows typically the structure of the interlayer connection part of the multilayer wiring board of this invention formed by making the conductive pillar 24 oppose and penetrate.

  On the other hand, in the case where the conductive pillar 24 is formed in one of the two wiring layers connected between the layers as described above, and the conductive pillar 24 is penetrated from one side of the insulating layer 21, the interlayer connection is formed. It is preferable to set the height h of the conductive pillar 24 to a height of about 1.6 to 4 times the thickness d of the insulating layer 21.

  The multilayer wiring board of the present invention produced in Example 8 was cut, and the cross-sectional shape of the conductive pillar 24, the conductive pillar 24 and the wiring layers 22, 23, 27a, b, and the contact angle were observed. Each of the cross-sectional shapes by a plane parallel to the axis of the conductive pillar 24 had a drum shape whose outer peripheral surface was substantially hyperboloid. Further, the contact angle θ was distributed over an angle range of 30 to 80 °.

  Five four-layer multilayer wiring boards having 9000 conductive pillars 24 manufactured as described above were prepared, and these multilayer wiring boards were immersed in a solder bath at 288 ° C. for 20 seconds and then pulled up to reduce the wiring resistance. Changes were tested and evaluated. The measured wiring resistance value was within the measurement error range before and after the test, and there was no substantial change. Even when the same test was repeated five more times, no significant change in resistance value was observed.

  Further, five four-layer multilayer wiring boards having 9000 conductive pillars 24 manufactured as described above were prepared and subjected to a thermal cycle test. In the thermal cycle test, a cycle in which the multilayer wiring board was allowed to stand at −65 ° C. and + 125 ° C. for 30 minutes each was repeated 3000 cycles. There was no significant change in the wiring resistance values before and after the test, and all were distributed within the range of measurement error.

  For comparison, the height of the conductive pillar 24 is made smaller than the thickness of the insulating layer 21 through which the tip of the conductive pillar 24 penetrates by the manufacturing method described in the seventh and eighth embodiments (insulating layer). In consideration of shrinkage due to thermosetting of 21), a multilayer wiring board having four wiring layers was manufactured. All the materials including the insulating layers 21 and 21b wiring layers 22, 23, 27a, and 27b conductive pillars 24 are the same as those in the seventh and eighth embodiments.

  The wiring circuit was also formed in the same pattern. The multilayer wiring board was cut, and the cross-sectional shape of the conductive pillar 24 and the contact angle between the conductive pillar 24 and the wiring layers 22, 23, 27a, and 27b were observed. The cross-sectional shape by a plane parallel to the axis of the conductive pillar 24 is the shape shown in FIGS. 11A and 11B. The contact angle θ was distributed in the range of 30 to 150 °.

  The multilayer wiring board of this comparative example was dipped in a solder bath at 288 ° C. for 20 seconds and then pulled up and tested for changes in wiring resistance. As a result, 95% of the via connections were in a broken state on average. When the cross section was observed longitudinally, peeling occurred at the bonding interface between the conductive pillar 24 and the wiring layers 22, 23, 27a, 27b. This is because the insulating layers 21 and 21b are thermally expanded in the axial direction of the conductive pillar 24 to a greater extent than the conductivity due to the heat load caused by the solder bath. At this time, in the structure of the multilayer wiring board of the comparative example, the conductive pillar 24 is used. This is because a large stress (tension) is concentrated on the bonding interface between the wiring layer 22, 23, 27 a, and b, particularly on the notch of the bonding portion between the outer surface of the conductive pillar 24 and the wiring layer.

  Next, the relationship between the height h of the conductive pillar 24 and the thickness d of the insulating layer 21 will be described. The inventor made the multilayer wiring board of the present invention by changing the height d of the conductive pillar 24 and performed various tests.

  As the insulating layer 21, an epoxy resin prepreg with a glass cloth having a thickness of about 115 μm was used. On the other hand, as the first wiring layer 22 and the second wiring layer 23, an electrolytic copper foil having a thickness of about 35 μm was used. Then, as the conductive pillar 24, screen printing, drying, and curing of a conductive paste using silver fine particles as a conductive filler were repeated, and six types of multilayer wiring boards having different heights d of the conductive pillar 24 were manufactured. Each of the conductive pillars 24 has a substantially conical shape having a substantially circular bottom surface, and the diameter of the bottom surface is about 250 μm. The height d was 100 μm, 140 μm, 200 μm, 300 μm, 570 μm, and 600 μm. Therefore, the contact angle θ between the first wiring layer 22 and the conductive pillar 24 has such a shape that stress is not concentrated in any case. The insulating layer 21 shrinks by about 20% when cured, and its thickness d becomes about 100 μm. Therefore, the protruding height of the conductive pillar 24 is set such that the height h of the conductive pillar 24 is 100 μm. In this case, it is slightly exposed, and in other cases, it is about 40 μm, 100 μm, 200 μm, 470 μm, or 500 μm.

  An insulating layer 21 made of an epoxy resin prepreg with a glass cloth having a thickness of 115 μm is laminated on the first wiring layer 22 on which such conductive pillars 24 are formed, and the head is plastically deformed by pressing with a stainless steel plate. Crushed. Next, a second wiring layer 23 made of an electrolytic copper foil having a thickness of about 35 μm was laminated and pressed while being heated.

  While the insulating layer was cured by heating, the first wiring layer 22 and the second wiring layer 23 were connected by the conductive pillar 24.

  The six types of multilayer wiring boards thus manufactured were cut and the structure of the interlayer connection including the conductive pillars 24 was observed with a photograph. 19A shows an interlayer connection structure of a multilayer wiring board manufactured by adjusting the height h of the conductive pillar 24 to 100 μm, and FIGS. 19B, 19C, 19D, 19E, and 19F show the structure of the conductive pillar 24, respectively. It is a figure which shows typically the structure of the interlayer connection of the multilayer wiring board manufactured by adjusting height d to 140 micrometers, 200 micrometers, 300 micrometers, 570 micrometers, and 600 micrometers.

  When the height h of the conductive pillar 24 is smaller than the thickness d of the insulating layer 21, the bonding area with the second wiring layer 23 is not sufficient as shown in FIG. 19A. Further, the contact angle θ was larger than 90 ° and distributed in a range of about 100 to 160 °.

  On the other hand, when the height h of the conductive pillar 24 is set larger than the thickness d of the insulating layer 21 (h = 140 μm, 200 μm, 300 μm, 570 μm, the junction area with the second wiring layer 23 is sufficient. In addition, the contact angle θ was smaller than 90 ° and the stress was not easily concentrated, and the contact angle θ was distributed in a range of approximately 30 to 80 °.

However, when the height h of the conductive pillar 24 exceeds 5 times the thickness of the insulating layer 21 (FIG. 19F), there was a portion where the second wiring layer 23 was damaged. A multilayer wiring board in which a second wiring layer is formed on another insulating layer 21c and a stress release means as illustrated in FIG. 2 is provided in a via land connected to the conductive pillar 24 having a height h of 600 μm. When manufactured, the second wiring layer 23 as shown in FIG. 19F was not damaged (FIG. 19G). Note that the conductive pillar 24 has a penetration portion 24b partially penetrating into the insulating layer 21c.
Further, the first wiring layer 22 and the second wiring layer 23 of the multilayer wiring board shown in FIG. 19A to FIG. 19F are patterned into a wiring circuit, and after being immersed in a solder bath at about 288 ° C. for 20 seconds, a test is performed. Then, the change of the wiring resistance before and after that was investigated.

In the multilayer wiring board in which the height h at the time of forming the conductive pillar 24 was set to 100 μm and 600 μm, poor connection was recognized after the test, and the resistance value was also increased in the portion where conduction was ensured.
On the other hand, in the multilayer wiring board in which the height h at the time of forming the conductive pillar 24 is set to 140 to 570 μm, no significant change is observed in the wiring resistance value before and after the test, and it is distributed within the measurement error range. It was. Even when the same test was repeated five times, no significant change was observed in the wiring resistance value, and the distribution was within the measurement error range.

  Separately, the first wiring layer 22 and the second wiring layer 23 of the multilayer wiring board shown in FIGS. 19A to 19F are patterned into a wiring circuit, and a thermal load cycle of 20 seconds at 20 ° C. and 5 seconds at 260 ° C. A hot oil test was repeated, and changes in wiring resistance before and after the test were examined.

In the multilayer wiring board in which the height h at the time of forming the conductive pillar 24 was set to 100 μm and 600 μm, poor connection was recognized after the test, and the resistance value was also increased in the portion where conduction was ensured.
On the other hand, in the multilayer wiring board in which the height h at the time of forming the conductive pillar 24 is set to 140 to 570 μm, no significant change is observed in the wiring resistance value before and after the test, and it is distributed within the measurement error range. It was. Even when the same test was repeated five times, no significant change was observed in the wiring resistance value, and the distribution was within the measurement error range.

  In addition, a multilayer wiring board (four-layer board) according to the present invention having interlayer connections with 10,000 conductive pillars was manufactured. In this multilayer wiring board, most of the connection shapes between the outer surface of the conductive pillar 24 and the surface of the wiring layer (via land) have shapes as shown in FIGS. 10A, 10B, and 10C, for example. 12A and 12B, the macroscopic contact angle θ was smaller than 90 °, but the microscopic contact angle ψ was 90 ° or more.

  When this multilayer wiring board was subjected to the hot oil test as described above to check the continuity of the interlayer connection, the continuity was ensured at all the connection portions. In addition, the wiring resistance value before and after the test was not significantly changed and was distributed within the measurement error range. Even when the same test was repeated five times, no significant change was observed in the wiring resistance value, and the distribution was within the measurement error range.

  For comparison, a multilayer wiring board (four-layer board) having an interlayer connection with 10,000 conductive pillars having a connection shape with a macroscopic contact angle θ larger than 90 ° as shown in FIGS. 11A and 11B is manufactured. Then, when the same test was performed, all the connection portions were defective in conduction.

  As described above, since the multilayer wiring board of the present invention has an interlayer connection structure with conductive pillars that do not concentrate stress, it is conductive even when a thermal load is applied in the mounting process or usage environment. The occurrence of peeling and disconnection between the conductive pillar and the wiring layer can be prevented. Therefore, it is possible to provide a multilayer wiring board having high reliability and a simple structure. In addition, since the multilayer wiring board of the present invention has a small number of through holes or no through holes, the mountable area of electronic components can be expanded and high-density mounting can be supported.

  Further, according to the method for manufacturing a multilayer wiring board of the present invention, it is possible to manufacture a multilayer wiring board in which the bonding strength between the conductive pillar and the wiring layer is improved without reducing the productivity. According to the method for manufacturing a multilayer wiring board of the present invention, electrical connection between wiring layers can be easily and reliably ensured. Therefore, a highly reliable multilayer wiring board can be provided at low cost.

  The multilayer wiring board of the present invention is used not only for wiring boards for general electronic devices and personal computers, but also for wiring boards for multichip modules (MCM) and CSP (Chip Size Package). Reliability can be improved and mounting density can be improved.

FIG. 20A is a perspective view schematically showing an example of an electronic component of the present invention, and FIG. 20B is a diagram showing a schematic structure of this electronic component seen through from the side opposite to the electrode forming surface. Here, a semiconductor element is shown as an example of the electronic component.

  The semiconductor element 41 is in a bare chip state and has 64 electrodes 42 for connection to an external circuit. On each electrode 42, a conductive pillar 43 having a substantially conical shape similar to that described above is formed. The electronic component is not limited to a semiconductor element, and for example, a surface acoustic wave element may be used. Further, the state of the electronic component is not limited to the bare chip, but may be molded with resin or the like, or may be sealed with a metal case or the like.

  The conductive pillar 43 was formed by the same method as described above. FIG. 21A, FIG. 21B, and FIG. 21C are diagrams for explaining an example of a method for forming a conductive pillar on an electrode of an electronic component. That is, first, from the upper side of the electrode 42, the metal mask 31 having a cylindrical through hole 31a is disposed at a predetermined position (FIG. 21A). Then, the conductive resin 33 is filled by screen printing (FIG. 21B), and the metal mask 31 is pulled up in the normal direction of the surface of the electrode 42 to thereby have a substantially conical shape on the electrode 42 of the semiconductor element 41. Pillars 43 were formed (FIG. 21C). The conductive pillar 43 formed in this way fixed the outer shape by heat-curing the binder resin.

  The contact portion between the conductive pillar 43 and the electrode 42 has a shape in which the outer peripheral surface of the conductive pillar 43 and the surface of the electrode 42 are smoothly continuous, and has a shape in which stress concentration hardly occurs. .

  Such an electronic component of the present invention having conductive pillars as means for connecting to an external circuit is mounted on the multilayer wiring board in the same manner as the multilayer wiring process of the multilayer wiring board of the present invention, and the electronic component of the present invention is mounted. A component package can be obtained.

For example, first, a wiring layer having a predetermined pattern having via lands at positions corresponding to the electrodes of the electronic component and an electronic component having conductive pillars formed on the electrodes are arranged to face each other via an uncured insulating resin layer. . Then, by applying pressure from both sides, the conductive pillar penetrates the semi-cured insulating resin layer and is connected to the via land while being plastically deformed. The insulating resin layer is cured by heating at the same time.
Thus, the electronic component of the present invention has a great advantage that no solder is required for mounting. Further, by mounting on the multilayer wiring board of the present invention, the lead wiring from the electronic component can be handled by a plurality of wiring layers, and the mounting density can be remarkably improved.

  FIG. 22 is a perspective view schematically showing an example of an electronic component package of the present invention. FIG. 23 is a diagram schematically showing a cross-sectional structure in the AA direction of the electronic component package shown in FIG.

  This electronic component package is obtained by mounting the electronic component 40 of the present invention as illustrated in FIG. 20 on the multilayer wiring substrate 50 of the present invention as described above, and the electrical connection between the semiconductor element 41 and the multilayer wiring substrate 50. Connection is performed by the conductive pillar 43.

  The electrode 42 of the semiconductor element 41 and the via land 13 a of the wiring board are connected by a conductive pillar 43. The via land 13 a has a through hole as illustrated in FIG. 2 and can release normal stress applied in the axial direction of the conductive pillar 43. Further, some via lands 13 a are directly connected to via lands 12 a of another wiring layer via conductive pillars 14. That is, in the electronic component package of FIG. 22, the electrodes 42 of the semiconductor element 41 are connected to via lands formed in a plurality of different wiring layers. For example, the electrode 42a is connected to the wiring layer to which the via land 13a belongs, while the electrode 42b is connected to the wiring layer to which the via land 12a belongs. Therefore, even an electronic component having a high degree of integration and a large number of electrodes can be easily routed and the mounting area can be reduced. Further, the connection part between the electronic component package and the external circuit may be formed by forming, for example, a pad for PGA, BGA or wire bonding around the electronic component mounting surface of the multilayer wiring board 50 or the back surface thereof. Good. As a matter of course, via connection using via lands and conductive pillars included in the multilayer wiring board of the present invention as described above may be used for a connection portion of such an electronic component package with an external circuit.

  Such an electronic component package structure can also be applied to a chip size package (CSP) in which the package size is very close to the chip size.

  Thus, an electronic component package suitable for high-density mounting can be obtained by combining the multilayer wiring board of the present invention and an electronic component. The number of electronic components mounted on the substrate is not limited to one, and a plurality of different types of electronic components may be mounted on a single multilayer wiring board. For example, the present invention can be applied in exactly the same manner when a multichip module is configured by mounting a semiconductor element and a chip capacitor.

  As described above, the multilayer wiring board according to the present invention includes the via land having the stress releasing means, so that the stress applied to the via land in the axial direction of the conductive pillar can be released. Further, the stress (tangential stress) applied in the tangential direction of the via land is relieved mainly by plastic deformation of the conductive pillar. Therefore, damage to via land and wiring circuit can be avoided, and highly reliable interlayer connection can be established. In addition, since interlayer connection by through holes can be suppressed to a necessary minimum, high-density mounting can be supported.

  In the multilayer wiring board of the present invention, the contact portion between the conductive pillar and the via land or the wiring layer has a shape in which stress is not concentrated. Even in such a case, peeling of the conductive pillar and the wiring layer and disconnection can be prevented. Therefore, it is possible to provide a multilayer wiring board having high reliability and a simple structure. In addition, since the multilayer wiring board of the present invention has a small number of through holes or no through holes, the mountable area of electronic components can be expanded and high-density mounting can be supported. Furthermore, when used in combination with stress relief means, even if pressure is applied between the conductive pillar and via land, even when tension is applied, damage to the via connection is prevented and the function of the interlayer connection is stably maintained. Can do.

  Such a multilayer wiring board of the present invention is used not only for wiring boards of general electronic devices and personal computers, but also for wiring boards of multichip modules (MCM) and CSP (Chip Size Package). Therefore, it is possible to improve the connection reliability and the mounting density.

According to the prefabricated material of the multilayer wiring board of the present invention, it is possible to easily manufacture a multilayer wiring board using a conductive pillar and having a highly reliable interlayer connection portion with a simple structure.
Further, according to the method for manufacturing a multilayer wiring board of the present invention, it is possible to suppress the occurrence of connection failure while maintaining the high productivity of the method for manufacturing a multilayer wiring board using conductive pillars. Further, productivity can be improved.

  Further, according to the method for manufacturing a multilayer wiring board of the present invention, it is possible to manufacture a multilayer wiring board in which the bonding strength between the conductive pillar and the wiring layer is improved without reducing the productivity. According to the method for manufacturing a multilayer wiring board of the present invention, electrical connection between wiring layers can be easily and reliably ensured. Therefore, a highly reliable multilayer wiring board can be provided at low cost.

  In addition, according to the method for forming a conductive pillar of the present invention, for example, a conductive pillar having high connection reliability with less stress concentration is formed on an electrode of an electronic component, a conductor layer of a wiring board, or a via land. Can do.

  The electronic component of the present invention can be mounted without using solder. Therefore, the health of workers can be protected during the manufacturing process, and environmental pollution can be prevented. In addition, by mounting the electronic component of the present invention on a multilayer wiring board, the lead wiring from the electronic component can be handled by a plurality of wiring layers, and the mounting density can be remarkably improved.

  According to the electronic component package of the present invention, the mounting surface of the electronic component can be used in multiple layers, and even an electronic component having a high degree of integration and a large number of electrodes can be handled with a small mounting area. Therefore, various electronic component mounting packages including CSP and MCM can be further miniaturized or the mounting density can be improved. The lead-out wiring from the electrode of the electronic component can be easily routed, and the degree of freedom in design can be greatly improved.

It is a figure which shows roughly an example of a structure of the multilayer wiring board of this invention. It is a figure which shows roughly an example of the shape of a 1st via land. It is a figure which shows roughly another example of the shape of a 1st via land. It is a figure which shows roughly another example of the shape of a 1st via land. It is a figure which shows roughly another example of the shape of a 1st via land. It is a figure which shows roughly another example of the shape of a 1st via land. It is a figure which shows roughly another example of the shape of a 1st via land. It is a figure which expands and shows the interlayer connection part of the multilayer wiring board of this invention shown in FIG. It is sectional drawing which shows schematically another example of a structure of the multilayer wiring board of this invention. It is a figure for demonstrating the manufacturing process of the multilayer wiring board of this invention shown in FIG. It is a figure for demonstrating the manufacturing process of the multilayer wiring board of this invention shown in FIG. It is a figure for demonstrating the manufacturing process of the multilayer wiring board of this invention shown in FIG. It is a figure for demonstrating another example of the manufacturing method of the multilayer wiring board of this invention. It is a figure for demonstrating another example of the manufacturing method of the multilayer wiring board of this invention. It is a figure for demonstrating another example of the manufacturing method of the multilayer wiring board of this invention. It is a figure for demonstrating another example of the manufacturing method of the multilayer wiring board of this invention. It is a figure which shows a mode that the multilayer wiring board of FIG. 7D was cut | disconnected in the plane parallel to the axial direction of an electroconductive pillar, and the state of the interlayer connection part was observed. It is a figure which shows roughly the cross-section of the interlayer connection part of the multilayer wiring board of this invention. It is a figure which shows roughly the cross-section of the interlayer connection part shown to FIG. 9A. It is a perspective view which shows roughly the structure of the interlayer connection part shown to FIG. 9A. It is a figure which shows typically the example of the shape of the connection part of an electroconductive pillar and a 1st via land or a 2nd via land. It is a figure which shows typically the example of the shape of the connection part of an electroconductive pillar and a 1st via land or a 2nd via land. It is a figure which shows typically the example of the shape of the connection part of an electroconductive pillar and a 1st via land or a 2nd via land. It is a figure which shows typically the example which is not desirable of the shape of the connection part of the conductive pillar shown for the comparison, and the 1st via land or the 2nd via land. It is a figure which shows typically the example which is not desirable of the shape of the connection part of the conductive pillar shown for the comparison, and the 1st via land or the 2nd via land. It is a figure which shows typically another example of the shape of the connection part of an electroconductive pillar and a 1st via land or a 2nd via land. It is a figure which shows typically another example of the shape of the connection part of an electroconductive pillar and a 1st via land or a 2nd via land. It is a figure which shows typically an example of the structure of the multilayer wiring board of this invention. It is a figure which shows typically a state when a thermal load is applied to the multilayer wiring board of FIG. 13A. It is a figure for demonstrating an example of the manufacturing method of the multilayer wiring board of this invention. It is a figure for demonstrating an example of the manufacturing method of the multilayer wiring board of this invention. It is a figure for demonstrating an example of the manufacturing method of the multilayer wiring board of this invention. It is a figure for demonstrating an example of the manufacturing method of the multilayer wiring board of this invention. It is a figure for demonstrating an example of the manufacturing method of the multilayer wiring board of this invention. It is a figure for demonstrating an example of the manufacturing method of the multilayer wiring board of this invention. It is a figure for demonstrating an example of the manufacturing method of the multilayer wiring board of this invention. It is a figure for demonstrating an example of the manufacturing method of the multilayer wiring board of this invention. 5 is a diagram for explaining an example of a process for forming a conductive pillar 24. FIG. 5 is a diagram for explaining an example of a process for forming a conductive pillar 24. FIG. 5 is a diagram for explaining an example of a process for forming a conductive pillar 24. FIG. 5 is a diagram for explaining an example of a process for forming a conductive pillar 24. FIG. 5 is a diagram for explaining an example of a process for forming a conductive pillar 24. FIG. 2 is a diagram schematically showing a relationship between a conductive pillar 24 and an insulating layer 21. FIG. It is a figure which shows typically a mode that the 1st wiring layer and the 2nd wiring layer were arrange | positioned with the conductive pillar facing from both sides of an insulating layer. It is a figure which shows typically the structure of the interlayer connection part of the multilayer wiring board of this invention formed by making the conductive pillar 24 oppose and penetrate from both sides of the insulating layer. 19A to 19F are diagrams schematically showing the structure of the interlayer connection of the multilayer wiring board manufactured by changing the height h of the conductive pillar. 19A to 19F are diagrams schematically showing the structure of interlayer connection of a multilayer wiring board manufactured by changing the height h of the conductive pillar. 19A to 19F are diagrams schematically showing the structure of interlayer connection of a multilayer wiring board manufactured by changing the height h of the conductive pillar. 19A to 19F are diagrams schematically showing the structure of the interlayer connection of the multilayer wiring board manufactured by changing the height h of the conductive pillar. 19A to 19F are diagrams schematically showing the structure of the interlayer connection of the multilayer wiring board manufactured by changing the height h of the conductive pillar. It is a figure which shows typically the structure of the interlayer connection of the multilayer wiring board manufactured by changing the height h of each conductive pillar. FIG. 20 is a diagram schematically showing an interlayer connection structure of the multilayer wiring board of FIG. 19F in which stress releasing means is formed in the via land. 1 is a perspective view schematically showing an example of an electronic component of the present invention. FIG. 20B is a diagram illustrating the electronic component of FIG. 20A seen from the back side. It is a figure for demonstrating one example of the method of forming a conductive pillar on the electrode of an electronic component. It is a figure for demonstrating one example of the method of forming a conductive pillar on the electrode of an electronic component. It is a figure for demonstrating one example of the method of forming a conductive pillar on the electrode of an electronic component. It is a perspective view which shows roughly an example of the electronic component package of this invention. It is a figure which shows roughly the cross-section of the AA direction of the electronic component package shown in FIG. It is sectional drawing which shows one example of the cross-sectional structure of the conventional multilayer wiring board. It is a figure which shows one example of the manufacturing method of the multilayer wiring board which connected the wiring layer using the conductive bump. It is a figure which shows one example of the manufacturing method of the multilayer wiring board which connected the wiring layer using the conductive bump. It is a figure which shows another example of the manufacturing method of the multilayer wiring board which connected the wiring layer using the conductive bump. It is a figure which shows another example of the manufacturing method of the multilayer wiring board which connected the wiring layer using the conductive bump. It is a figure which shows typically the via connection part of the multilayer wiring board by which the via land became concave by the pressurization process.

Claims (18)

A multilayer wiring board in which a wiring layer and an insulating layer are laminated,
A first insulating layer having a first surface;
A first wiring layer having a first via land formed on the first surface of the first insulating layer and having a through hole;
A second insulating layer formed on the first insulating layer from above the first wiring layer ;
A second via land formed on the second insulating layer so as to face the first via land;
A multilayer wiring board comprising: a conductive pillar that connects the first via land and the second via land and has a portion penetrating into the first insulating layer from the through hole of the first via land. . The rigidity of the conductive pillar, a multilayer wiring board according to claim 1, wherein greater than the stiffness of the first insulating layer. The multilayer wiring board according to claim 1, wherein the conductive pillar is made of a conductive resin. Shape of the contact portion between the conductive pillar and the first via land and the second via land, a portion where the outer surface of the first via land and the second via land of a surface of the conductive pillar is smoothly and continuously The multilayer wiring board according to claim 1, comprising: Shape of the contact portion between the conductive pillar and the first via land and the second via land, the angle between the outer surface and the first via land and the second via land of a surface of the conductive pillar is an acute angle portion The multilayer wiring board according to claim 1, comprising: A method for manufacturing a multilayer wiring board, comprising:
Forming a first wiring layer having a first via land having a through hole on the first insulating layer;
Forming a conductive pillar having a substantially conical shape in a region corresponding to the first via land of the first wiring layer on the conductor layer;
Disposing the first insulating layer and the conductor layer via an uncured insulating resin layer so that the first via land and the conductive pillar face each other;
The first insulating layer and the conductor layer are pressed in the axial direction of the conductive pillar so that a part of the conductive pillar penetrates into the first insulating layer through a hole formed in the first via land. And a step of connecting the first via land and the conductive pillar. A method for manufacturing a multilayer wiring board, comprising:
Forming a first wiring layer having a first via land having a through hole on the first surface of the first insulating layer;
Forming a conductive pillar having a substantially conical shape on the first via land of the first insulating layer;
Laminating an uncured insulating resin layer on the first surface of the first insulating layer such that the head of the conductive pillar is exposed;
A step of disposing a conductor layer opposite to the first surface of the first insulating layer via the insulating resin layer;
The first insulating layer and the conductor layer are added in the axial direction of the conductive pillar so that a part of the conductive pillar penetrates into the first insulating layer through a hole formed in the first via land. And a step of connecting the first via land and the conductive pillar under pressure. A method of manufacturing a multilayer wiring board, comprising: A method for manufacturing a multilayer wiring board, comprising:
Forming a first wiring layer having a first via land having a through hole on the first insulating layer;
Forming a first conductive pillar having a substantially conical shape on the first via land of the first wiring layer;
Forming a second conductive pillar having a substantially conical shape in a region corresponding to the first via land of the first wiring layer on the conductor layer;
Disposing the first insulating layer and the conductor layer through an uncured insulating resin layer so that the first conductive pillar and the second conductive pillar face each other;
The first and second conductive layers are connected to the first insulating layer and the conductor layer so that a part of the first conductive pillar penetrates the first insulating layer through a through hole formed in the first via land. A method of manufacturing a multilayer wiring board, comprising the step of connecting the first conductive pillar and the second conductive pillar by applying pressure in the axial direction of the conductive pillar. An electronic component package having electronic components mounted on a wiring board,
An electronic component having an electrode on a first surface;
A first insulating layer formed on the electronic component, the first surface having a first surface and a second surface, the first surface facing the first surface of the electronic component;
A first wiring layer formed on the second surface of the first insulating layer and having a first via land;
A first conductive pillar connecting the first via land and the electrode;
Wherein the first via land, electronic components package and having a through-hole. The contact portion between the first conductive pillar and the electrode has a portion in which the outer surface of the first conductive pillar and the electrode surface are smoothly continuous . Electronic component package . Electronic component package according to claim 9 contact portion between the electrode and the conductive pillar, characterized in that the angle between the outer surface and the surface of the electrodes of the conductive pillar has a portion is an acute angle. The electronic component package according to claim 9, wherein the electronic component is a semiconductor element. The electronic component package according to claim 12, wherein the semiconductor element is a bare chip. An electronic component package,
An electronic component having a pad-like electrode on the first surface;
A first insulating layer formed on the electronic component, the first surface having a first surface and a second surface, the first surface facing the first surface of the electronic component;
A first wiring layer formed on the second surface of the first insulating layer and having a first via land;
A first conductive pillar connecting the first via land and the electrode;
A second insulating layer having a first surface and a second surface, the first surface being opposed to the second surface of the first insulating layer and formed on the first insulating layer;
A second wiring layer formed on the second surface of the second insulating layer and having a second via land;
A second conductive pillar connecting the first via land and the second via land;
The electronic component package, wherein the first via land or the second via land has a through hole. The contact portion between the first conductive pillar and the electrode has a portion in which the outer surface of the first conductive pillar and the electrode surface are smoothly continuous . Electronic component package . Electronic component package according to claim 14 a contact portion between the electrode and the conductive pillar, characterized in that the angle between the outer surface and the surface of the electrodes of the conductive pillar has a portion is an acute angle. The electronic component package according to claim 14, wherein the electronic component is a semiconductor element. The electronic component package according to claim 17, wherein the semiconductor element is a bare chip.

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