JP4053285B2 - Facsimile modem apparatus and facsimile apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a facsimile modem apparatus that temporarily stores received data in a buffer and then outputs the data, and a facsimile apparatus including the facsimile modem apparatus.
[0002]
[Prior art]
In recent years, with the increase in the transmission speed of a facsimile, the time interval at which the host controller that controls the facsimile system collects the demodulated data output from the modem is shortened. Then, taking the demodulated data from the modem at such a short interval increases the processing load on the host controller.
[0003]
For this reason, facsimile modem devices equipped with a high data rate often have a FIFO buffer for the purpose of reducing the processing load on the host controller.
[0004]
[Problems to be solved by the invention]
By the way, the FIFO buffer can reduce the instantaneous maximum load of the host depending on the size of the buffer. However, in the control part of the facsimile transmission procedure, when demodulated data is collected via the FIFO buffer, In some cases, problems occur due to loss of real-time performance.
[0005]
The present invention has been made in view of such circumstances, and an object of the present invention is to provide a facsimile modem apparatus and a facsimile apparatus that can appropriately receive and process a facsimile transmission procedure signal.
[0006]
[Means for Solving the Problems]
The present invention relates to a facsimile modem apparatus for temporarily storing received data in a buffer and then outputting the data, wherein the received data is stored, and the stored received data is read by a next-stage apparatus, and the data A control data FIFO buffer having the same number of shift stages as that of the FIFO buffer and shifted in synchronization with the data FIFO buffer, and a flag indicating the head and tail of the data frame when receiving the data frame of the facsimile transmission procedure A series of mark data corresponding to each is generated and accumulated in the control data FIFO buffer, and when a series of data from the beginning to the last data of the data frame is continuously detected, a count up signal is output. Read from the control FIFO buffer A state management unit that generates a countdown signal each time the series of mark data detected is detected, and the number of data frames that are counted up by the countup signal and counted down by the countdown signal and accumulated in the data FIFO buffer And a frame counter that outputs the number of data frames .
[0007]
In addition, the state management unit, in response to a command from an external device, instructs the start of the latest data frame stored in the data FIFO buffer, the value of the read pointer of the data FIFO buffer, and the control The value of the read pointer of the data FIFO buffer is updated.
[0008]
A facsimile apparatus comprising the facsimile modem apparatus according to claim 1 .
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[0011]
FIG. 1 shows a group 3 facsimile apparatus according to an embodiment of the present invention.
[0012]
In the figure, a system control unit 1 performs control processing for each part of the group 3 facsimile apparatus and predetermined group 3 facsimile transmission control procedure processing. The system control unit 1 executes the system memory 2. The control processing program and various data necessary for executing the processing program are stored, and the work area of the system control unit 1 is configured. The parameter memory 3 is unique to the group 3 facsimile machine. The clock circuit 4 is for storing various types of information, and the clock circuit 4 is for outputting current time information.
[0013]
The scanner 5 reads an original image with a predetermined resolution, the plotter 6 records and outputs an image with a predetermined resolution, and the operation display unit 7 operates the group 3 facsimile apparatus. It consists of various operation keys and various displays.
[0014]
The encoding / decoding unit 8 encodes and compresses the image signal, and also decodes the encoded and compressed image information into the original image signal. The image storage device 9 performs encoding and compression. This is for storing a large number of image information in the selected state.
[0015]
The group 3 facsimile modem 10 is for realizing the modem function of the group 3 facsimile, and is a low-speed modem function (V.21 modem) for exchanging transmission procedure signals and mainly for exchanging image information. A high-speed modem function (V.17 modem, V.34 modem, V.29 modem, V.27ter modem, etc.) is provided.
[0016]
The network control apparatus 11 is for connecting the group 3 facsimile apparatus to the analog public network PSTN, and has an automatic outgoing / incoming function.
[0017]
The system control unit 1, the system memory 2, the parameter memory 3, the clock circuit 4, the scanner 5, the plotter 6, the operation display unit 7, the encoding / decoding unit 8, the image storage device 9, the group 3 facsimile modem 10, and The network control device 11 is connected to an internal bus 12, and data exchange between these elements is mainly performed via the internal bus 12.
[0018]
Data exchange between the network control device 11 and the group 3 facsimile modem 10 is performed directly.
[0019]
Further, the group 3 facsimile modem 10 includes a FIFO buffer at the output stage of received data, and an example of the configuration of the output stage is shown in FIG. Here, the data capacity of the FIFO buffer is set to a value sufficient for communication in the ECM mode, for example, 1024 to 2048 octets.
[0020]
In the figure, received data DT is added to the data FIFO buffer FFd and the state management unit CC in a 1-octet (8-bit) parallel state, for example.
[0021]
The data FIFO buffer FFd is a data shift register FSd that sequentially transfers input 1-octet parallel received data, and a FIFO pointer that stores FIFO pointer data for managing the head address output by the data FIFO buffer FFd. A register FP is provided. The output of the data shift register FSd is output to the next stage device as reception output data DTo.
[0022]
The state management unit CC analyzes the received data DT and determines which part of the HDLC frame (described later) constituting the facsimile transmission procedure signal is received when receiving the facsimile transmission procedure signal at the time of facsimile communication. In addition, the mark data MD representing the determination result is output, and when one complete HDLC frame is detected, the count-up signal CU is output, and when one complete HDLC frame is output to the external device, the count-down signal CD is output. When the partial clear signal PCL is applied from the external device, the value of the FIFO pointer register FP of the data FIFO buffer FFd is set so as to indicate the head of the data determined as a complete HDLC frame at that time. It is something to be preset. Further, the mark data MD output from the state control unit CC is output to the control data FIFO buffer FFc, and the count up signal CU and the count down signal CD are output to the frame counter CB, respectively.
[0023]
The control data FIFO buffer FFc has the same number of shift stages as the data shift register FSd of the data FIFO buffer FFd, and includes a control data shift register FSc that sequentially stores the mark data MD output from the state management unit CC.
[0024]
Here, V. which is a facsimile transmission procedure signal. 21 frames will be described. ITU-T recommendation 30 according to V.30 carrying a binary signal. As shown in FIG. 3A, 21 frames are provided with a preamble having a length of 1 second ± 5% at the head thereof. In addition, this preamble is a flag in which a flag composed of one octet data of a predetermined bit pattern (0111110) is continued a plurality of times.
[0025]
V. The 21 frame has a frame configuration of an HDLC frame as shown in FIG. This HDLC frame has two flags at the beginning, an address field of 1 octet length, a control field of 1 octet length, an information field of arbitrary octet length, a frame check sequence (FCS; CRC data) of octet length, and a tail Are configured by arranging one flag respectively.
[0026]
V. In the case of 21 frames, as shown in FIG. 6C, an FCF representing a facsimile transmission procedure signal and an FIF for notifying information necessary for the facsimile transmission procedure signal are arranged in the information field.
[0027]
With the above configuration, when the group 3 facsimile modem 10 performs a reception operation, the reception data DT output from the reception unit (not shown) of the group 3 facsimile modem 10 is sequentially input to the data shift register FSd of the data FIFO buffer FFd. And is added to the state manager CC.
[0028]
The state management unit CC examines the contents of the received data DT, and the above-described V.D. When the preamble added to the head of the 21th frame is detected, the mark data MD representing the preamble is output to the control data FIFO buffer FFc. When a flag (trailing flag) representing the end of 21 frames is detected, mark data MD representing the final data is output to the control data FIFO buffer FFc (see FIG. 4A). The output data from the control data FIFO buffer FFc is input to the state management unit CC.
[0029]
In addition, the state management unit CC receives the V.V. When a series of data up to the final data of 21 frames is continuously detected, a count-up signal CU is output to the frame counter CB, whereby the frame counter CB performs a count-up operation, and the reception output from the frame counter CB is received. The value of the number of frames NB increases.
[0030]
On the other hand, when the system control unit 1 reads the received data from the group 3 facsimile modem 10, the read operation of the received output data DTo is performed on the data FIFO buffer FFd . Accordingly, the data FIFO buffer FFd sequentially outputs data from the data shift register FSd, and the output data is output to the system control unit 1 as reception output data DTo.
[0031]
Further, the state management unit CC monitors the read operation, and performs the shift operation of the control data FIFO buffer FFc in accordance with the shift operation of the data shift register FSd. As a result, since the state management unit CC receives the mark data MD output from the control data FIFO buffer FFc, the state management unit CC sequentially examines the mark data MD, and the V.V. When a series of mark data MD up to the final data of 21 frames is detected, a countdown signal CD is output to the frame counter CB. As a result, the frame counter CB performs a countdown operation, and the value of the number of received frames NB output from the frame counter CB decreases.
[0032]
Further, each time the reception data DT is input to the data shift register FSd, the value of the address of the data shift register FSd to which the reception data DT is to be input is updated among the values of the FIFO pointer register FP. Each time data is read from the register FSd, the value of the address of the data shift register FSd from which the received data DT is to be read out of the value of the FIFO pointer register FP is updated.
[0033]
In this way, when the group 3 facsimile modem 10 is receiving, the value of the number of received frames NB output from the frame counter CB is the V.V. stored in the data FIFO buffer FFc at that time. Since the number is equal to the number of 21 frames, the system control unit 1 reads the received frame number NB and reads the received data, for example, when the received data is read from the group 3 facsimile modem 10 using the DMA channel. Since the number can be designated, the received data can be read smoothly.
[0034]
By the way, when a remarkable line delay time occurs with a partner terminal, the following problems have conventionally occurred.
[0035]
For example, as shown in FIG. When 21 frames (1) are transmitted, this V.V. The 21 frame is received by the partner terminal after the line delay time t has elapsed (V.21 frame (2)).
[0036]
Here, when an echo due to crosstalk occurs, the V.V. The 21 frame {circle around (1)} is received by the own terminal when the line delay time t has elapsed after reaching the counterpart terminal (V.21 frame {circle around (3)}).
[0037]
On the other hand, in its own terminal, V.I. Since the transition to the receiving operation starts immediately after the completion of the transmission of 21 frames (1), V. 21 frames (3) are received. From the point in time before transmission of 21 frames {circle around (1)} is completed. If 21 frames (3) are received, The subsequent data is received in a state where the preamble portion of 21 frame (3) is missing.
[0038]
Then, from the other terminal, V.P. 21 frames (4) are sent out. 21 frame {circle around (4)} is received by the terminal itself after the line delay time t has elapsed. Received as 21 frames (5).
[0039]
Therefore, the V.V. When receiving a response signal from the partner terminal after the transmission of 21 frames (1) is completed, the data FIFO buffer FFd contains V. The data of the incomplete frame portion of 21 frames (3), The complete frame data of 21 frames (5) is accumulated, and the control data FIFO buffer FFc stores V.V. as shown in FIG. 21. Incomplete frame portion of frame (3); Mark data MD representing a complete frame of 21 frames (5) is stored.
[0040]
In this state, when the system control unit 1 performs a read operation of the received data from the group 3 facsimile modem 10, the echo component V.P. This is not preferable because even the incomplete part of 21 frame (3) is received.
[0041]
Therefore, the system control unit 1 outputs the partial clear signal PCL to the state management unit CC prior to the reception data read operation from the group 3 facsimile modem 10.
[0042]
As a result, the state management unit CC indicates the beginning of the data determined as a complete HDLC frame at that time (that is, indicates the position of the preamble of the last block (5)) , and the data FIFO buffer. The value of the FIFO pointer register FP of FFd is preset. Along with this, the value of the read pointer of the control data FIFO buffer FFc is also preset to a corresponding value.
[0043]
Therefore, after that, when the system control unit 1 performs the reading operation of the received data from the group 3 facsimile modem 10, only the desired received data is taken over by the system control unit 1 with the echo component data excluded. Become.
[0044]
In this way, since incomplete received data is suppressed from being taken over by the system control unit 1, for example, the system control unit 1 does not need to check the validity of the received data, and as a result, The processing load on the system control unit 1 can be greatly reduced.
[0045]
【The invention's effect】
As described above, according to the present invention, the received data is temporarily stored in the FIFO buffer and then output in the facsimile modem apparatus which outputs the received data in the facsimile transmission procedure. When receiving 21 frames, the V.V. stored in the FIFO buffer is received. Since the means for displaying the number of 21 frames is provided, it is possible to reduce the processing when the external device collects the received data.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration example of a group 3 facsimile apparatus according to an embodiment of the present invention.
FIG. 2 is a block diagram showing an example of a configuration of a received data output stage of the group 3 facsimile modem 10;
FIG. Schematic which showed an example of 21 frames.
FIG. 4 is a schematic diagram for explaining an accumulation mode of mark data MD in a control data FIFO buffer FFc.
FIG. 5 is a time chart for explaining an operation at the time of reception.
[Explanation of symbols]
1 System control unit FFd Data FIFO buffer FSd Data shift register FP FIFO pointer register CC State management unit FFc Control data FIFO buffer CB Frame counter

Claims (3)

A facsimile modem device for outputting received data once after storing it in a buffer ,
A data FIFO buffer in which received data is accumulated and the accumulated received data is read out by the next-stage device;
A control data FIFO buffer having the same number of shift stages as the data FIFO buffer and shifted in synchronization with the data FIFO buffer;
When receiving a data frame of a facsimile transmission procedure, a flag representing the beginning and end of the data frame is detected, a series of mark data corresponding to each is generated, stored in the control data FIFO buffer, and the data frame A state management unit that outputs a count-up signal when a series of data from the beginning to the last data is continuously detected, and generates a count-down signal each time the series of mark data read from the control FIFO buffer is detected;
A facsimile comprising a frame counter that counts up by the count up signal, counts down by the count down signal, counts the number of data frames stored in the data FIFO buffer, and outputs the number of data frames Modem device. In response to a command from the external device, the state management unit instructs the read pointer value of the data FIFO buffer and the control data FIFO to indicate the start of the latest data frame stored in the data FIFO buffer. 2. The facsimile modem apparatus according to claim 1 , wherein the value of the read pointer of the buffer is updated . A facsimile apparatus comprising the facsimile modem apparatus according to claim 1 .

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