JP4336790B2 - Clock switching method and clock switching device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a clock switching method and a clock switching device, and more particularly to a clock switching method and a clock switching device that perform switching without causing a transmission signal error due to clock switching.
[0002]
[Prior art]
In the wireless transmission device, in order to simplify the signal processing in the device, the clock is extracted from the input signal and used as the in-device clock. The clock in the device generates a clock synchronized with the input signal using a PLL circuit. However, when there are a plurality of input signals, the clock in the device is generated using an arbitrary input signal as a synchronization source. To synchronize and transmit other input signals. On the other hand, an input interface unit for synchronizing a plurality of input signals with the internal clock is required. However, there is a limit to the size of the input interface unit due to the size that can be mounted on the device, etc. All input signals cannot be synchronized with one input interface unit, and multiple input interface units are used. To synchronize.
[0003]
For this reason, when the input signal used as the internal clock generation synchronization source is deteriorated due to a failure, or when the input interface unit is removed from the device for maintenance, the internal clock synchronization source is not connected to the input interface unit that is not removed. It is necessary to switch. A digital sampling PLL circuit is used to switch the clock synchronization source in the apparatus without interruption. By using this digital sampling PLL circuit, it is possible to suppress the frequency fluctuation of the in-device clock even when the input signal used for line extraction is switched, and unnecessary data errors do not occur in other transmission signals. However, the digital sampling PLL circuit performs phase control using a value obtained by removing the lower X (X ≧ 1) bits of the sampling data from the quantization error at the time of digitizing the phase difference and the feasibility on the circuit configuration. When the internal clock synchronization source is switched, the following problem occurs.
[0004]
Here, as a conventional example, the input interface unit 2 ₁₁ 2 ₁₂ 9 will be described with reference to FIGS. 10 to 12 using a working first line (FIG. 1) including a working first wireless line of the apparatus configured as shown in FIG. In-device clock synchronization source is input signal 1 ₁ In the case of 201, the input interface unit 2 ₁₁ Then, in the conversion circuit 101, the input signal 1 ₁ The clock extracted from 201 is sent to the extraction selection circuit 104, and the extraction selection circuit 104 uses the phase control unit 4. ₁ Is selected using the control signal 221 from the control signal 221 and sent to the selection circuit 105. The selection circuit 105 uses the control signal 221 to input the input interface unit 2. ₁₁ The extraction selection clock 220 from the extraction selection circuit 104 is selected and sent to the digital PLL circuit 106. The digital PLL circuit 106 generates a clock and frame pulse (hereinafter referred to as FP) synchronized with the selection output 222 of the selection circuit 105, and inputs the input interface unit 2. ₁₁ To the multiplexing circuit 103.
[0005]
On the other hand, the input interface unit 2 ₁₂ However, the input interface unit 2 is similarly selected from the control signal 221 by the selection circuit 105. ₁₁ Is selected and sent to the digital PLL circuit 106. The digital PLL circuit 106 generates a clock and FP that are synchronized with the selection output 222 of the selection circuit 105, and inputs the input interface unit 2. ₁₂ To the multiplexing circuit 103. The digital PLL circuit 106 at this time is shown in FIG. 10, and the circuit operation will be described with reference to FIG. The frequency divider N 301 divides the selection output 222 by N (N ≧ 2), and sends it to the phase comparison circuit 303 as an N divided output 401. The frequency divider M302 sends an M frequency divided output 402 obtained by dividing the output clock 406 of the voltage control oscillator 311 by M (M ≧ 2) to the phase comparison circuit 303. The phase comparison circuit 303 compares the phase difference between the N-divided output 401 and the M-divided output 402, converts the phase comparison result 403 by the A / D conversion circuit 306, and counts 404 "a" (lower X (X ≧ X ≧ 2) The value excluding the bits is “A”). Using the timing signal (timing clock) of the timing generation circuit 305, the phase storage circuit 307 stores the count value 404 "a" as the storage value 405 "a". This operation is the input interface unit 2 ₁₁ And input interface part 2 ₁₂ Input interface part 2 ₁₁ And input interface part 2 ₁₂ The phase difference of the output FP407 of each frequency divider P315 is “0”.
[0006]
When the in-device clock synchronization source is switched at time t1 '' in FIG. 12, the input interface unit 2 ₁₁ In the digital PLL circuit 106, the control circuit 313 sets the control signal 408 to “H” to enter the phase holding state, and the output of the selection circuit T 308 is changed from the count value 404 “a” of the A / D conversion circuit 306 to the phase storage circuit 307. The storage value 405 "a" is switched and sent to the D / A conversion circuit 309, and the storage value 405 "a" of the phase storage circuit 307 is held so as not to be updated with the sampling clock.
[0007]
Next, the position of the N-divided output 401 of the frequency divider N301, which was the position of t2 ″ in the past, is changed to the position of t3 ″ by switching the in-device clock synchronization source. The count value 404 from the time t3 ″ to the time t4 ″ of the A / D conversion circuit 306 changes from “a” to “b” (the value excluding the lower X bits is “B”) at the time t5 ″. The circuit 314 compares the value “B” excluding the lower X bits of the count value 404 “b” with the value “A” excluding the lower X bits of the stored value 405 “a”, and compares the comparison result 409 with “LT”. Send out as As a result, the control circuit 313 controls the frequency divider M302 to change the phase of the M frequency divided output 402 from time t7 ″ to time t8 ″. The count value 404 of the A / D conversion circuit 306 from time t5 ″ to t9 ″ is “e” (the value excluding the lower X bits is “A”). At time t9 ″, the comparison circuit 314 compares the value “A” excluding the lower X bits of the count value 404 “e” with the value “A” excluding the lower X bits of the stored value 405 “a”. Since the count value 404 matches the stored value 405, the comparison result 409 is sent to the control circuit 313 as “EQ”. In the control circuit 313, when the comparison result 409 “EQ” is obtained, the control signal 408 is set to “L”, the output of the selection circuit T308 is switched from the stored value 405 “a” to the count value 404 “e”, and the stored value of the phase storage circuit 307 is set. The holding state at 405 is released and the phase holding operation is terminated.
[0008]
Thereafter, the digital PLL circuit 106 operates normally, and at time t10 ″ after a lapse of a certain time, the count value 404 ″ a ″ is obtained, so that θ3 ″ = θ1 ″ (FIGS. 11 and 12). Similarly, the input interface unit 2 ₁₂ However, switching of the in-device clock synchronization source occurs, and control is performed after the phase holding operation. However, the count value 404 of the A / D conversion circuit 306 from time t5 ″ to time t9 ″ becomes “f” (the value excluding the lower X bits is “A”), and then the control is canceled and time t10 ′. “Occasionally θ3 ″ = θ1 ″.
[0009]
[Patent Document 1]
JP-A-11-27247 (Claim 1, FIG. 1)
[0010]
[Problems to be solved by the invention]
However, this conventional technique has the following problems.
[0011]
The first problem is that the two input interface units 2 ₁₁ 2 ₁₂ The phase of the output FP 407 of the frequency divider P 315 fluctuates. The reason for this is that when the internal clock synchronization source is switched and becomes steady, θ3 ″ = θ1 ″ is obtained by the operation of the digital PLL circuit 106, but the input interface unit 2 ₁₁ Output FP 407 and input interface unit 2 of the digital PLL circuit 106 of FIG. ₁₂ A phase difference θ4 ″ (FIG. 12) occurs in the output FP407 of the digital PLL circuit 106, and the phase difference does not become constant. This is two input interface sections 2 ₁₁ 2 ₁₂ This is because the digital PLL circuit 106 of the digital PLL circuit 106 operates independently, and the count operation is performed because the control operation and sampling clock of each digital PLL circuit 106 are asynchronous, the quantization error of the sampling clock, and the feasibility of the circuit configuration. In order to compare the value 404 with the value excluding the lower X bits of the stored value 405, the count value 404 of the A / D conversion circuit 306 from time t5 ″ to t9 ″ is “e” as shown in FIG. Although it is “f”, the value excluding the low-order X bits becomes the same “a”, and it is regarded as a match, and the control ends. Thereafter, at time t10 ″, a phase difference corresponding to the values “e” and “f” occurs. This phase difference is generated and accumulated every time switching occurs. This FP is sent from the multiplexing circuit 103 to the phase control unit 4. ₁ To the phase control unit 4 ₁ The phase absorption circuit 108 is used as a synchronization source of the PLL circuit 110 of the phase absorption circuit 108 in FIG. ₁₁ 2 ₁₂ After the phase difference is absorbed, the modulator 5 ₁ Is sent out. The phase absorption circuit 108 can absorb the phase up to a certain range of phase difference and can transmit the transmission signal without error even if the in-device synchronous clock source is switched. If the phase absorption range is exceeded, an error occurs in the transmission signal when the clock synchronization source in the apparatus is switched.
[0012]
The second problem is an increase in delay during transmission. The reason is that the phase control unit 4 is used to solve the first problem. ₁ In order to increase the phase absorption range in the internal phase absorption circuit 108, a method of increasing the memory can be considered. However, if the phase absorption range is increased, a large amount of data is written to and read from the memory, which increases the signal delay during multiplexing. Further, even if the memory is increased, it is finite, and if the phase absorption range is exceeded, an error occurs in the transmission signal.
[0013]
The present invention provides an in-device clock switching method and device that solve the above problems.
[0014]
[Means for Solving the Problems]
A clock switching method of the present invention is a clock switching method for switching a clock from a first input interface unit to a second input interface unit in a transmission apparatus, and is a method of switching from a plurality of input signals to the first input interface unit. And selecting one of the plurality of input signals to the second input interface unit as the second synchronous clock source. Sending as a second extraction selection clock; and selecting one of the first extraction selection clock and the second extraction selection clock in the first selection circuit and sending it as a first selection output; The step of selecting either the first extraction selection clock or the second extraction selection clock in the second selection circuit and sending it as the second selection output In the first digital PLL circuit, the first synchronous clock and the first synchronous FP that are synchronized with the first selected output are generated and sent to the first input interface unit and the second input interface unit. In the second digital PLL circuit, the second synchronization clock and the second synchronization FP are generated in synchronization with the second selected output, and the first input interface unit and the second input interface unit A step of sending, and a step of selecting and sending either the first synchronous clock and the first synchronous FP or the second synchronous clock and the second synchronous FP in the first input interface unit; In the second input interface unit, the first synchronous clock and the first synchronous FP, or the second synchronous clock and the second synchronous FP are selected. A step of sending a first synchronization FP Phase of And the phase of the second synchronous FP Control to be the same Generating the first control output , Sending to the first digital PLL circuit; and a first synchronous FP Phase of And the phase of the second synchronous FP Control to be the same Generate a second control output , And sending to the second digital PLL circuit.
[0020]
The clock switching device of the present invention is a clock switching device that switches a clock from a first input interface unit to a second input interface unit in a transmission device, and the first interface unit includes a first extraction selection circuit, A first selection circuit; a first digital PLL circuit; a first clock switching circuit; and a first subordinate control circuit. The second interface unit includes a second extraction selection circuit; , A second digital PLL circuit, a second clock switching circuit, and a second subordinate control circuit, and the first extraction selection circuit has a plurality of inputs to the first input interface unit One of the signals is selected as a first synchronous clock source, and is sent as a first extraction selection clock to the first selection circuit and the second selection circuit. The second extraction selection circuit has a second input Inn One of a plurality of input signals to the face unit is selected as a second synchronous clock source, and is sent as a second extraction selection clock to the first selection circuit and the second selection circuit. The first selection circuit Selects one of the first extraction selection clock and the second extraction selection clock and sends it to the first digital PLL circuit as a first selection output, and the second selection circuit selects the first extraction selection clock. One of the clock and the second extraction selection clock is selected and sent to the second digital PLL circuit as a second selection output. The first digital PLL circuit is synchronized with the first selection output, The first synchronous FP and the first synchronous FP are generated and sent to the first input interface unit and the second input interface unit, and the second digital PLL circuit is synchronized with the second selection output, The synchronous clock and the second synchronous FP are generated and sent to the first clock switching circuit and the second clock switching circuit. The first clock switching circuit includes the first synchronous clock and the first synchronous FP, Alternatively, the second synchronous clock and the second synchronous FP are selected and transmitted, and the second clock switching circuit includes the first synchronous clock and the first synchronous FP, or the second synchronous clock and Select and send one of the second synchronous FP,
The first subordinate control circuit has a first synchronous FP Phase of And the phase of the second synchronous FP Control to be the same Generating the first control output , Send to the first digital PLL circuit,
The second subordinate control circuit has a first synchronous FP Phase of And the phase of the second synchronous FP Control to be the same Generate a second control output , The data is sent to the second digital PLL circuit.
[0021]
In the clock switching device of the present invention, the digital PLL circuit sends out the N-divided output obtained by dividing the selection output of the selection circuit by N (N ≧ 2), and the clock is M (M ≧ 2). Divided Divider M that sends M-divided output, phase comparison of N-divided output and M-divided output, phase comparison circuit that sends phase comparison results, counts phase comparison results, and sends count value An A / D conversion circuit that stores the count value and transmits the stored value as a stored value, a selection circuit T that transmits a selected output of the count value and the stored value as a selected value, and D / A converts the selected value A D / A conversion circuit that generates and sends an analog voltage, a loop filter that suppresses and sends unnecessary frequency components included in the analog voltage, and the clock whose frequency is controlled according to the voltage sent from the loop filter. A voltage control transmitter for sending, a frequency divider P for sending an FP generated by dividing the clock by P (P ≧ 2), a comparison circuit for comparing the count value with the stored value and sending the comparison result; Selected times T, characterized in that it comprises a phase memory circuit, a control circuit for controlling the frequency divider M, the.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described in detail with reference to the drawings. In the clock switching according to the present invention, a clock and a frame pulse (hereinafter referred to as FP) generated by a digital PLL circuit of one input interface unit selected as an in-device synchronous clock source are supplied to the other input interface unit. Are generated by one digital PLL, and the other input interface unit selects the clock and FP supplied by the clock switching circuit (112 in FIG. 2), multiplexes the input signals, and the subordinate control circuit ( 2), a control signal is generated in which the phase of the FP generated by the digital PLL circuit (106 of FIG. 2) has a unique phase relationship with the supply FP, and this control signal is generated by the digital PLL circuit (FIG. 2). 106), the internal clock synchronization source is switched and the input interface section that supplies the clock and FP is switched off. There also occurs, since the FP is in a unique phase relationship, to realize the clock switching no error occurs in the transmission signal.
[0023]
1-4, in a radio transmission apparatus having a working N (N ≧ 2) line for multiplexing and transmitting input signals, the input signal 1 ₁ Since 201 is selected as the in-device clock synchronization source, the input interface unit 2 ₁₁ Becomes the master operation, and the input interface unit 2 ₁₂ Shall be in slave operation. In a steady state, an input signal 1 that is a clock synchronization source in the apparatus ₁ Input interface unit 2 for processing 201 ₁₁ Is the master operation, so the input signal 1 ₁ 201 is converted by the conversion circuit 101, and the phase control unit 4 ₁ Is selected as an in-device clock synchronization source by the extraction selection circuit 104 and the selection circuit 105 using the control signal 221 from the control signal 221 and sent to the digital PLL circuit 106. The digital PLL circuit 106 uses the digital PLL to input signal 1 ₁ A clock and FP synchronized with 201 are generated, and the clock switching circuit 112 and the other input interface unit 2 ₁₂ To the internal clock switching circuit 112. At this time, in the digital PLL circuit 106, an N divided output 401 obtained by dividing the selection output 222 serving as a synchronization source by the divider N301 and an output clock 406 of the voltage control oscillator 311 is divided by M by the divider M302. The phase difference is measured from the peripheral output 402 using the phase comparison circuit 303 and the A / D conversion circuit 306, and stored in the phase storage circuit 307. The clock switching circuit 112 uses the control output 224 from the slave control circuit 113 from the master operation to input interface unit 2. ₁₁ The clock and FP generated in (1) are selected and sent to the multiplexing circuit 103. The control signal 227 of the slave control circuit 113 is input from the master operation to the input interface unit 2. ₁₁ The frequency divider P312 in the digital PLL circuit 106 is not controlled.
On the other hand, the input interface unit 2 ₁₂ Is a slave operation, so the phase control unit 4 ₁ Using the control signal 221 from the input interface unit 2 ₁₁ Are selected and sent to the digital PLL circuit 106. The digital PLL circuit 106 generates a clock and FP synchronized with the selection output 222, and the clock switching circuit 112 and the input interface unit 2. ₁₁ To the internal clock switching circuit 112. At this time, in the digital PLL circuit 106, the input interface unit 2 ₁₁ Similarly, the phase difference is stored in the phase storage circuit 307. The clock switching circuit 112 uses the control output 224 from the subordinate control circuit 113 to input the input interface unit 2. ₁₁ The clock and FP generated in (1) are selected and sent to the multiplexing circuit 103. Further, from the slave operation, the control output 227 of the slave control circuit 113 controls the frequency divider P312 in the digital PLL circuit 106, and the input interface unit 2 ₁₁ The phase of the FP is controlled so as to have a unique phase with the FP.
[0024]
In-device clock synchronization source is input signal 1 ₁ To input signal 1 ₅ When switching occurs in the input interface unit 2 ₁₁ 2 ₁₂ In the digital PLL circuit 106, the control circuit 313 holds the state before the switching of the in-device clock synchronization source using the value stored in the phase storage circuit 307 in the steady state, and the phase control unit 4 ₁ The digital PLL output is switched in the selection circuit 105 from the control signal 221 from the control signal 221, and the N divided output 401 of the frequency divider N 301 after switching the synchronous clock source using the phase comparison circuit 303 and the A / D conversion circuit 306. The phase difference of the M-divided output 402 of the frequency divider M302 is measured, and the phase of the M-divided output 402 of the frequency divider M302 is changed by controlling the frequency divider M302 to match the value stored in the steady state. Take control. When a certain time elapses after the match, the input interface unit 2 ₁₁ In the subordinate control circuit 113, the master operation is switched to the slave operation, and the clock switching circuit 112 outputs the output to the multiplexing circuit 103 to the input interface unit 2. ₁₁ From the digital PLL output 223 of the input interface unit 2 ₁₂ The switching signal to the digital PLL output 229 is sent out. The control output 227 sent to the digital PLL circuit 106 is the input interface unit 2. ₁₁ Phase control is started so as to have a unique phase with the FP.
[0025]
On the other hand, the input interface unit 2 ₁₂ The slave control circuit 113 changes from the slave operation to the master operation, and the clock switching circuit 112 outputs the output to the multiplexing circuit 103 to the input interface unit 2. ₁₁ From the digital PLL output 223 of the input interface unit 2 ₁₂ The switching signal to the digital PLL output 229 is sent out. Further, the FP phase control performed by the control signal 227 sent to the digital PLL circuit 106 is stopped.
[0026]
Thereby, the input interface unit 2 ₁₁ 2 ₁₂ Even if the internal synchronous clock source is switched between the input interface unit 2 ₁₁ 2 ₁₂ By maintaining the output phase of the multiplexing circuit 103 in a unique phase relationship, the phase control unit 4 ₁ Since the phase of the FP is kept within the phase absorption range of the phase absorption circuit 108 even if the in-device synchronous clock source switching occurs in the phase absorption circuit 108, a transmission signal error due to the phase variation of the FP does not occur. In-device clock switching is possible.
[0027]
An apparatus synchronous clock switching method and apparatus according to the present invention provides an internal clock by supplying a clock and FP generated by a digital PLL circuit of one input interface unit selected as an internal clock synchronization source to the other input interface unit. And the FP generated by the other digital PLL circuit is controlled to have a unique phase relationship, so that the phase control unit 4 can be controlled from a plurality of input interface units. ₁ The output phase to can be kept constant. As a result, even if clock switching occurs, the FP of the input interface unit is not affected by the phase control unit 4. ₁ Therefore, switching can be performed without generating an error by clock switching.
[0028]
In order to describe the above-described embodiment of the present invention in more detail, examples of the present invention will be described below with reference to the drawings.
[0029]
First Embodiment: FIG. 1 is a block diagram showing the configuration of a radio transmission apparatus according to an embodiment of the present invention. FIG. 2 shows an input interface unit 2 in the apparatus. ₁₁ 2 ₁₂ FIG. 3 shows the input interface unit 2 ₁₁ 2 ₁₂ FIG. 4 shows a phase control unit 4. ₁ It is.
[0030]
The working first line including the working first radio line in FIG. ₁₁ ~ 1 ₁₄ , Input signal 1 ₁₅ ~ 1 ₁₈ Input interface unit 2 ₁₁ 2 ₁₂ , Phase control unit 4 ₁ , Modulation section 5 ₁ , Transmitter 6 ₁ , Receiver 7 ₁ , Demodulator 8 ₁ , Distribution unit 9 ₁ Output interface unit 10 ₁₁ 10 ₁₂ , Output signal 11 ₁₁ ~ 11 ₁₄ , Output signal 11 ₁₅ ~ 11 ₁₈ It is comprised including. The working second, third, and N lines including the working second, third, and N radio lines have the same configuration.
[0031]
The present invention provides an input interface unit 2 for a working first line including the working first wireless line of FIG. ₁₁ 2 ₁₂ , Phase control unit 4 ₁ , Modulation section 5 ₁ The input interface unit 2 of the working second wireless line, working third wireless line, working Nth wireless line ₂₁ 2 ₂₂ 2 ₃₁ 2 ₃₂ 2 _N1 2 _N2 Etc. have the same configuration and function.
[0032]
Input interface unit 2 ₁₁ 2 ₁₂ In the conversion circuit 101, the input signal 1 ₁ ~ 1 ₄ , Input signal 1 ₅ ~ 1 ₈ Is converted to a unipolar signal that can be easily processed by the apparatus, frame synchronization is established, and a data frame pulse (hereinafter referred to as FP) clock converted to a unipolar signal is sent to the memory circuit 102, Is sent to the extraction selection circuit 104.
[0033]
In the memory circuit 102, the data sent from the conversion circuit 101 is written in the memory, and the data is read by a clock from the multiplexing circuit 103 described later.
[0034]
The multiplexing circuit 103 reads and multiplexes the data in the storage circuit 102 using the clock and FP sent from the clock switching circuit 112 (to be described later), and performs the multiplexing. ₁ To send.
[0035]
In the extraction selection circuit 104, the phase control unit 4 ₁ A plurality of input signals 1 using a control signal (HW (highway) selection signal) 221 from ₁ ~ 1 ₄ (Input signal 1 ₅ ~ 1 ₈ ) Are selected as synchronous clock sources, and the selection circuit 105 and the other input interface unit 2 are selected as the extraction selection clock 220 (extraction selection clock 219). ₁₂ To the selection circuit 105 and input signal 1 ₁ ~ 1 ₄ The extracted clock information 210 indicating whether can be selected is the phase control unit 4 ₁ To send.
[0036]
The selection circuit 105 uses the control signal 221 to select the extraction selection clock 220 of the own panel extraction selection circuit 104 or the other input interface unit 2. ₁₂ One of the extraction selection clocks 219 of the extraction selection circuit 104 is selected and sent to the digital PLL circuit 106 as a selection output 222.
[0037]
The digital PLL circuit 106 generates a clock and FP synchronized with the selection output 222 in a steady state, and generates the digital PLL outputs 223 and 229 as the clock switching circuit 112 and the other input interface unit 2. ₁₂ The control signal 408 is transmitted to the slave control circuit 113 as the control signal 228. When there is a change in the synchronous clock source from the control signal 221, the synchronous clock source is switched while operating using the sampling value stored in the steady state.
[0038]
In the clock switching circuit 112, a clock, FP, or other input interface unit 2 from the digital PLL circuit 106 using a control output 224 from the slave control circuit 113 described later. ₁₂ One of the clock and FP from the internal digital PLL circuit 106 is selected and sent to the multiplexing circuit 103, and the clock switching circuit 112 is connected to the other input interface unit 2. ₁₂ When the clock and FP are selected, the selected FP is sent to the slave control circuit 113.
[0039]
The subordinate control circuit 113 uses a control signal 408 (228) and a control signal 221 of the control circuit 313 to be described later, and when the control signal 221 is an input signal on the own panel side, the master operation (for example, an input interface) 2 ₁₁ ) For selecting the output of the digital PLL circuit 106, and if it is the other input signal, the control output 224 becomes “H” for selecting the output of the digital PLL circuit 106 on the other panel side as a slave operation, and the other input interface Part 2 ₁₂ In the master operation, “L” is sent out in the case of master operation, and “H” control outputs 225 and 226 are sent out in the case of slave operation. The selected FP sent from the clock switching circuit 112 is sent to the digital PLL circuit 106 in the slave operation. Send it out.
[0040]
In the digital PLL circuit 106 (FIG. 3), an N-divided output 401 obtained by dividing the selection output 222 of the selection circuit 105 by N (N ≧ 2) by the frequency divider N301 is sent to the phase comparison circuit 303.
[0041]
The frequency divider M302 sends an M frequency divided output 402 obtained by dividing the output clock 406 of the voltage control oscillator 311 by M (M ≧ 2) to the phase comparison circuit 303. Further, the phase of the M-divided output 402 can be varied by a control signal 410 from the control circuit 313.
[0042]
The phase comparison circuit 303 performs phase comparison with “H” between the waveform rise of the N-divided output 401 and the waveform rise of the M-divided output 402, and sends the phase comparison result 403 to the A / D conversion circuit 306. .
[0043]
The A / D conversion circuit 306 counts while the phase comparison result 403 is “H” using the clock of the transmitter 304, and sends the count value 404 to the phase storage circuit 307, the selection circuit T 308, and the comparison circuit 314. .
[0044]
The timing generation circuit 305 sends a timing signal (timing clock) for determining the operation timing of each circuit to the A / D conversion circuit 306, the phase storage circuit 307, the selection circuit T308, and the control circuit 313.
[0045]
The phase storage circuit 307 has a function of storing the count value 404 in accordance with the timing signal (timing clock) output from the timing generation circuit 305 and holding the value stored in accordance with the control signal 408 from the control circuit 313. The stored value 405 is sent to the circuit T308 and the comparison circuit 314.
[0046]
In the selection circuit T308, output selection of the count value 404 and the storage value 405 is performed by the control signal 408 from the control circuit 313, and the selection value is sent to the D / A conversion circuit 309.
[0047]
The D / A conversion circuit 309 generates an analog voltage by D / A converting the selection value sent from the selection circuit T308 and sends it to the loop filter 310.
[0048]
The loop filter 310 suppresses unnecessary frequency components included in the input analog voltage and sends them to the voltage control transmitter 311.
[0049]
The voltage control oscillator 311 sends an output clock 406, the frequency of which is controlled according to the voltage sent from the loop filter 310, to the frequency divider P312, the frequency divider M302, and the clock switching circuit 112.
[0050]
The frequency divider P312 sends an output FP (frame pulse) 407 generated by dividing the output clock 406 by P (P ≧ 2) to the multiplexing circuit 103 via the clock switching circuit 112. Further, the frequency division counter is reset by the control output 227 from the subordinate control circuit 113.
[0051]
The comparison circuit 314 compares the count value 404 and the stored value 405 except for the lower X (X ≧ 1) bits. When the count value 404 is smaller than the stored value 405, “LT” is obtained. Is sent to the control circuit 313 as “GT”, and in this case, “EQ”.
[0052]
The control circuit 313 outputs the control signal 408 “L” in the steady state, and when the state of the control signal 221 changes, the control signal 408 is set to “H” to shift to the HOLDOVER mode and control is performed to the selection circuit T308. After switching to the stored value 405 side using the signal 408 and keeping the stored value 405 of the phase storage circuit 307 so that the clock does not fluctuate, the count value 404 of the A / D conversion circuit 306 and the stored value 405 are compared. The frequency divider M302 is controlled using the result 409, and is controlled to be the same as the phase state immediately before switching. When the comparison result 409 of the comparison circuit 314 becomes “EQ” and matches, the control signal 408 switches the selection value of the “L” selection circuit T308 from the stored value 405 to the count value 404, and the stored value 405 held in the phase storage circuit 307 is released. To do.
[0053]
Phase control unit 4 shown in FIG. ₁ Then, the phase absorption circuit 108 is connected to the input interface unit 2. ₁₁ Output 209 and input interface unit 2 ₁₂ The output unit 209 absorbs the phase difference by using the clock of the voltage control oscillator 107 to modulate the modulation unit 5. ₁ To send. The selection circuit B 109 receives the input interface unit 2 in response to a control signal from a clock control circuit 111 described later. ₁₁ 2 ₁₂ Either FP is selected and sent to the PLL circuit 110. The PLL circuit 110 sends a control signal synchronized with the FP selected by the selection circuit B 109 to the voltage control oscillator 107. The voltage control oscillator 107 generates a clock synchronized with the control signal of the PLL circuit 110 and sends it to the phase absorption circuit 108. The clock control circuit 111 includes the input interface unit 2 ₁₁ 2 ₁₂ The in-device synchronous clock is determined using the extracted clock information 210 from the data, and the selection result is sent to the selection circuit B109 and the input interface unit 2 ₁₁ 2 ₁₂ (As control signal 221).
[0054]
Next, the circuit operation of FIGS. 1 to 4 will be described together with the timing charts (time charts) of FIGS. In this description, the in-device synchronous clock source switching is input signal 1 ₁₁ To input signal 1 ₁₅ The parentheses for the count value 404 and the stored value 405 are values obtained by removing the lower X (X ≧ 1) bits of the respective values.
[0055]
Input interface unit 2 in steady state ₁₁ Then, the phase control unit 4 ₁ The control signal 221 from the input signal 1 ₁₁ Therefore, the subordinate control circuit 113 performs the master operation, and the other input interface unit 2 ₁₂ The control output 225 to “L” is set to “L”, the control output 224 to the clock switching circuit 112 is set to “L”, and the control output 227 to the digital PLL circuit 106 is set to “H”. In the extraction selection circuit 104, the control signal 221 is input signal 1 ₁₁ Input signal 1 from selection ₁ The unipolar signal 211 is selected, the selection circuit 105 as the extraction selection clock 220 and the other input interface unit 2 ₁₂ To the selection circuit 105.
[0056]
In the selection circuit 105, the control signal 221 is input signal 1 ₁₁ The extraction selection clock 220 is selected from the selection and sent to the digital PLL circuit 106. The clock switching circuit 112 selects the digital PLL output 223 on the own panel side when the control output 224 of the slave control circuit 113 is “L”, and sends it to the multiplexing circuit 103.
[0057]
A frequency divider N301 in the digital PLL circuit 106 (FIG. 3) divides the selection output 222 selected by the selection circuit 105 by N and sends it to the phase comparison circuit 303 as an N divided output 401. The frequency divider M302 divides the output clock 406 of the voltage control oscillator 311 by M and sends the M-frequency divided output 402 to the phase comparison circuit 303.
[0058]
The phase comparison circuit 303 sends the phase comparison result 403 to the A / D conversion circuit 306 with the time θ1 from the rising waveform of the N divided output 401 to the rising waveform of the M divided output 402 being “H”. In the A / D conversion circuit 306, the phase comparison result 403 is counted using the clock of the transmitter 304, converted into a count value 404 "a", and sent to the phase storage circuit 307, the selection circuit T308, and the comparison circuit 314.
[0059]
The phase storage circuit 307 stores the count value 404 "a" and the storage value 405 "a" by the timing signal (timing clock) from the timing generation circuit 305.
[0060]
The selection circuit T308 sends the count value 404 “a” as a selection value to the D / A conversion circuit 309 according to the control signal 408. In the D / A conversion circuit 309, the selection value “a” is voltage-converted by D / A conversion and sent to the loop filter 310. The voltage control oscillator 311 outputs an output clock 406 whose frequency is controlled using a voltage in which unnecessary frequency components are suppressed by the loop filter 310.
[0061]
The frequency divider P312 generates an output FP407 obtained by dividing the output clock 406 by P and sends it to the clock switching circuit 112.
[0062]
One input interface unit 2 ₁₂ Then, the phase control unit 4 ₁ Input signal 1 from control signal 221 from ₁₁ Since the subordinate control circuit 113 is in a slave operation, the other input interface unit 2 is selected. ₁₁ The control output 226 to “H” is set to “H”, the control output 224 to the clock switching circuit 112 is set to “H”, and the control output 227 to the digital PLL circuit 106 is transmitted. In the clock switching circuit 112, the control output 224 is changed from “H” to the other input interface unit 2. ₁₁ Side digital PLL output 223 is selected and sent to the multiplexing circuit 103. The digital PLL circuit 106 includes an input interface unit 2. ₁₁ The frequency divider P312 resets the P frequency division counter using the control output 227 from the subordinate control circuit 113, and the input interface unit 2 ₁₁ The FP is controlled so that the output phase is the same as that of the FP.
[0063]
Here, the input signal 1 ₁₁ To input signal 1 ₁₅ When switching occurs, phase control unit 4 ₁ The control signal 221 from the input signal 1 ₁₁ To input signal 1 ₁₅ To change. Input interface unit 2 ₁₁ Then, when the state change of the control signal 221 is detected, the control circuit 313 in the digital PLL circuit 106 transmits the control signal 408 as “H” at time t 1, so that the storage value 405 is held in the phase storage circuit 307. In the selection circuit T308, the selection value for the D / A conversion circuit 309 is switched from the count value 404 to the stored value 405. The input interface unit 2 is controlled by the control signal 221. ₁₁ Then, the selection circuit 105 outputs the selection output 222 to the input interface unit 2. ₁₁ Extraction selection clock 220 from the other input interface unit 2 ₁₂ Is switched to the extraction selection clock 219. By switching the selection output 222, the N-divided output 401 output at time t2 when the phase of the N-divided output 401 of the frequency divider N301 is in a steady state is output at the position of time t3.
[0064]
The phase comparison circuit 303 sends a phase comparison result 403 in which the phase difference from time t3 to t4 is “H” to the A / D conversion circuit 306. The A / D conversion circuit 306 uses the clock of the oscillator 304. The counted value 404 “b” is sent to the comparison circuit 314. At time t5, the comparison circuit 314 compares the value “B” excluding the lower X bits of the count value 404 “b” and the value “A” excluding the lower X bits of the stored value 405 “a”. The comparison is performed, and a comparison result 409 “LT” indicating that “b” <“a” is smaller than the stored value 405 is sent to the control circuit 313. The control circuit 313 controls the frequency divider M302 based on the comparison result 409 “LT” to change the phase of the M frequency divided output 402 from t7 to t8. The phase comparison circuit 303 sends a phase comparison result 403 in which the phase difference from time t6 to time t8 is “H” to the A / D conversion circuit 306. The A / D conversion circuit 306 uses the clock of the oscillator 304. The counted value 404 “e” is sent to the comparison circuit 314. At time t9, the comparison circuit 314 compares the value “A” obtained by removing the lower X bits of the count value 404 “e” and the value “A” obtained by removing the lower X bits of the stored value 405 “a”. 409 “EQ” is sent to the control circuit 313. The control circuit 313 sends a control signal 408 “L” from the comparison result 409 “EQ”. In the selection circuit T308 from the control signal 408 “L”, the selection value is switched from the storage value 405 to the count value 404. In the phase storage circuit 307, the operation of holding the storage value 405 is canceled, and the timing signal (timing of the timing generation circuit 305) The operation returns to the operation of setting the count value 404 to the stored value 405 according to the clock).
[0065]
On the other hand, input interface 2 ₁₂ In the selection circuit 105, the selection output 222 is sent to the other input interface unit 2. ₁₁ Input interface unit 2 from extraction selection clock 220 ₁₂ Are switched to the extraction selection clock 219 and sent to the digital PLL circuit 106. The digital PLL circuit 106 includes an input interface unit 2 ₁₁ In the same manner as described above, the synchronous clock is switched while maintaining the phase.
[0066]
Input interface unit 2 ₁₁ The subordinate control circuit 113 of the control signal 221 also receives the input signal 1 ₁₁ To input signal 1 ₁₅ As a result, the comparison result 409 of the digital PLL circuit 106 becomes “EQ”, and the master operation is changed to the slave operation at time t11 after a predetermined time has elapsed. ₁₂ The control output 225 to “H” is set to “H”, the control output 224 to the clock switching circuit 112 is set to “H”, and the control output 227 to the digital PLL circuit 106 is transmitted. As a result, the clock switching circuit 112 supplies the clock to the input interface unit 2. ₁₁ Digital PLL output 223 to the other input interface unit 2 ₁₂ Is switched to the digital PLL output 229.
[0067]
Input interface unit 2 ₁₂ The subordinate control circuit 113 of the other input interface unit 2 ₁₁ When the control output 225 to “L” is changed from “L” to “H”, the slave operation becomes the master operation, and the other input interface unit 2 ₁₁ The control output 226 to “L” is set to “L”, the control output 224 to the clock switching circuit 112 is set to “L”, and the control output 227 to the digital PLL circuit 106 is set to “H”. As a result, the clock switching circuit 112 supplies the clock to the other input interface unit 2. ₁₁ From the digital PLL output 223 of the input interface unit 2 ₁₂ Is switched to the digital PLL output 229.
[0068]
Second Embodiment: Next, a second embodiment of the present invention will be described in detail with reference to the drawings. FIG. 7 is a second embodiment of the present invention, and FIG. 8 is a timing chart.
[0069]
Input interface unit 2 ₁₁ The subordinate control circuit 113 includes a control output 225 and the other input interface unit 2. ₁₂ The master operation and the slave operation are controlled using the control output 226 of the subordinate control circuit 113 and the extracted clock information 210 from the extraction selection circuit 104. When the control output 225 is “H”, the control output 226 is “H”, and the extracted clock information 210 can be used by any one of the unipolar signals 211 to 214, the master operation is performed and the control output 225 is set to “L”. “The control output 224 to the clock switching circuit 112 is set to“ L ”, and the control output 227 to the digital PLL circuit 106 is set to“ H ”. When the control output 225 is “H” and the control input 226 is “L”, the slave operation is performed, the control output 225 is “H”, the control output 224 to the clock switching circuit 112 is “H”, and the control output 227 is clocked. The FP input from the switching circuit 112 is sent out. Switching from the master operation to the slave operation occurs because the control output 225 is changed from “L” to “H” after a certain time has elapsed since the extracted clock information 210 sends a signal indicating that all unipolar signals cannot be used. The output 224 is switched from “L” to “H”, and the control output 227 to the digital PLL circuit 106 is switched from “H” to FP input from the clock switching circuit 112.
[0070]
On the other hand, the input interface unit 2 ₁₂ Operates with the same logic, but even if the control output 226 is “H”, the control output 225 is “H”, and the extracted clock information 210 can be used by any one of the unipolar signals 211 to 214, Shall be. Input signal 1 ₁₁ To input signal 1 ₁₅ When switching occurs in the input signal 1 ₁₂ To input signal 1 ₁₄ Is the same operation as in the first embodiment of the present invention when input is interrupted or in an abnormal state. On the other hand, input signal 1 ₁₂ To input signal 1 ₁₄ Is normal, the master interface and the slave operation are not switched at time t11 ′ in FIG. ₁₅ An in-device clock synchronized with is used. The advantage of this embodiment is that the configuration of the subordinate control circuit 113 is simplified.
[0071]
【The invention's effect】
The first effect is that a transmission signal can be transmitted without error even if the in-device clock synchronization source switching between the input interface units occurs. The reason is that the clock switching device according to the present invention makes the internal clock identical by supplying the clock and FP generated by the digital PLL circuit of the input interface unit selected as the internal clock synchronization source to the other input interface unit. By controlling the FP generated by another digital PLL circuit to have a unique phase relationship, the output phase from the plurality of input interface units to the phase control unit is kept constant. As a result, even if clock switching occurs, the FP of the input interface unit can be kept within the phase absorption range of the phase absorption circuit in the phase control unit, so that switching can be performed without generating a transmission signal error due to clock switching. Can do. For this reason, it becomes possible to transmit a transmission signal without error.
[0072]
The second effect is that an unnecessary alarm does not occur. The reason is that, conventionally, an out-of-synchronization alarm or the like is generated in the multiplexing circuit due to switching of the clock in the apparatus, but if the present invention is used, an out-of-synchronization does not occur and an unnecessary alarm does not occur.
[Brief description of the drawings]
FIG. 1 shows the configuration of a radio transmission apparatus having an active N line according to the present invention.
FIG. 2 is an input interface unit according to the first embodiment of the present invention.
FIG. 3 is a digital PLL circuit in the input interface unit of the present invention.
FIG. 4 is a phase controller of the present invention.
FIG. 5 is a clock synchronization circuit operation timing chart in the steady state of the present invention.
FIG. 6 is a clock synchronization circuit operation timing chart during the clock switching operation in the device of the present invention.
FIG. 7 shows an input interface unit according to a second embodiment of the present invention.
FIG. 8 is an operation timing chart of the clock synchronization circuit at the time of the internal clock switching operation according to the second embodiment of the present invention.
FIG. 9 shows an input interface unit according to a conventional example.
FIG. 10 is a digital PLL circuit in an input interface unit according to a conventional example.
FIG. 11 is an operation timing chart of a clock synchronization circuit in a steady state according to a conventional example.
FIG. 12 is an operation timing chart of the clock synchronization circuit at the time of the internal clock switching operation according to the conventional example.
[Explanation of symbols]
1 ₁₁ ~ 1 ₁₄ 1 ₁₅ ~ 1 ₁₈ input signal
1 ₁ ~ 1 ₄ 1 ₅ ~ 1 ₈ input signal
2 ₁₁ 2 ₁₂ Input interface section
4 ₁ Phase controller
5 ₁ Modulator
6 ₁ Transmitter
7 ₁ Receiver
8 ₁ Demodulator
9 ₁ Distribution department
10 ₁₁ 10 ₁₂ Output interface section
11 ₁₁ ~ 11 ₁₄ , 11 ₁₅ ~ 11 ₁₈ Output signal
101 Conversion circuit
102 Memory circuit
103 Multiplexing circuit
104 Extraction selection circuit
105 selection circuit
106 Digital PLL circuit
107 Voltage controlled transmitter
108 Phase absorption circuit
109 Selection circuit B
110 PLL circuit
111 Clock control circuit
112 Clock switching circuit
113 Subordinate control circuit
201 Input signal
209 output
210 Extracted clock information
211-214 Unipolar signal
219, 220 Extraction selection clock
221 Control signal
222 Selection output
223 Digital PLL output
224 Control output
225 Control output
226 Control output
227 Control output
228 control signal
229 Digital PLL output
301 Divider N
302 Divider M
303 Phase comparison circuit
304 transmitter
305 Timing generation circuit
306 A / D conversion circuit
307 Phase memory circuit
308 Selection circuit T
309 D / A conversion circuit
310 Loop filter
311 Voltage controlled transmitter
312 Divider P
401 N frequency division output
402 M frequency division output
403 Phase comparison result
404 count value
405 Memory value
406 output clock
407 output FP
408 Control signal
409 Comparison results
410 Control signal

Claims (3)

A clock switching method for switching a clock from a first input interface unit to a second input interface unit in a transmission apparatus,
Selecting one of a plurality of input signals to the first input interface unit as a first synchronous clock source and sending it as a first extraction selection clock;
Selecting one of a plurality of input signals to the second input interface unit as a second synchronous clock source and sending it as a second extraction selection clock;
In the first selection circuit, selecting one of the first extraction selection clock and the second extraction selection clock and sending it as a first selection output;
In the second selection circuit, selecting either the first extraction selection clock or the second extraction selection clock and sending it as a second selection output;
In the first digital PLL circuit, a first synchronization clock and a first synchronization frame pulse (FP) are generated in synchronization with the first selection output, and the first input interface unit and the second synchronization frame pulse (FP) are generated. Sending to the input interface unit;
In the second digital PLL circuit, a second synchronous clock and a second synchronous FP that are synchronized with the second selected output are generated, and the first input interface unit and the second input interface unit A sending process;
Selecting and transmitting either the first synchronous clock and the first synchronous FP, or the second synchronous clock and the second synchronous FP in the first input interface unit;
Selecting and sending either the first synchronous clock and the first synchronous FP or the second synchronous clock and the second synchronous FP in the second input interface unit;
A step of the first synchronization FP phase and the second synchronization FP phases to generate a first control output for controlling to be the same, and sends it to the first digital PLL circuit,
Said first synchronization FP phase and the second synchronization FP phase generates a second control output for controlling to be the same, and a step of sending to said second digital PLL circuit And a clock switching method. A clock switching device for switching a clock from a first input interface unit to a second input interface unit in a transmission device,
The first interface unit includes a first extraction selection circuit, a first selection circuit, a first digital PLL circuit, a first clock switching circuit, and a first subordinate control circuit,
The second interface unit includes a second extraction selection circuit, a second selection circuit, a second digital PLL circuit, a second clock switching circuit, and a second subordinate control circuit,
The first extraction selection circuit selects one of a plurality of input signals to the first input interface unit as a first synchronous clock source, and uses the first selection circuit as a first extraction selection clock. And sending to the second selection circuit,
The second extraction selection circuit selects one of a plurality of input signals to the second input interface unit as a second synchronous clock source, and uses the first selection circuit as a second extraction selection clock. And sending to the second selection circuit,
The first selection circuit selects one of the first extraction selection clock and the second extraction selection clock and sends it to the first digital PLL circuit as a first selection output;
The second selection circuit selects either the first extraction selection clock or the second extraction selection clock and sends it to the second digital PLL circuit as a second selection output;
The first digital PLL circuit generates a first synchronous clock and a first synchronous FP synchronized with the first selection output, and the first input interface unit and the second input interface unit To
The second digital PLL circuit generates a second synchronous clock and a second synchronous FP synchronized with the second selection output, and the first clock switching circuit and the second clock switching circuit To
The first clock switching circuit selects and sends either the first synchronous clock and the first synchronous FP, or the second synchronous clock and the second synchronous FP,
The second clock switching circuit selects and sends either the first synchronous clock and the first synchronous FP, or the second synchronous clock and the second synchronous FP,
The first dependent control circuit, said first first generates a control output, wherein the synchronized FP phase second synchronization FP phase is controlled to be the same, the first digital PLL To the circuit,
It said second slave control circuit, the first second and generates a control output, wherein the synchronized FP phase second synchronization FP phase is controlled to be the same, the second digital PLL Send to circuit,
A clock switching device. The first and second digital PLL circuits are
A frequency divider N for transmitting an N-divided output obtained by dividing the selection output of the selection circuit by N (N ≧ 2);
A frequency divider M for transmitting an M-divided output obtained by dividing the clock by M (M ≧ 2);
A phase comparison circuit that performs phase comparison of the N-divided output and the M-divided output and sends out a phase comparison result;
An A / D conversion circuit that counts the phase comparison results and sends a count value;
A phase storage circuit for storing the count value and sending it as a stored value;
A selection circuit T for sending a selection output of the count value and the stored value as a selection value;
A D / A conversion circuit for D / A converting the selected value to generate and send an analog voltage;
A loop filter that suppresses and transmits unnecessary frequency components included in the analog voltage;
A voltage controlled oscillator for transmitting the clock whose frequency is controlled according to the voltage transmitted from the loop filter;
A frequency divider P for sending out an FP generated by dividing the clock by P (P ≧ 2);
A comparison circuit that compares the count value with the stored value and sends a comparison result;
A control circuit for controlling the selection circuit T, the phase storage circuit, and the frequency divider M;
The clock switching device according to claim 2, further comprising:

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