JP4360077B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a power semiconductor device such as an insulated gate bipolar transistor (hereinafter referred to as IGBT).
[0002]
[Prior art]
The IGBT is a voltage-driven type element that has a low on-voltage and high-speed switching characteristics, and its application range has expanded from an industrial field such as an inverter to a field of consumer equipment such as a microwave oven. Conventionally, IGBTs have a punch-through (hereinafter referred to as PT) type, non-punch-through (hereinafter referred to as NPT) type, and field stop (hereinafter referred to as FS) type, and an n-channel vertical type. A double diffusion structure is the mainstream.
[0003]
PT type IGBT is p ⁺ N on the semiconductor substrate ⁺ Buffer layer and n ^- The active layer is formed using an epitaxial wafer obtained by epitaxial growth. Therefore, for example, in a device with a withstand voltage of 600 V, the thickness of the active layer is about 70 μm, but the total thickness including the substrate is about 200 to 300 μm.
[0004]
FIG. 29 shows a shallow p with a low dose. ⁺ It is sectional drawing which shows the structure for 1/2 cell of NPT type IGBT which has a collector layer. As shown in FIG. 29, for example, n made of an FZ wafer ^- The semiconductor substrate is an active layer 1 and p is formed on the surface side thereof. ⁺ A base region 2 is selectively formed. The surface layer of the base region 2 has n ⁺ An emitter region 3 is selectively formed. A gate electrode 5 is formed on the substrate surface via a gate oxide film 4.
[0005]
The emitter electrode 6 is in contact with the emitter region 3 and the base region 2 and is insulated from the gate electrode 5 by the interlayer insulating film 7. P on the back of the board ⁺ A collector layer 8 and a collector electrode 9 are formed. In the case of the NPT type, the thickness of the active layer 1 is thicker than that of the PT type, but the entire element is significantly thinner than the PT type element. Moreover, since the FZ substrate is used without using the epitaxial substrate, the cost is low.
[0006]
FIG. 30 is a cross-sectional view showing the configuration of 1/2 cell of FS type IGBT. As shown in FIG. 30, the element structure on the substrate surface side is the same as the NPT type element shown in FIG. On the back side of the substrate, n ^- Active layer 1 and p ⁺ N with the collector layer 8 ⁺ A buffer layer 10 is provided. In the case of the FS type, the thickness of the active layer 1 is about 70 μm (withstand voltage 600 V system), which is the same as that of the PT type, and the thickness of the entire element is about 100 to 200 μm.
[0007]
Recently, in order to further reduce the total loss, an attempt has been made to thin the wafer and reduce the device thickness as much as possible. For example, in the case of an element having a withstand voltage of 600 V, the thickness of the FS-IGBT is assumed to be about 70 μm. When the breakdown voltage class is lowered, the thickness of the element is further reduced. As described below, a method for polishing an FZ wafer and a method for polishing an epitaxial wafer are known as methods for manufacturing such a thickness FS type IGBT or a device similar thereto.
[0008]
FIG. 31 is a diagram showing a manufacturing process of an FS type IGBT using a conventional FZ wafer. As shown in FIG. 31, first, n which becomes the active layer 1 ^- On the surface side of the FZ wafer, a surface-side element structure portion 11 including a base region, an emitter region, a gate oxide film, a gate electrode, an interlayer insulating film, an emitter electrode, and a passivation film is formed (FIG. 1A). Next, the back surface of the wafer is ground by combining a processing method such as back grinding, polishing, or etching, alone or in combination, so that the wafer has a desired thickness, for example, 70 μm (FIG. 31B). In the case of etching, although it is not strictly grinding, in this specification, since means for thinning the wafer is not questioned, grinding including etching is performed.
[0009]
Next, for example, phosphorus (P), which is an n-type impurity, and boron (B), which is a p-type impurity, are ion-implanted from the back surface of the wafer, and a heat treatment (annealing) is performed at 350 to 500 ° C. in an electric furnace. 10 and the collector layer 8 are formed (FIG. 31C). Next, a plurality of metals such as aluminum (Al), titanium (Ti), nickel (Ni), and gold (Au) are vapor-deposited on the back surface of the wafer, that is, the surface of the collector layer 8 to form the collector electrode 9 (FIG. 31 (d)). Finally, the dicing tape 12 is attached to the collector electrode 9 side to perform dicing, and the wafer is cut into a plurality of chips 13 (FIG. 31E).
[0010]
FIG. 32 is a diagram showing a manufacturing process of an FS type IGBT using a conventional epitaxial wafer. As shown in FIG. 32, first, n which becomes the buffer layer 10 ⁺ An epitaxial wafer is prepared by growing an epitaxial layer to be the active layer 1 on a semiconductor substrate, and a base region, an emitter region, a gate oxide film, a gate electrode, an interlayer insulating film, an emitter electrode, A surface-side element structure 11 made of a passivation film is formed (FIG. 1A). The n layer is diffused in the diffusion step when forming the surface-side element structure portion 11. Next, the wafer is made, for example, 70 μm thick by back grinding or the like, and n ⁺ The semiconductor substrate is left to have a thickness of, for example, 10 μm (FIG. 32B).
[0011]
Next, boron, which is a p-type impurity, is ion-implanted from the back surface of the wafer, and annealed at 350 to 500 ° C. in an electric furnace to form the collector layer 8 (FIG. 32C). Next, a collector electrode 9 made of a plurality of metal layers is formed on the surface of the collector layer 8 (FIG. 32D). Finally, dicing is performed by attaching a dicing tape 12, and the wafer is cut into a plurality of chips 13 (FIG. 32E).
[0012]
FIG. 33 is a process diagram for explaining the conventional back grinding process in detail. As shown in FIG. 33, in the back grinding process, first, a protective tape 16 is attached to the surface side of the wafer 15 on which a surface element structure portion (not shown) is formed (FIG. 33A). This is turned upside down and vacuum-sucked onto the suction stand 19 of the back grinding apparatus with the protective tape 16 facing downward (FIG. 33B).
[0013]
Then, back grind. At this time, since the step portion 17 of polyimide constituting the passivation film is formed on the surface of the wafer 15, a recess 18 reflecting the pattern of the step portion 17 is formed on the back surface of the wafer (FIG. 33 (c)). )). After the back grinding, the wafer 15 is removed from the suction table 19 and the protective tape 16 is peeled off (FIG. 33 (d)). In this way, a wafer 15 having a desired thickness is obtained (FIG. 33 (e)).
[0014]
[Problems to be solved by the invention]
However, if an element having a thickness of, for example, about 70 μm is manufactured by the above-described conventional manufacturing method, the wafer after back grinding is too thin, and therefore, when performing ion implantation from the back side of the wafer, the wafer is likely to be broken. is there. Further, when a metal film serving as a collector electrode is deposited on the back surface of the wafer, the metal film becomes a film having a large compressive stress when viewed from the substrate side, and thus there is a problem that the wafer is likely to be cracked.
[0015]
In addition, there is a problem that the wafer is easily broken by the stress generated in the wafer during annealing in the electric furnace. Further, even if the wafer is not cracked, the wafer is greatly warped by the compressive stress, so that there is a problem that dicing becomes difficult. In addition, since the shape of the chip after dicing is distorted, the designed characteristics may not be obtained.
[0016]
Further, in the above-described conventional back grinding process, the back surface of the wafer becomes concave and convex due to the back grinding, and the wafer is cracked deeply particularly in a portion where vacuum suction is strong (see FIG. 33 (e), central recess). There is a problem that it is likely to occur. In addition, since the strength of the outer peripheral portion of the wafer is low, there is a problem that the outer periphery of the wafer is lifted from the suction table of the back grinding apparatus and causes a wafer crack. Moreover, there is a possibility that desired device characteristics cannot be obtained because the back surface of the wafer is locally scraped.
[0017]
The present invention has been made in view of the above problems, and suppresses warping of the wafer and stress acting on the wafer when manufacturing a semiconductor device such as an IGBT having a thin device thickness by back grinding the back surface of the wafer. Accordingly, it is an object of the present invention to provide a method for manufacturing a semiconductor element that can manufacture a semiconductor element while preventing the wafer from being broken.
[0018]
Another object of the present invention is to provide a method of manufacturing a semiconductor device that prevents the wafer from cracking by preventing local chipping on the back surface of the wafer during back grinding.
[0019]
[Means for Solving the Problems]
In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention includes a step of manufacturing a surface element structure portion of a semiconductor element on a surface of a semiconductor wafer, and a step of manufacturing the surface element structure portion of the semiconductor wafer. Side surface High Rigid adhesive sheet Paste Process, A step of further bonding an adhesive sheet for particle removal to the high-rigidity adhesive sheet; Above High rigidity Adhesive sheet And the particle removing adhesive sheet The Pasted Grinding the back surface of the semiconductor wafer in a state so that the surface on the back surface side of the semiconductor wafer is flat; The step of peeling the adhesive sheet for particle removal, and after peeling the adhesive sheet for particle removal, Ion implantation, the implanted impurity is activated by laser annealing, and a back surface structure is fabricated so that no stress is generated on the ground surface of the semiconductor wafer, and the back surface structure is fabricated. From the semiconductor wafer High rigidity A step of peeling the adhesive sheet; High rigidity Adhesive sheet After peeling And a step of cutting the semiconductor wafer into chips.
[0020]
In the present invention, when the back surface structure is manufactured, ion implantation may be performed, and the implanted impurities may be activated by a laser annealing method.
[0023]
In this invention, after affixing the adhesive sheet to the semiconductor wafer, further affixing an adhesive sheet for particle removal to the adhesive sheet, and after grinding the back surface of the wafer, after peeling off the adhesive sheet for particle removal, It is good also as a structure which produces a back surface structure.
[0024]
According to the present invention, after the surface element structure portion of the semiconductor element is formed on the surface side of the semiconductor wafer, the high-rigidity adhesive sheet is pasted on the surface, and in this state, the back grinding is performed to thin the wafer. By performing the processing on the wafer back surface, the warp of the wafer and the stress acting on the wafer during the processing on the wafer back surface are suppressed.
[0025]
In addition, according to the present invention, the backside grinding is performed with the high-rigidity adhesive sheet and the particle removal adhesive sheet attached to the back surface of the semiconductor wafer, and after the backside grinding is finished, the particle removal adhesive sheet is peeled off before the back surface structure. Thus, particles such as shavings and other dust generated during grinding of the back surface of the wafer are removed before the back surface structure is manufactured.
[0030]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the embodiment, a case where an IGBT is manufactured by the method of the present invention will be described as an example. In the following description of each embodiment and the accompanying drawings, the same reference numerals are assigned to the same components.
[0031]
Embodiment 1 FIG.
1 and 2 are diagrams showing a manufacturing process of the method for manufacturing a semiconductor device according to the first embodiment of the present invention. First, n ^- On the surface side of the FZ wafer 21, SiO ₂ A gate electrode made of polysilicon and the like is deposited and processed. Then, an interlayer insulating film such as BPSG is deposited on the surface and processed to produce an insulated gate structure. Next, P ⁺ Forming a base layer with n ⁺ An emitter layer is formed.
[0032]
Then, a surface electrode made of an Al—Si film, that is, an emitter electrode is formed, and heat treatment is performed at about 400 to 500 ° C. to make the Al—Si film a low resistance wiring having stable bonding. A polyimide passivation film is laminated on the entire surface, and a surface-side element structure portion 22 similar to the structure shown in FIG. 30 is completed (FIG. 1A). In the present specification, the surface of the wafer 21 on the side where the surface-side element structure 22 is formed is referred to as a wafer surface, and the opposite surface is referred to as a wafer back surface. In FIG. 1 and FIG. 2, the detailed configuration of the surface side element structure portion 22 is not shown.
[0033]
Next, the wafer 21 is turned over, and the support substrate 32 is bonded to the surface of the surface side element structure portion 22 via a double-sided adhesive type adhesive sheet 31 (FIG. 1B). Here, for example, a quartz glass wafer that transmits UV light is used as the support substrate 32. Further, as the adhesive sheet 31, for example, a high-rigidity UV tape type sheet or a heat-resistant UV tape type sheet that can be peeled off when the adhesive is cured by UV light irradiation, or a heat-foamed tape type sheet that can be peeled off by heating foaming. Use one that does not contain air bubbles during bonding. The thickness of the adhesive sheet 31 is suitably about 100 μm, for example. Moreover, the adhesive sheet 31 has a high heat-resistant temperature, little outgas, and is easy to peel off.
[0034]
Next, with the support substrate 32 bonded, the back surface of the wafer is ground by back grinding, etching, or the like, so that the total thickness of the wafer including the surface side element structure 22 is set to a desired thickness, for example, 70 μm (FIG. 1 ( c)). Next, for example, phosphorus, which is an n-type impurity, is applied from the back surface of the wafer 21 at a dose of 1 × 10, for example. ¹¹ ~ 1x10 ¹³ cm ^-2 Then, ion implantation is performed at an acceleration voltage of, for example, 200 k to 6 MeV. Subsequently, from the back surface of the wafer 21, for example, boron, which is a p-type impurity, has a dose amount of, for example, 1 × 10. ¹³ ~ 1x10 ¹⁵ cm ^-2 Then, ion implantation is performed at an acceleration voltage of 20 k to 100 keV, for example.
[0035]
After that, annealing is performed by irradiating the back surface of the wafer with a laser to form a buffer layer. ⁺ P to be layer 23 and collector layer ⁺ The layer 24 is formed (FIG. 2A). Although not particularly limited, for example, a YAG third harmonic (YAG3ω) pulse laser (wavelength: 355 nm, half width: 100 to 500 ns, frequency: 500 Hz) is used as the laser here. Then, for example, a single irradiation area is about 1 mm square, and irradiation is performed with 50% to 90% overlap. The reason for using the third harmonic of YAG is that deep n ⁺ This is because the layer 23 can be formed. In addition, this laser annealing allows p ⁺ Layers 24 and n ⁺ Only the layer 23 can be activated, and heat treatment can be performed regardless of the heat-resistant temperature of the adhesive sheet 31.
[0036]
Next, a plurality of metals such as aluminum, titanium, nickel, and gold are vapor-deposited on the back surface of the wafer to form a back surface electrode 25 that serves as a collector electrode (FIG. 2B). Here, it is appropriate to deposit a metal film by a low temperature sputtering method. The reason is that the heat-resistant temperature of the adhesive sheet 31 is approximately 100 ° C. or less for a high-rigidity UV tape-type sheet, 200 ° C. or less for a heat-resistant UV tape-type sheet, and 150 ° C. or less for a heated foam tape-type sheet. Therefore, it is desirable that the temperature during film formation is 100 ° C. or lower.
[0037]
Next, a general dicing tape 26 is attached to the back surface of the wafer. Then, UV light is irradiated from the support substrate 32 side, the adhesive sheet 31 is peeled off at the interface with the passivation film of the surface side element structure portion 22, and the adhesive sheet 31 and the support substrate 32 are removed (FIG. 2C). At that time, care should be taken not to leave an adhesive residue of the adhesive sheet 31 on the surface side element structure 22. When the adhesive sheet 31 is a heat-foamed tape-type sheet, the adhesive sheet 31 is peeled off by heat foaming instead of UV light irradiation. Thereafter, the wafer 21 is cut into a plurality of chips 27 (FIG. 2D). Although not shown, each chip 27 is soldered to a fixing member such as a wiring board via the back electrode 25. An aluminum wire electrode is fixed to the electrode on the wafer surface side of each chip 27 by an ultrasonic wire bonding apparatus.
[0038]
According to the first embodiment described above, after the front surface side element structure portion 22 is formed, the support substrate 32 is bonded to the surface, the back grinding is performed in this state, the wafer 21 is thinned, and then the processing on the back surface of the wafer is performed. Therefore, it is possible to suppress the warpage of the wafer 21 and the stress acting on the wafer 21 during the processing on the back surface of the wafer. In addition, by adopting laser annealing instead of electric furnace annealing, which is a source of stress generation, stress acting on the wafer 21 can be suppressed. Therefore, it is possible to prevent the wafer 21 from being cracked during the processing on the wafer back surface. Further, since the warpage of the wafer 21 is reduced, dicing can be easily performed and device characteristics as designed can be obtained. Also, by performing laser annealing, p ⁺ Since the concentration of the layer 24 can be increased, the on-voltage can be reduced.
[0039]
In the first embodiment described above, when a heat-foamed tape-type sheet is used as the adhesive sheet 31, the support substrate 32 does not need to transmit UV light, so that UV, such as metal, ceramic, or hard plastic, is used. It may be made of a material that does not transmit light. In addition, the adhesive sheet 31 may have a UV curable adhesive on both sides, a heat-foamed adhesive on both sides, or a surface on the support substrate 32 side and an element side surface. Each may be a UV curable type and a heated foam type, or vice versa.
[0040]
In the case of manufacturing an NPT type IGBT, in Embodiment 1, n ⁺ An ion implantation step of n-type impurities (phosphorus) for forming the layer 23 may be omitted. In that case, the laser used for laser annealing on the back surface of the wafer may be an XeF pulse laser (wavelength: 351 nm, half width: 14 ns) having a short half width, or an XeCl pulse laser (wavelength: 308 nm, half width: 49 ns). If these lasers, or YAG second harmonic (YAG2ω) and third harmonic (YAG3ω) pulse lasers are used, p ⁺ Only layer 24 can be activated.
[0041]
Embodiment 2. FIG.
3 and 4 are diagrams showing a manufacturing process of the semiconductor element manufacturing method according to the second embodiment of the present invention. In the second embodiment, an n-doped epitaxial wafer is used. First, n ⁺ On the surface side of the epitaxial wafer on which the epitaxial layer 42 has been grown on the semiconductor substrate 41, that is, on the surface of the epitaxial layer 42, the same surface side element structure portion as that shown in FIG. 22 is produced (FIG. 3A). The n layer is diffused in the diffusion process when the surface-side element structure 22 is manufactured. 3 and 4, the detailed configuration of the surface-side element structure 22 is not shown.
[0042]
Next, the wafer is turned over, and the support substrate 32 is bonded to the surface of the surface-side element structure 22 via the adhesive sheet 31 (FIG. 3B). Since the adhesive sheet 31 and the support substrate 32 are the same as those in the first embodiment, a duplicate description is omitted. However, in the second embodiment, the thickness of the support substrate 32 is, for example, 625 μm.
[0043]
Next, with the support substrate 32 bonded, the back surface of the wafer is ground by back grinding, etching, or the like, so that the total thickness of the wafer including the surface-side element structure 22 is a desired thickness, for example, 70 μm, and n ⁺ The semiconductor substrate 41 is left with a thickness of 10 μm, for example (FIG. 3C). Next, from the back surface of the wafer, for example, boron which is a p-type impurity, the dose amount is, for example, 1 × 10. ¹⁴ ~ 1x10 ¹⁵ cm ^-2 Then, ion implantation is performed at an acceleration voltage of 20 k to 100 keV, for example.
[0044]
After that, annealing is performed by irradiating the back surface of the wafer with a laser to form a collector layer. ⁺ The layer 24 is formed (FIG. 4A). Although not particularly limited, here, a XeCl pulse laser (wavelength: 308 nm, half width: 49 ns, frequency: 100 Hz) is used as the laser. Then, for example, a single irradiation area is about 1 mm square, and irradiation is performed with 50% to 90% overlap. By this laser annealing, p on the backside of the wafer ⁺ Only the layer 24 can be activated, and heat treatment can be performed regardless of the heat-resistant temperature of the adhesive sheet 31. In place of XeCl, YAG2ω, YAG3ω, or XeF may be used.
[0045]
Next, for the same reason as in the first embodiment, a back electrode 25 serving as a collector electrode is formed on the back surface of the wafer by, for example, a low temperature sputtering method (FIG. 4B). Then, a general dicing tape 26 is attached to the back surface of the wafer, and the adhesive sheet 31 is peeled off from the front surface side element structure portion 22 by irradiation with UV light, and the adhesive sheet 31 and the support substrate 32 are removed (FIG. 4C). ). In addition, when the heat foaming type adhesive sheet 31 is used, the adhesive sheet 31 is peeled off by heat foaming. Thereafter, the wafer is cut into a plurality of chips 27 (FIG. 4D). Although not shown, the back electrode 25 of each chip 27 is soldered to a fixing member such as a wiring board, and an aluminum wire electrode is fixed to the electrode on the wafer surface side by an ultrasonic wire bonding apparatus.
[0046]
According to the second embodiment described above, similar to the first embodiment, it is possible to suppress the warpage of the wafer and the stress acting on the wafer during the processing on the wafer back surface, and also the laser annealing. By adopting, the stress acting on the wafer can be suppressed, so that the wafer can be prevented from cracking during the processing on the wafer back surface. Further, dicing is easy and device characteristics as designed can be obtained. Also, p by laser annealing ⁺ The on-voltage can be reduced by increasing the concentration of the layer 24. Note that according to the second embodiment, an NPT type IGBT can be manufactured, and the same effect can be obtained in that case.
[0047]
Embodiment 3 FIG.
5 and 6 are diagrams showing a manufacturing process of the method for manufacturing a semiconductor device according to the third embodiment of the present invention. First, n ^- On the surface side of the FZ wafer 21, a surface-side element structure 22 having the same configuration as that shown in FIG. 30 is fabricated in the same manner as in the first embodiment (FIG. 5A). 5 and 6, the detailed configuration of the surface side element structure portion 22 is not shown.
[0048]
Next, the wafer 21 is turned over, and a high-rigidity adhesive sheet 51 is attached to the surface of the surface-side element structure portion 22 (FIG. 5B). As a base material of the high-rigidity adhesive sheet 51, for example, PET (polyethylene terephthalate) may be used. The elastic modulus of the base material of the high-rigidity adhesive sheet 51 is suitably 2 to 5 Gpa. Moreover, it is appropriate that the thickness of the base material of the high-rigidity adhesive sheet 51 is 50 μm or more. The reason is that rigidity ratio≈thickness × elastic modulus, but the rigidity must be increased in order to eliminate cracks in the wafer transfer process (to prevent the wafer from sagging). For that purpose, in the case of PET, the above elastic modulus and thickness are required.
[0049]
Further, as the adhesive of the high-rigidity adhesive sheet 51, an acrylic UV curable adhesive that can be cured and peeled off by irradiation with UV light may be used. Further, as the pressure-sensitive adhesive, a urethane-based heat-foamable pressure-sensitive adhesive that can be peeled off by heat foaming can also be used. Alternatively, a visible light curable pressure sensitive adhesive that can be cured and peeled off by irradiation with visible light can be used as the pressure sensitive adhesive.
[0050]
Next, with the high-rigidity adhesive sheet 51 attached, the back surface of the wafer is ground by back grinding, etching, or the like, so that the total thickness of the wafer including the front-side element structure 22 is set to a desired thickness, for example, 70 μm ( FIG. 5 (c)). Next, for example, phosphorus, which is an n-type impurity, is applied from the back surface of the wafer 21 at a dose of 1 × 10, for example. ¹¹ ~ 1x10 ¹³ cm ^-2 Then, ion implantation is performed at an acceleration voltage of, for example, 200 k to 6 MeV. Subsequently, from the back surface of the wafer 21, for example, boron, which is a p-type impurity, has a dose amount of, for example, 1 × 10. ¹³ ~ 1x10 ¹⁵ cm ^-2 Then, ion implantation is performed at an acceleration voltage of 20 k to 100 keV, for example.
[0051]
After that, annealing is performed by irradiating the back surface of the wafer with a laser to form a buffer layer. ⁺ P to be layer 23 and collector layer ⁺ The layer 24 is formed (FIG. 6A). Although there is no particular limitation, a deep n is used here as the laser as in the first embodiment. ⁺ A YAG third harmonic (YAG3ω) pulse laser capable of forming the layer 23 is used. Irradiation conditions and the like are the same as those in the first embodiment. By this laser annealing, p on the backside of the wafer ⁺ Layers 24 and n ⁺ Since only the layer 23 can be activated, heat treatment can be performed regardless of the heat resistant temperature of the high-rigidity adhesive sheet 51.
[0052]
Next, a back electrode 25 serving as a collector electrode is formed on the back surface of the wafer in the same manner as in the first embodiment, for example, by a low temperature sputtering method (FIG. 6B). Here, the temperature during film formation is desirably 100 ° C. or lower. The reason is that the heat-resistant temperature of the high-rigidity adhesive sheet 51 is approximately 100 ° C. or less for the UV curable sheet, 150 ° C. or less for the heat-foamed sheet, and 100 ° C. or less for the visible light curable sheet. Because there is.
[0053]
Next, a general dicing tape 26 is attached to the back surface of the wafer. Then, UV light is irradiated from the high-rigidity adhesive sheet 51 side, the high-rigidity adhesive sheet 51 is peeled off at the interface with the passivation film of the surface-side element structure portion 22, and the high-rigidity adhesive sheet 51 is removed (FIG. 6C). ). At that time, care should be taken so that the adhesive residue of the high-rigidity adhesive sheet 51 does not remain on the surface-side element structure 22.
[0054]
If the high-rigidity adhesive sheet 51 uses a heat-foaming pressure-sensitive adhesive, the high-rigidity adhesive sheet 51 is peeled off by heat foaming instead of UV light irradiation. When the high-rigidity adhesive sheet 51 uses a visible light curable pressure-sensitive adhesive, the high-rigidity adhesive sheet 51 is peeled off by irradiating visible light. Thereafter, the wafer 21 is cut into a plurality of chips 27 (FIG. 6D). Although not shown, the back electrode 25 of each chip 27 is soldered to a fixing member such as a wiring board, and an aluminum wire electrode is fixed to the electrode on the wafer surface side by an ultrasonic wire bonding apparatus.
[0055]
According to the third embodiment described above, after forming the surface-side element structure 22, the high-rigidity adhesive sheet 51 is bonded to the surface, and in this state, the back grinding is performed to thin the wafer 21, and then the wafer back surface Therefore, the warping of the wafer 21 and the stress acting on the wafer 21 during the processing on the back surface of the wafer can be suppressed. In addition, by adopting laser annealing, the stress acting on the wafer 21 can be suppressed, so that the wafer 21 can be prevented from cracking during the processing on the wafer back surface. Further, dicing is easy and device characteristics as designed can be obtained. Also, p by laser annealing ⁺ The on-voltage can be reduced by increasing the concentration of the layer 24.
[0056]
Note that in the case where an NPT type IGBT is manufactured, in Embodiment 3, n ⁺ An ion implantation step of n-type impurities (phosphorus) for forming the layer 23 may be omitted. In that case, laser annealing of the back surface of the wafer may be performed using a XeF pulse laser or a XeCl pulse laser. If these lasers, or YAG second harmonic (YAG2ω) and third harmonic (YAG3ω) pulse lasers are used, p ⁺ Only layer 24 can be activated.
[0057]
Embodiment 4 FIG.
7 and 8 are diagrams showing a manufacturing process of the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention. In the fourth embodiment, an n-doped epitaxial wafer is used. First, n ⁺ On the surface of the epitaxial layer 42 grown on the semiconductor substrate 41, a surface-side element structure portion 22 having the same configuration as that shown in FIG. 30 is fabricated in the same manner as in the first embodiment (FIG. 7A). The n layer is diffused in the diffusion process when the surface-side element structure 22 is manufactured. 7 and 8, the detailed configuration of the surface-side element structure 22 is not shown.
[0058]
Next, the wafer is turned over, and a high-rigidity adhesive sheet 51 is attached to the surface of the surface-side element structure portion 22 (FIG. 7B). Since the high-rigidity adhesive sheet 51 is the same as that of the third embodiment, a duplicate description is omitted. Next, with the high-rigidity adhesive sheet 51 bonded, the back surface of the wafer is ground by back grinding, etching, or the like, so that the entire thickness of the wafer including the front-side element structure 22 is a desired thickness, for example, 70 μm, and n ⁺ The semiconductor substrate 41 is left with a thickness of 10 μm, for example (FIG. 7C). Next, from the back surface of the wafer, for example, boron which is a p-type impurity, the dose amount is, for example, 1 × 10. ¹³ ~ 1x10 ¹⁵ cm ^-2 Then, ion implantation is performed at an acceleration voltage of 20 k to 100 keV, for example.
[0059]
After that, annealing is performed by irradiating the back surface of the wafer with a laser to form a collector layer. ⁺ The layer 24 is formed (FIG. 8A). Although not particularly limited, here, a XeCl pulse laser is used as the laser, as in the second embodiment. Irradiation conditions and the like are the same as those in the second embodiment. By this laser annealing, p on the backside of the wafer ⁺ Since only the layer 24 can be activated, heat treatment can be performed regardless of the heat-resistant temperature of the high-rigidity adhesive sheet 51. In place of XeCl, YAG2ω, YAG3ω, or XeF may be used.
[0060]
Next, a back electrode 25 serving as a collector electrode is formed on the back surface of the wafer by the low temperature sputtering method for the same reason as in the third embodiment (FIG. 8B). Then, a general dicing tape 26 is attached to the rear surface of the wafer, and the high-rigidity adhesive sheet 51 is removed from the front-side element structure portion 22 by irradiation with UV light, thereby removing the high-rigidity adhesive sheet 51 (FIG. 8C). ). In the case of the high-rigidity adhesive sheet 51 using the heat-foaming pressure-sensitive adhesive, the high-rigidity adhesive sheet 51 is peeled off by heat foaming. Thereafter, the wafer is cut into a plurality of chips 27 (FIG. 8D). Although not shown, the back electrode 25 of each chip 27 is soldered to a fixing member such as a wiring board, and an aluminum wire electrode is fixed to the electrode on the wafer surface side by an ultrasonic wire bonding apparatus.
[0061]
According to the above-described fourth embodiment, similarly to the third embodiment, it is possible to suppress the warpage of the wafer during the processing on the wafer back surface and the stress acting on the wafer. By adopting, the stress acting on the wafer can be suppressed, so that the wafer can be prevented from cracking during the processing on the wafer back surface. Further, dicing is easy and device characteristics as designed can be obtained. Also, p by laser annealing ⁺ The on-voltage can be reduced by increasing the concentration of the layer 24. Note that according to the fourth embodiment, an NPT type IGBT can be manufactured, and in this case, the same effect can be obtained.
[0062]
Embodiment 5 FIG.
FIG. 9 is a diagram showing a part of a manufacturing process of the method for manufacturing a semiconductor device according to the fifth embodiment of the present invention. First, n ^- On the surface side of the FZ wafer 21, as in the first embodiment, a surface-side element structure portion 22 (detailed configuration is not shown) similar to the configuration shown in FIG. 30 is produced (FIG. 9A). .
[0063]
Next, the wafer 21 is turned over, and a high-rigidity adhesive sheet 51 is attached to the surface of the surface-side element structure 22. Since the high-rigidity adhesive sheet 51 is the same as that of the third embodiment, a duplicate description is omitted. Further, the particle removing adhesive sheet 52 is attached to the surface of the high-rigidity adhesive sheet 51 (FIG. 9B). Examples of the particle removing adhesive sheet 52 include a UV curable type that can be peeled off by curing with UV light, a heated foam type that can be peeled off by heating foam, a visible light curable type that can be peeled off by curing with visible light, or A mechanically peelable type film-like adhesive sheet can be used.
[0064]
Next, with the high-rigidity adhesive sheet 51 and the particle removal adhesive sheet 52 attached, the back surface of the wafer is ground by back grinding, etching, or the like, so that the thickness of the entire wafer including the front-side element structure 22 is set to a desired thickness. For example, the thickness is set to 70 μm (FIG. 9C). Thereafter, according to the type of the particle removing adhesive sheet 52, the particle removing adhesive sheet 52 is peeled off by UV light irradiation, heat foaming, visible light irradiation, or mechanically, and the particle removing adhesive sheet 52 is removed. Remove. The high-rigidity adhesive sheet 51 remains adhered (FIG. 9 (d)). Since the subsequent processes are the same as those in FIG. 6 and subsequent figures of the third embodiment, the description thereof is omitted.
[0065]
According to the above-described fifth embodiment, similarly to the third embodiment, wafer cracking can be prevented, dicing is easy, device characteristics as designed can be obtained, and ON voltage can be reduced. In addition to the above effects, by removing the particle removal adhesive sheet 52 after grinding the wafer back surface and then performing ion implantation, particles such as shavings and other dust generated during grinding of the wafer back surface are removed before ion implantation. Since it can be removed, it is possible to prevent the occurrence of defective products due to particles.
[0066]
Embodiment 6 FIG.
FIG. 10 is a diagram showing a part of the manufacturing process of the method for manufacturing a semiconductor device according to the sixth embodiment of the present invention. In the sixth embodiment, an n-doped epitaxial wafer is used. First, n ⁺ On the surface of the epitaxial layer 42 grown on the semiconductor substrate 41, the surface-side element structure portion 22 (detailed configuration is not shown) similar to the configuration shown in FIG. FIG. 10 (a)). The n layer is diffused in the diffusion process when the surface-side element structure 22 is manufactured.
[0067]
Next, the wafer is turned over, and a high-rigidity adhesive sheet 51 is attached to the surface of the surface-side element structure portion 22, and further, a particle removal adhesive sheet 52 is attached to the surface of the high-rigidity adhesive sheet 51 (FIG. 10B). )). The high-rigidity adhesive sheet 51 and the particle removal adhesive sheet 52 are the same as those in the third embodiment and the fifth embodiment, respectively, and thus redundant description is omitted. Next, in this state, the back surface of the wafer is ground by back grinding, etching, or the like, so that the entire thickness of the wafer including the surface side element structure portion 22 is a desired thickness, for example, 70 μm, and n ⁺ The semiconductor substrate 41 is left with a thickness of, for example, 10 μm (FIG. 10C).
[0068]
Thereafter, the particle removing adhesive sheet 52 is peeled from the high-rigidity adhesive sheet 51, and the particle removing adhesive sheet 52 is removed. The high-rigidity adhesive sheet 51 remains adhered (FIG. 10 (d)). The subsequent processes are the same as those in FIG.
[0069]
According to the above-described sixth embodiment, as in the third embodiment, wafer cracking can be prevented, dicing is easy, device characteristics as designed can be obtained, and ON voltage can be reduced. In addition to the above effects, by removing the particle removal adhesive sheet 52 after grinding the wafer back surface and then performing ion implantation, particles such as shavings and other dust generated during grinding of the wafer back surface are removed before ion implantation. Since it can be removed, it is possible to prevent the occurrence of defective products due to particles.
[0070]
Embodiment 7 FIG.
FIG. 11 is a process diagram for explaining in detail the back grinding process of the semiconductor device manufacturing method according to the seventh exemplary embodiment of the present invention. First, on the surface of the semiconductor wafer 61, a surface-side element structure (not shown) similar to the configuration shown in FIG. A stepped portion 62 made of polyimide or the like constituting the passivation film is formed on the surface after the fabrication of the surface side element structure portion (not shown) (FIG. 11A).
[0071]
Next, a filler 63 is filled in the groove portion between the step portion 62 and the step portion 62 so as to fill the groove portion and flatten the surface (FIG. 11B). As the filler 63, for example, an adhesive that can be peeled off by heating and foaming is used. The pressure-sensitive adhesive can be filled by a doctor blade method, a spin coating method, a screen printing method, or the like as long as the groove portion has a width of about 50 to 100 μm and a depth of about 10 μm.
[0072]
Next, a protective tape 64 having a general thickness (for example, about 50 μm) is attached to the surface flattened by the filling of the filler 63 (FIG. 11C). The tape material is generally a resin substrate such as EVA (ethylene-vinyl acetate copolymer), PO (polyolefin) resin, or PET. Then, the wafer 61 is attached to the suction stand 65 of the back grinding apparatus with the protective tape 64 facing down (FIG. 11 (d)), and back grinding is performed (FIG. 11 (e)). After the back grinding, the wafer 61 is removed from the suction table 65 (FIG. 11 (f)).
[0073]
Next, for example, the semiconductor wafer 61 is placed on a hot plate (not shown) and heated to, for example, about 150 ° C. to foam the foam-peelable filler 63, and the protective tape 64 is peeled off together with the filler 63 (FIG. 11). (G)). Thereafter, if necessary, surface treatment on the back side of the wafer is performed by etching. Then, as in the first to sixth embodiments, processing on the back side of the wafer such as ion implantation, annealing, and formation of the back electrode is performed, and the wafer is cut into chips by dicing.
[0074]
According to the above-described seventh embodiment, after the surface-side element structure portion is formed, the surface of the step portion 62 is reflected on the back surface of the wafer 61 by performing the back grinding after the surface is flattened with the filler 63. The back surface can be ground flat without causing it to occur. Further, since the outer peripheral portion of the wafer is reinforced by the filler 63, it is possible to prevent the outer periphery of the wafer 61 from being lifted from the suction table of the back grinding apparatus during back grinding. Therefore, it is possible to prevent the wafer from cracking. In addition, since the back surface of the wafer 61 can be prevented from being locally scraped, desired device characteristics can be obtained.
[0075]
Note that an adhesive that can be cured and peeled off by irradiation with UV light may be used as the filler 63, and the protective tape 64 may be peeled off together with the adhesive by irradiating with UV light after completion of back grinding. Alternatively, a resist agent or polyimide may be used as the filler 63, and in that case, after removing the protective tape 64, the resist or polyimide may be removed using those stripping solutions.
[0076]
Embodiment 8 FIG.
FIG. 12 is a process diagram for explaining in detail the back grinding process of the semiconductor device manufacturing method according to the eighth exemplary embodiment of the present invention. First, on the surface of the semiconductor wafer 61, a surface-side element structure (not shown) similar to the configuration shown in FIG. A stepped portion 62 made of polyimide or the like constituting the passivation film is formed on the surface after the fabrication of the surface side element structure portion (not shown) (FIG. 12A).
[0077]
Next, a protective tape 66 made of a resin such as EVA, PO, or PET, which is thicker than a general thickness, is attached from above the stepped portion 62 (FIG. 12B). In addition, as the protective tape for back grind based on EVA (ethylene-vinyl acetate copolymer), trade names BT-150E-AL and BT-150E-FL manufactured by Nitto Denko Corporation can be used.
[0078]
Here, it is appropriate that the thickness of the protective tape 66 is 150 to 200 μm. The reason for this is shown in FIG. 13 as a result of the inventors examining the uniformity of the thickness in the wafer plane by setting the thickness of the protective tape to 30 μm, 50 μm, 100 μm, 150 μm, 175 μm, 200 μm, 250 μm, and 300 μm. As described above, when the thickness of the tape is 150 to 200 μm, the variation in the wafer in-plane thickness is 3 μm or less which can maintain the device performance.
[0079]
If the protective tape is thinner than 150 μm, the pattern due to the stepped portion 62 on the wafer surface cannot be sufficiently absorbed, so that it is considered that the variation in the wafer in-plane thickness becomes large. On the other hand, when the protective tape is thicker than 200 μm, it is considered that the variation in the wafer in-plane thickness is deteriorated due to the variation in the thickness of the tape itself or the variation due to the pressing of the tape.
[0080]
After affixing the protective tape 66, the wafer 61 is attached to the suction stand 65 of the back grinding apparatus with the protective tape 66 facing down (FIG. 12C), and back grinding is performed (FIG. 12D). At this time, a recess 67 slightly reflecting the pattern of the stepped portion 62 is formed on the back surface of the wafer. As is apparent from FIG. 13, the depth of the recess 67 is about 3 μm. The effect is very small. In addition, the influence on device characteristics is extremely small.
[0081]
After the back grinding, the wafer 61 is removed from the suction table 65 and the protective tape 66 is peeled off (FIG. 12E). Thereafter, if necessary, surface treatment on the back side of the wafer is performed by etching. Then, as in the first to sixth embodiments, processing on the back side of the wafer such as ion implantation, annealing, and formation of the back electrode is performed, and the wafer is cut into chips by dicing.
[0082]
According to the above-described eighth embodiment, the pattern of the stepped portion 62 is reflected on the back surface of the wafer 61 as much as possible by performing back grinding with the thick protective tape 66 applied after forming the front surface side element structure portion. The back surface can be ground almost flatly without causing to occur. Therefore, it is possible to prevent the wafer from cracking. In addition, since the back surface of the wafer 61 can be prevented from being locally deeply etched, desired device characteristics can be obtained. The same effect can be obtained even when a tape having a good uniformity of in-plane pressure when the tape substrate is softened and thickened is used as the protective tape 66.
[0083]
Embodiment 9 FIG.
FIG. 14 is a process diagram for explaining in detail the back grinding process of the semiconductor device manufacturing method according to the ninth exemplary embodiment of the present invention. First, in the same manner as in the seventh embodiment, a surface-side element structure portion (not shown) is formed on the surface of the semiconductor wafer 61 (FIG. 14A), and a step portion 62 made of polyimide or the like constituting the passivation film and A groove portion between the stepped portion 62 is filled with a filler 63 having peelability by heat foaming to flatten the surface (FIG. 14B). About the filler 63, since it is the same as Embodiment 7, the overlapping description is abbreviate | omitted.
[0084]
Next, a double-sided adhesive heat-resistant UV tape-type adhesive sheet 31 is attached to the surface flattened by filling the filler 63 (FIG. 14C), and a support substrate 32 is attached to the adhesive sheet 31. (FIG. 14 (d)). Since the adhesive sheet 31 and the support substrate 32 are the same as those in the first embodiment, a duplicate description is omitted. Next, a protective tape 64 having a general thickness (for example, about 100 μm) is attached to the surface of the support substrate 32 that is not bonded to the element, and the back grinding apparatus is attached with the protective tape 64 facing downward. (Fig. 14 (e)) and back grinding is performed (Fig. 14 (f)). After the back grinding, the wafer 61 is removed from the suction table 65, and the protective tape 64 is peeled off (FIG. 14 (g)).
[0085]
Next, the wafer 61 is heated to, for example, about 150 ° C. using a hot plate (not shown), for example, and the foam-peelable filler 63 is peeled off (FIG. 14H). Thereafter, if necessary, surface treatment on the back side of the wafer is performed by etching. Then, as in the first to sixth embodiments, processing on the back side of the wafer such as ion implantation, annealing, and formation of a back electrode is performed, and UV light is irradiated to peel off the adhesive sheet 31 and the support substrate 32 (FIG. 14 (h)). Finally, it is cut into chips by dicing (FIG. 14 (i)).
[0086]
According to the above-described ninth embodiment, after the surface-side element structure portion is formed, the surface is flattened by the filler 63 and further back-grinded with the support substrate 32 bonded, whereby the back surface of the wafer 61 is formed. Thus, the back surface can be ground flat without reflecting the pattern of the stepped portion 62. Further, even when the wafer 61 is thinned, the warp of the wafer 61 in the process after back grinding can be suppressed by being bonded to the support substrate 32. Therefore, it is possible to prevent the wafer from cracking. In addition, since the back surface of the wafer 61 can be prevented from being locally scraped, desired device characteristics can be obtained.
[0087]
As the filler 63, an adhesive that can be cured and peeled off by irradiation with UV light may be used. In that case, it is not necessary to heat the wafer 61 with a hot plate or the like, and after the back grinding, the wafer back surface processing is performed until the back surface electrode is formed with the filler 63 being filled. Immediately before dicing, the filler 63 is removed simultaneously with the peeling of the adhesive sheet 31 and the support substrate 32 by irradiation with UV light.
[0088]
【Example】
Example 1.
In accordance with the first embodiment described above, an FS type IGBT was manufactured. N used ^- The diameter of the FZ wafer 21 was 6 inches, and the thickness was 625 μm. A quartz glass wafer was used as the support substrate 32. A UV tape type sheet was used as the adhesive sheet 31. The thickness of the wafer 21 after back grinding was set to 70 μm, 80 μm, 90 μm, or 100 μm in order to investigate the relationship between the amount of warpage of the wafer and the cracking rate with respect to the wafer thickness.
[0089]
N serving as a buffer layer ⁺ In order to form the layer 23, the dose when phosphorus is ion-implanted is 5 × 10 ¹² cm ^-2 And the acceleration voltage was 600 keV. P to be the collector layer ⁺ In order to form the layer 24, the dose when boron is ion-implanted is 1 × 10 ¹⁵ cm ^-2 And the acceleration voltage was 50 keV. In laser annealing, YAG third harmonic (YAG3ω) pulsed laser was irradiated with 50% overlap. The back electrode 25 serving as a collector electrode was made of aluminum, titanium, nickel, and gold, and had a total thickness of 2 μm.
[0090]
Example 2
In accordance with the second embodiment described above, an FS type IGBT was manufactured. The diameter of the epitaxial wafer used was 6 inches. The thickness of the wafer after back grinding is 70 μm (n ⁺ The remaining thickness of the semiconductor substrate 41: 10 μm), 80 μm (n ⁺ The remaining thickness of the semiconductor substrate 41: 20 μm), 90 μm (n ⁺ The remaining thickness of the semiconductor substrate 41: 30 μm) or 100 μm (n ⁺ The remaining thickness of the semiconductor substrate 41 was 40 μm). In laser annealing, XeCl pulsed laser was irradiated with 90% overlap. The support substrate 32, the adhesive sheet 31, the boron ion implantation, and the back electrode 25 were the same as those in Example 1. However, phosphorus ion implantation was not performed on the back surface of the wafer.
[0091]
Example 3
In accordance with the third embodiment described above, an FS type IGBT was manufactured. The same as Example 1 except that the high-rigidity adhesive sheet 51 was affixed without using the support substrate 32 and the adhesive sheet 31.
[0092]
Example 4
In accordance with the fourth embodiment described above, an FS type IGBT was manufactured. It was the same as Example 2 except that the high-rigidity adhesive sheet 51 was attached without using the support substrate 32 and the adhesive sheet 31.
[0093]
Embodiment 5 FIG.
According to the fifth embodiment described above, an FS type IGBT was manufactured. It was the same as Example 1 except that the high-rigidity adhesive sheet 51 and the particle removal adhesive sheet 52 were attached without using the support substrate 32 and the adhesive sheet 31.
[0094]
Example 6
In accordance with the above-described sixth embodiment, an FS type IGBT was manufactured. Example 2 was the same as Example 2 except that the high-rigidity adhesive sheet 51 and the particle removal adhesive sheet 52 were attached without using the support substrate 32 and the adhesive sheet 31.
[0095]
Example 7
In accordance with the seventh embodiment described above, an FS type IGBT was manufactured. The wafer 61 used had a diameter of 6 inches. As the filler 63, an adhesive that can be peeled off by heating and foaming was used. The thickness of the wafer 61 after back grinding was 70 μm, 80 μm, 90 μm, or 100 μm. The back electrode was made of aluminum, titanium, nickel and gold, and had a total thickness of 2 μm.
[0096]
Example 8 FIG.
In accordance with the above-described eighth embodiment, an FS type IGBT was manufactured. The diameter of the wafer 61 used was 6 inches. The protective tape 66 used was a resin tape having a thickness of approximately 150 μm. The thickness of the wafer 61 after back grinding was set to 70 μm, 80 μm, 90 μm, or 100 μm. The back electrode was made of aluminum, titanium, nickel and gold, and had a total thickness of 2 μm.
[0097]
Example 9
In accordance with the ninth embodiment described above, an FS type IGBT was manufactured. As the filler 63, an adhesive that can be peeled off by heating and foaming was used. Others were the same as Example 2.
[0098]
Conventional Example 1
The FS type IGBT was manufactured according to the manufacturing process (see FIG. 31) of the FS type IGBT using the conventional FZ wafer. Example 1 was the same as Example 1 except that the support substrate 32 and the adhesive sheet 31 were not used, and that electric furnace annealing was performed instead of laser annealing (1 hour at 400 ° C.).
[0099]
Conventional Example 2
The FS type IGBT was manufactured according to the manufacturing process of the FS type IGBT using the conventional epitaxial wafer (see FIG. 32). Example 2 was the same as Example 2 except that the support substrate 32 and the adhesive sheet 31 were not used and that electric furnace annealing (400 ° C. for 1 hour) was performed instead of laser annealing.
[0100]
FIG. 15 is a diagram showing the results of examining the relationship between the amount of warpage of the wafer after forming the back electrode (after back surface deposition) and the thickness of the wafer after back grinding for Example 1 and Example 2. Here, the amount of warpage is the difference in height between the center and the periphery of the wafer. From FIG. 15, in both Example 1 and Example 2, even when the thickness of the wafer after back grinding is reduced to 70 μm, the amount of warpage of the wafer after forming the back electrode is such that cracking occurs after the back electrode is formed. It can be seen that it is much smaller than 5.5 mm (in the case of a wafer having a diameter of 6 inches) which is the limit value of the warpage of the wafer.
[0101]
For comparison, FIG. 15 also shows the results of examining the same for Conventional Example 1 and Conventional Example 2. In Conventional Example 1 and Conventional Example 2, when the thickness of the wafer after back grinding is set to 90 μm or less, the warpage amount of the wafer after forming the back electrode is 5.5 mm (a 6-inch diameter wafer). Case). Specifically, when the thickness of the wafer after back grinding is 70 μm, the amount of warpage of the wafer after forming the back electrode is 2 mm in Example 1, 2.1 mm in Example 2, and the conventional example 1 is 11 mm, and the conventional example 2 is 11.2 mm.
[0102]
FIG. 16 is a diagram showing the results of examining the amount of warpage of a wafer for each step in Example 1 and Example 2 where the thickness of the wafer after back grinding is 70 μm. In this specification, it is assumed that a tensile stress acts on the wafer when the surface side of the wafer becomes concave, and a compressive stress acts when the wafer becomes convex. The warpage amount when a tensile stress is acting on the wafer is expressed as a positive value, and the warpage amount when a compressive stress is acting is expressed as a negative value. From FIG. 16, it can be seen that both Example 1 and Example 2 have almost no warpage in each step.
[0103]
For comparison, FIG. 28 shows the result of examining the same in the conventional example 1 and the conventional example 2 in which the wafer thickness after back grinding is 70 μm. In Conventional Example 1 and Conventional Example 2, a positive warp amount occurs before the back electrode is formed, but a warp amount of approximately -11 mm occurs due to the formation of the back electrode.
[0104]
FIG. 17 is a diagram showing the results of examining the relationship between the element cracking rate and the thickness of the wafer after back grinding for Example 1 and Example 2. For comparison, FIG. 17 also shows the results of examining the same for Conventional Example 1 and Conventional Example 2. As shown in FIG. 17, in both Example 1 and Example 2, even when the thickness of the wafer after back grinding is reduced to 70 μm, the cracking ratio is as small as 2% or less. In Example 1 or Example 2, cracking occurs when the UV tape-type adhesive sheet is peeled off and during dicing, and is hardly cracked in the middle of the process. On the other hand, as shown in FIG. 17, in the conventional example 1 and the conventional example 2, although the wafer thickness after the back grinding is 70 μm, the cracking rate is as high as 95%.
[0105]
FIG. 18 is a diagram showing the results of examining the carrier concentration distribution in Example 1 and Conventional Example 1. FIG. 19 is a diagram showing the results of examining the carrier concentration distribution in Example 2 and Conventional Example 2. However, in all cases, measurement was performed by SR (spreading resistance method) from the back side of the wafer except for the back surface electrode. As shown in FIGS. 18 and 19, in Example 1 and Example 2, by using laser annealing, the p layer on the back surface of the wafer can be made higher in concentration than in the conventional example, and a low on-voltage can be achieved. I understand that.
[0106]
FIG. 20 is a diagram showing the results of examining the relationship between the amount of warpage of the wafer after forming the back electrode and the thickness of the wafer after back grinding for Example 3 to Example 6. For comparison, the results of Conventional Example 1 and Conventional Example 2 are also shown in FIG. From FIG. 20, in all of Examples 3 to 6, even when the thickness of the wafer after back grinding is reduced to 70 μm, the amount of warpage of the wafer after forming the back electrode is such that cracking occurs after the back electrode is formed. It can be seen that it is smaller than 5.5 mm (in the case of a wafer having a diameter of 6 inches) which is the limit value of the warpage of the wafer. Specifically, in Examples 3 to 6, the amount of warpage of the wafer after forming the back electrode when the thickness of the wafer after back grinding is 70 μm is about 3 to 3.51 mm.
[0107]
FIG. 21 is a diagram showing the results of examining the amount of warpage of a wafer for each step in Example 3 and Example 4 where the wafer thickness after back grinding is 70 μm. FIG. 22 is a diagram showing the results of examining the amount of warpage of the wafer for each step in Example 5 and Example 6 where the thickness of the wafer after back grinding is 70 μm. From FIG. 21 and FIG. 22, it can be seen that all of Examples 3 to 6 have almost no warpage in each step.
[0108]
FIG. 23 is a diagram showing the results of examining the relationship between the element cracking rate and the thickness of the wafer after back grinding for Examples 3 to 6. For comparison, the results of Conventional Example 1 and Conventional Example 2 are also shown in FIG. As shown in FIG. 23, in all of Examples 3 to 6, even when the thickness of the wafer after back grinding is reduced to 70 μm, the cracking rate is as small as 5% or less. In Examples 3 to 6, cracks occur when the high-rigidity adhesive sheet or the particle removal adhesive sheet is peeled off and during dicing, and are hardly cracked in the middle of the process.
[0109]
FIG. 18 shows the result of examining the carrier concentration distribution for Example 3 and Example 5, and FIG. 19 shows the result of examining the carrier concentration distribution for Example 4 and Example 6, respectively. However, all measured by SR from the wafer back surface side except for the back electrode. As shown in FIGS. 18 and 19, in Examples 3 to 6, the laser annealing can be used to increase the concentration of the p-layer on the back surface of the wafer as compared to the conventional example, thereby reducing the on-voltage. I understand that.
[0110]
FIG. 24 is a diagram showing the results of examining the relationship between the amount of warpage of the wafer after forming the back electrode and the thickness of the wafer after back grinding for Example 7 and Example 8. For comparison, the results of Conventional Example 1 and Conventional Example 2 are also shown in FIG. 24, in both Example 7 and Example 8, even when the thickness of the wafer after back grinding is reduced to 70 μm, the amount of warpage of the wafer after forming the back electrode is such that cracking occurs after the back electrode is formed. It can be seen that it is smaller than 5.5 mm (in the case of a wafer having a diameter of 6 inches) which is the limit value of the warpage of the wafer.
[0111]
Specifically, in Example 7 and Example 8, when the thickness of the wafer after back grinding is 70 μm, the amount of warpage of the wafer after forming the back electrode is 5.4 mm. That is, it can be seen that the amount of warpage can be reduced to about half of the conventional amount by performing back grinding without reflecting the uneven pattern on the wafer surface to the back surface of the wafer as much as possible.
[0112]
FIG. 25 is a diagram showing the results of examining the relationship between the element cracking rate and the thickness of the wafer after back grinding for Example 7 and Example 8. For comparison, the results of Conventional Example 1 and Conventional Example 2 are also shown in FIG. As shown in FIG. 25, the cracking rate when the thickness of the wafer after back grinding is 70 μm is 30% in Example 7 and 35% in Example 8. The reason why the cracking ratio is reduced compared to the conventional example is that the amount of warpage is reduced, and the cracks due to the fact that the uneven pattern on the wafer surface is reflected on the back surface of the wafer are almost lost.
[0113]
FIG. 26 is a diagram showing the results of examining the relationship between the amount of warpage of the wafer after forming the back surface electrode (after back surface deposition) and the thickness of the wafer after back grinding in Example 9. For comparison, the results of Example 2 are also shown in FIG. FIG. 26 shows that in Example 9, the amount of warpage of the wafer after forming the back electrode is smaller than that in Example 2. Specifically, in Example 9, the amount of warpage of the wafer after forming the back electrode when the thickness of the wafer after back grinding is 70 μm is 1.8 mm.
[0114]
FIG. 27 is a diagram showing the results of examining the relationship between the element cracking rate and the thickness of the wafer after back grinding in Example 9. For comparison, the results of Example 2 are also shown in FIG. As shown in FIG. 27, in Example 9, it can be seen that the crack rate is smaller than that in Example 2 when the thickness of the wafer after back grinding is set to 70 μm.
[0115]
In the above, since the surface configuration of the semiconductor element is not limited in the present invention, the surface side element structure portion of the semiconductor element may be a planar type or a trench type. Further, the present invention is not limited to an IGBT in which the thickness of a wafer after back grinding is 70 μm, but is applied to a method for manufacturing a power semiconductor device including a step of back grinding the back surface of the wafer to reduce the wafer thickness to 100 μm or less. it can. Further, as in the ninth embodiment, any one of the first to sixth embodiments may be combined with the seventh or eighth embodiment.
[0116]
【The invention's effect】
According to the present invention, after the surface element structure portion of the semiconductor element is formed on the surface side of the semiconductor wafer, the support substrate or the high-rigidity adhesive sheet is bonded to the surface, and in this state, the back grinding is performed and the wafer is bonded. After thinning, processing on the back side of the wafer can suppress warping of the wafer while processing the back side of the wafer and stress acting on the wafer, so that processing on the back side of the wafer is performed. It is possible to prevent the wafer from cracking. In addition, by adopting laser annealing instead of electric furnace annealing, which is a source of stress generation, stress acting on the wafer can be suppressed, so that the wafer can be prevented from cracking. Further, since the warpage of the wafer is reduced, device characteristics as designed can be obtained.
[0117]
Further, according to the present invention, the back grinding is performed with the high-rigidity adhesive sheet and the particle removal adhesive sheet attached to the back surface of the semiconductor wafer, and after the back surface grinding is finished, the particle removal adhesive sheet is peeled off and then ion implantation is performed. By carrying out the process, particles such as shavings and other dust generated during grinding of the back surface of the wafer can be removed before ion implantation, thereby preventing generation of defective products due to the particles.
[0118]
Further, according to the present invention, after the surface side element structure is formed, the surface is planarized with a filler and then back-grinded, or a thick protective tape is applied on the surface side element structure. By performing back grinding, the back surface can be ground flat without reflecting the pattern of the stepped portion on the wafer surface on the back surface of the wafer. Further, since the outer peripheral portion of the wafer is reinforced by the filler, it is possible to prevent the outer periphery of the wafer from being lifted from the adsorption table of the back grinding apparatus during back grinding. Therefore, it is possible to prevent the wafer from cracking. In addition, since the back surface of the wafer can be prevented from being locally scraped, desired device characteristics can be obtained.
[Brief description of the drawings]
FIG. 1 is a diagram showing a part of a manufacturing process of a semiconductor device manufacturing method according to a first embodiment of the present invention;
FIG. 2 is a diagram showing a continuation of the manufacturing process shown in FIG. 1;
FIG. 3 is a diagram showing a part of the manufacturing process of the semiconductor device manufacturing method according to the second exemplary embodiment of the present invention;
FIG. 4 is a diagram showing a continuation of the manufacturing process shown in FIG. 3;
FIG. 5 is a diagram showing a part of the manufacturing process of the semiconductor device manufacturing method according to the third exemplary embodiment of the present invention;
6 is a diagram showing a continuation of the manufacturing process shown in FIG. 5. FIG.
FIG. 7 is a diagram showing a part of the manufacturing process of the semiconductor element manufacturing method according to the fourth exemplary embodiment of the present invention;
8 is a diagram showing a continuation of the manufacturing process shown in FIG. 7. FIG.
FIG. 9 is a diagram showing a part of the manufacturing process of the semiconductor device manufacturing method according to the fifth exemplary embodiment of the present invention;
FIG. 10 is a diagram showing a part of the manufacturing process of the semiconductor device manufacturing method according to the sixth exemplary embodiment of the present invention;
FIG. 11 is a process diagram for explaining in detail the back grinding process of the semiconductor device manufacturing method according to the seventh exemplary embodiment of the present invention;
FIG. 12 is a process diagram for explaining in detail the back grinding process of the semiconductor device manufacturing method according to the eighth exemplary embodiment of the present invention;
FIG. 13 is a characteristic diagram showing the results of examining the uniformity of the in-wafer thickness by changing the thickness of the protective tape in the eighth embodiment.
FIG. 14 is a process diagram for explaining in detail the back grinding process of the semiconductor device manufacturing method according to the ninth embodiment of the present invention;
FIG. 15 is a diagram showing the results of examining the relationship between the amount of warpage of the wafer after forming the back electrode and the thickness of the wafer after back grinding for Example 1, Example 2, Conventional Example 1 and Conventional Example 2; It is.
16 is a diagram showing the results of examining the amount of warpage of a wafer for each step in Example 1 and Example 2. FIG.
17 is a diagram showing the results of examining the relationship between the cracking rate of the element and the thickness of the wafer after back grinding for Example 1, Example 2, Conventional Example 1 and Conventional Example 2. FIG.
FIG. 18 is a diagram showing the results of examining the carrier concentration distribution in Example 1, Example 3, Example 5 and Conventional Example 1.
FIG. 19 is a diagram showing the results of examining the carrier concentration distribution for Example 2, Example 4, Example 6, and Conventional Example 2;
FIG. 20 is a diagram showing the results of examining the relationship between the amount of warpage of the wafer after forming the back electrode and the thickness of the wafer after back grinding for Example 3, Example 4, Example 5 and Example 6; It is.
FIG. 21 is a diagram showing the results of examining the amount of wafer warpage for each step in Example 3 and Example 4;
22 is a diagram showing the results of examining the amount of warpage of a wafer for each step in Example 5 and Example 6. FIG.
FIG. 23 is a diagram showing the results of examining the relationship between the element cracking rate and the thickness of the wafer after back grinding for Example 3, Example 4, Example 5 and Example 6.
FIG. 24 is a diagram showing the results of examining the relationship between the amount of warpage of the wafer after forming the back electrode and the thickness of the wafer after back grinding for Example 7 and Example 8.
FIG. 25 is a diagram showing the results of examining the relationship between the cracking rate of the element and the thickness of the wafer after back grinding for Example 7 and Example 8.
FIG. 26 is a diagram showing the results of examining the relationship between the amount of warpage of the wafer after forming the back electrode and the thickness of the wafer after back grinding for Example 9 and Example 2.
27 is a diagram showing the results of examining the relationship between the element cracking rate and the thickness of the wafer after back grinding for Example 9 and Example 2. FIG.
FIG. 28 is a diagram showing the results of examining the amount of warpage of a wafer for each process in Conventional Example 1 and Conventional Example 2.
FIG. 29 is a cross-sectional view showing a configuration of an NPT type IGBT.
30 is a cross-sectional view showing a configuration of an FS type IGBT. FIG.
FIG. 31 is a diagram showing a manufacturing process of an FS type IGBT using a conventional FZ wafer.
FIG. 32 is a diagram showing a manufacturing process of an FS type IGBT using a conventional epitaxial wafer.
FIG. 33 is a process diagram for explaining in detail a conventional back grinding process.
[Explanation of symbols]
21, 61 Semiconductor wafer
22 Surface element structure
27 chips
31 Double-sided adhesive type adhesive sheet
32 Support substrate
41 n ⁺ Semiconductor substrate
42 Epitaxial layer
51 High rigidity adhesive sheet
52 Particle Removal Adhesive Sheet
63 Filler
66 protective tape

Claims (10)

Producing a surface element structure portion of the semiconductor element on the surface of the semiconductor wafer;
Attaching a high- rigidity adhesive sheet to a surface of the semiconductor wafer on which the surface-side element structure is formed;
A step of further bonding an adhesive sheet for particle removal to the high-rigidity adhesive sheet;
Grinding the back surface of the semiconductor wafer with the high-rigidity adhesive sheet and the particle removing adhesive sheet pasted so that the surface on the back surface side of the semiconductor wafer is flat;
Peeling the adhesive sheet for particle removal;
After peeling off the particle removing adhesive sheet, ion implantation is performed, and the implanted impurities are activated by a laser annealing method to form a back surface structure so that no stress is generated on the ground surface of the semiconductor wafer. A manufacturing process;
Peeling the high-rigidity adhesive sheet from the semiconductor wafer on which the back surface structure is produced;
After peeling off the highly rigid adhesive sheet, cutting the semiconductor wafer into chips,
The manufacturing method of the semiconductor element characterized by the above-mentioned. 2. The method of manufacturing a semiconductor element according to claim 1 , wherein an elastic modulus of a base material of the high-rigidity adhesive sheet is 2 to 5 Gpa, and a thickness of the base material is 50 μm or more . The pressure-sensitive adhesive for attaching the high-rigidity adhesive sheet to the semiconductor wafer is a UV-curable pressure-sensitive adhesive that can be cured and peeled off by irradiation with UV light. the method according to claim 1 or 2, characterized in that for stripping the. The pressure-sensitive adhesive for adhering the high-rigidity adhesive sheet to the semiconductor wafer is a heat-foamable pressure-sensitive adhesive that can be peeled off by heat foaming, and the high-rigidity adhesive sheet is heated and peeled off. the method according to claim 1 or 2. The pressure-sensitive adhesive for attaching the high-rigidity adhesive sheet to the semiconductor wafer is a visible-light curable pressure-sensitive adhesive that can be cured and peeled off by irradiation with visible light. When the high-rigidity adhesive sheet is peeled off, Irradiating visible light, The manufacturing method of the semiconductor element of Claim 1 or 2 characterized by the above-mentioned. 6. The method of manufacturing a semiconductor element according to claim 1, wherein the particle removing adhesive sheet is mechanically peeled off . The pressure-sensitive adhesive for sticking the particle-removing adhesive sheet is a UV-curable pressure-sensitive adhesive that can be cured and peeled off by UV light irradiation, and the UV light is irradiated to peel off the particle-removing adhesive sheet. The method for manufacturing a semiconductor device according to claim 1, wherein: The pressure-sensitive adhesive for attaching the particle-removing adhesive sheet is a heat-foaming pressure-sensitive adhesive that can be peeled off by heat foaming, and heats and peels off the particle-removing adhesive sheet. The manufacturing method of the semiconductor element as described in any one of 1-5 . The pressure-sensitive adhesive for sticking the particle-removing adhesive sheet is a visible-light curable pressure-sensitive adhesive that can be cured and peeled off by irradiation with visible light. The particle-removing adhesive sheet is irradiated with visible light. It peels , The manufacturing method of the semiconductor element as described in any one of Claims 1-5 characterized by the above-mentioned. 10. The semiconductor wafer according to claim 1, wherein the semiconductor wafer is an epitaxial wafer, and ion implantation is performed when the back surface structure is fabricated, and the implanted impurities are activated by a laser annealing method. The manufacturing method of the semiconductor element of description.

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