JP4364799B2 - ナノ結晶を形成する方法 - Google Patents
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- H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
- H10P14/3202—Materials thereof
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- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
- H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
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- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
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Description
本発明を、限定ではなく例示として添付図面に示す。図中、同様な参照符号は同様の要素を示す。
(図面の詳細な説明)
1実施形態においてデータ記憶装置として使用されるトランジスタの誘電体層上にナノ結晶を始めとするナノクラスターを形成するために、二相プロセスが使用される。第1相つまり核化相は第1の前駆物質を使用するが、この第1の前駆物質は、第2相つまり成長相で使用される第2の前駆物質よりも、下にある誘電体層(例えばトンネル誘電体)に対して高い付着係数を有する。さらに、第2の前駆物質は、下にある誘電体層に対してよりも、ナノ結晶を形成するために使用される材料に対してより大きな付着係数を有する。好ましい実施形態では、第1の前駆物質はジシラン(ガス)である。また、第2の前駆物質はシラン(ガス)である。さらに、好ましい実施形態では、第1相と第2相とで同じ処理条件(温度、圧力および同時フローガス)が使用される。二相プロセスの間に形成されるナノ結晶は、1実施形態では、図1に示される記憶装置の一部である。
ことができるため、記憶装置10のそれらの部分の構成は簡潔に説明する。半導体基板はケイ素、ケイ素ゲルマニウム、ガリウム砒素、ケイ素・オン・インシュレータ(SOI)、およびそれらの同等物、あるいはそれらの組み合わせであり得る。二酸化ケイ素を始めとする誘電体層が、熱成長、化学気相成長(CVD)、およびそれらの同等物、あるいはそれらの組み合わせにより半導体基板上に形成され、トンネル誘電体18として使用される。図2に関連してより詳細に説明するように、誘電体層上にナノ結晶が形成され、1実施形態ではナノ結晶は記憶装置10のフローティングゲートである。任意選択で、窒素を含有する不活性化層(図示しない)をナノ結晶20の上に形成してもよい。ナノ結晶20の上に、二酸化ケイ素、酸化ハフニウム、酸化アルミニウムおよびそれらの同等物、およびそれらの組み合わせなどのコントロール誘電体22が堆積される。コントロール誘電体22を形成した後に、ポリシリコンを始めとする導電材料がコントロール電極24を形成するため堆積される。ソース延長部13、深いソース領域14、ドレイン延長部15およびドレイン領域16が形成される場所の半導体基板12の領域の材料部分を除去するために、コントロール電極24、コントロール誘電体22、ナノ結晶20およびトンネル誘電体18がエッチングされる。
着係数の相対値は、核形成前のタイムラグして定義されるような、観察したインキュベーション時間より得ることができる。
化および成長の両方が十分にコントロールされる。
Claims (5)
- ナノ結晶を形成する方法(30)であって、
基板(12)を提供すること(32);
基板の上に誘電体(18)を形成すること;
化学気相成長室に基板を配置すること(34);
誘電体の表面に対する第1の付着係数を有する第1の前駆物質ガスを第1相の間化学気相成長室内に流し(36)、化学気相成長室内に存在する第1の所定条件で第1の期間誘電体上にナノ結晶(20)を核化すること;
化学気相成長室への第1の前駆物質ガスの流入を終了すること;および
第1の前駆物質ガスとは異なる第2の前駆物質ガスを第2相の間化学気相成長室内に流し(38)、化学気相成長室内に存在する第2の所定条件で第2の期間ナノ結晶を成長させることであって、第2の前駆物質ガスは誘電体の表面に対して第1の付着係数よりも小さい第2の付着係数を有すると共に、ナノ結晶の表面に対して第2の付着係数よりも大きい第3の付着係数を有すること;から成る方法(30)。 - 第1の前駆物質ガスとは異なる第2の前駆物質ガスを流入させた後に続き、不活性雰囲気でナノ結晶をアニールすること(40)をさらに含む請求項1に記載の方法。
- ナノ結晶(20)を形成する方法(30)であって、
半導体基板(12)を提供すること(32);
半導体基板の上に誘電体層(18)を形成すること;
誘電体層上で材料の急速加熱化学気相成長を実行するために化学気相成長室に半導体基板を配置すること(34);
ジシランガスを第1相の間化学気相成長室内に第1の期間流し(36)、化学気相成長室内に存在する400〜530℃の基板温度範囲と10〜100ミリトル(約1330〜13300Pa)のジシラン分圧で第1の所定条件で誘電体上に複数のナノ結晶を形成すること;および
第1相の後に続く第2相の間シランガスを前記第1の期間よりも長い第2の期間流し(38)、第1の期間と少なくとも同じ程度の温度と分圧を有する化学気相成長室内に存在する処理条件でナノ結晶を成長させること;から成る方法(30)。 - ナノ結晶(20)を形成する方法(30)であって、
基板(12)を提供すること(32);
基板の上に誘電体(18)を形成すること;
化学気相成長室に基板を配置すること(34);
誘電体の表面に対する第1の付着係数を有する第1の前駆物質ガスを第1相の間化学気相成長室内に流し(36)、化学気相成長室内に存在する第1の所定条件で第1の期間誘電体上にナノ結晶を核化すること;
第2の前駆物質ガスを第2相の間化学気相成長室内に流し(38)、化学気相成長室内に存在する第2の所定条件で第2の期間ナノ結晶を成長させることであって、第2の前駆物質ガスは誘電体の表面に対して第1の付着係数よりも小さい第2の付着係数を有すると共に、ナノ結晶の表面に対して第2の付着係数よりも大きい第3の付着係数を有すること;から成る方法(30)。 - 第1の前駆物質ガスはジシランガスであり、第2の前駆物質ガスはシランガスである請求項1または4に記載の方法。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/231,556 US6808986B2 (en) | 2002-08-30 | 2002-08-30 | Method of forming nanocrystals in a memory device |
| PCT/US2003/016289 WO2004021423A1 (en) | 2002-08-30 | 2003-05-22 | Method of forming nanocrystals |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2005537660A JP2005537660A (ja) | 2005-12-08 |
| JP2005537660A5 JP2005537660A5 (ja) | 2006-06-22 |
| JP4364799B2 true JP4364799B2 (ja) | 2009-11-18 |
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| Application Number | Title | Priority Date | Filing Date |
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| JP2004532572A Expired - Lifetime JP4364799B2 (ja) | 2002-08-30 | 2003-05-22 | ナノ結晶を形成する方法 |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US6808986B2 (ja) |
| EP (1) | EP1490896A1 (ja) |
| JP (1) | JP4364799B2 (ja) |
| KR (1) | KR20050031455A (ja) |
| CN (1) | CN100336175C (ja) |
| AU (1) | AU2003248563A1 (ja) |
| TW (1) | TWI231529B (ja) |
| WO (1) | WO2004021423A1 (ja) |
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| JP3727449B2 (ja) * | 1997-09-30 | 2005-12-14 | シャープ株式会社 | 半導体ナノ結晶の製造方法 |
| US6320784B1 (en) * | 2000-03-14 | 2001-11-20 | Motorola, Inc. | Memory cell and method for programming thereof |
| US6344403B1 (en) * | 2000-06-16 | 2002-02-05 | Motorola, Inc. | Memory device and method for manufacture |
| US6297095B1 (en) * | 2000-06-16 | 2001-10-02 | Motorola, Inc. | Memory device that includes passivated nanoclusters and method for manufacture |
| US6455372B1 (en) * | 2000-08-14 | 2002-09-24 | Micron Technology, Inc. | Nucleation for improved flash erase characteristics |
| CN1305232A (zh) * | 2001-02-27 | 2001-07-25 | 南京大学 | 锗/硅复合纳米晶粒浮栅结构mosfet存储器 |
-
2002
- 2002-08-30 US US10/231,556 patent/US6808986B2/en not_active Expired - Lifetime
-
2003
- 2003-05-22 CN CNB038016060A patent/CN100336175C/zh not_active Expired - Lifetime
- 2003-05-22 AU AU2003248563A patent/AU2003248563A1/en not_active Abandoned
- 2003-05-22 JP JP2004532572A patent/JP4364799B2/ja not_active Expired - Lifetime
- 2003-05-22 WO PCT/US2003/016289 patent/WO2004021423A1/en not_active Ceased
- 2003-05-22 EP EP03791554A patent/EP1490896A1/en not_active Withdrawn
- 2003-05-22 KR KR1020047009969A patent/KR20050031455A/ko not_active Ceased
- 2003-06-10 TW TW092115688A patent/TWI231529B/zh not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| US20040043583A1 (en) | 2004-03-04 |
| US6808986B2 (en) | 2004-10-26 |
| WO2004021423A1 (en) | 2004-03-11 |
| TWI231529B (en) | 2005-04-21 |
| CN100336175C (zh) | 2007-09-05 |
| KR20050031455A (ko) | 2005-04-06 |
| CN1596459A (zh) | 2005-03-16 |
| EP1490896A1 (en) | 2004-12-29 |
| JP2005537660A (ja) | 2005-12-08 |
| TW200409207A (en) | 2004-06-01 |
| AU2003248563A1 (en) | 2004-03-19 |
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