JP4366643B2 - Encoding apparatus and method, decoding apparatus and method, recording medium, and program - Google Patents

Description

  The present invention relates to an encoding device and method, a decoding device and method, a recording medium, and a program, and in particular, an encoding device and method, and a decoding device that can realize high compression and high error resistance encoding. And a method, a recording medium, and a program.

  A technique of compressing and communicating by encoding image data and audio data has been put into practical use.

As a technology that enables encoding with an increased compression rate, there is a technology that increases the compression rate by converting encoded data encoded in ADRC (Adaptive Dynamic Range Coding) code into vector quantization (VQ) code. (For example, refer to Patent Document 1).
Japanese Patent No. 2518214

  However, in general, the higher the compression rate is, the more the data deteriorates during decoding with respect to errors that occur during transmission. For example, when the compression rate is 10 times, the transmission bit weight is 10 bits at the time of non-compression.

  As a result, the encoding method with a high compression rate has a problem that if an error occurs in the code encoded on the transmission path, a large deterioration occurs during decoding.

  The present invention has been made in view of such a situation, and in particular, realizes encoding with a high compression ratio and high error resistance.

The encoding device of the present invention is input data that is image data, calculates a dynamic range and a minimum value from a plurality of input data, and outputs as a calculation result, and based on the calculation result of the calculation means, A code conversion means for converting input data into a code; a scramble means for scrambling the operation result with the code by obtaining an exclusive OR of the operation result and the code ; an operation result scrambled by the scramble means; Encoding means for encoding input data using a code.

The encoding method of the present invention is input data that is image data, calculates a dynamic range and a minimum value from a plurality of input data, outputs the result as a calculation result, and calculates the calculation result in the processing of the calculation step. Based on the code conversion step for converting the input data into the code, the scramble step for scrambling the calculation result with the code by obtaining the exclusive OR of the calculation result and the code, and the scramble processing by the processing of the scramble step And an encoding step for encoding the input data using the calculation result and the code.

The program of the first recording medium of the present invention is input data that is image data, and calculates a dynamic range and a minimum value from a plurality of input data, and outputs the result as a calculation result. A code conversion step for converting input data into a code based on the result of the operation, a scramble step for scrambling the operation result with the code by obtaining an exclusive OR of the operation result and the code, and a process of the scramble step And a coding step of coding input data using the calculation result obtained by the scramble processing and the code.

A first program of the present invention is input data that is image data, calculates a dynamic range and a minimum value from a plurality of input data, and outputs the result as a calculation result, and a calculation result in the processing of the calculation step Code conversion step for converting input data to code, scrambling step for scrambling operation result by code by obtaining exclusive OR of operation result and code, and scrambling processing by scrambling step processing The computer is caused to execute an encoding step of encoding input data using the calculated operation result and a code.

The decoding device of the present invention is input data that is image data, and a code obtained by converting input data based on a calculation result obtained by calculating a dynamic range and a minimum value from a plurality of input data, A decoding device that decodes encoded input data including an operation result scrambled by a code by obtaining an exclusive OR of the operation result and the code, and is included in the encoded input data Descramble means for descrambling the scrambled computation result by the code, error detection means for detecting an error in the code included in the encoded input data, and the computation result descrambled by the descrambling means Error detection means stored in the storage means and the error detection means stored in the storage means. Descramble processing by the descrambling means based on the error detection result of the estimation means and the error detection means of the error detection means based on the calculation result obtained from the scrambled calculation result based on the calculation result used in the processing in the case of being not performed The encoded input data is decoded from the calculated operation result and the code included in the encoded input data, or the operation result descrambled by the descrambling means and the code estimated by the estimation means. And a decoding means.

The decoding method of the present invention is input data that is image data, and a code obtained by converting input data based on a calculation result obtained by calculating a dynamic range and a minimum value from a plurality of input data, A decoding method of a decoding apparatus for decoding encoded input data including an operation result scrambled by a code by obtaining an exclusive OR of the operation result and a code, the encoded input data A descrambling step that descrambles the scrambled operation result with a code included in the code, an error detection step that detects an error in the code included in the encoded input data, and a descrambling process in the descrambling step A storage step for storing the processed calculation results, and storage by the processing of the storage step The estimation step for estimating the code from the scrambled computation result based on the computation result used in the processing when no error is detected in the error detection step processing, and the error detection step processing Based on the error detection result in, the calculation result descrambled by the descrambling process and the code included in the encoded input data, or the descrambling process by the descrambling process And a decoding step of decoding the encoded input data from the result and the code estimated in the estimation step.

The program of the second recording medium of the present invention is input data that is image data, and the input data is converted on the basis of a calculation result obtained by calculating a dynamic range and a minimum value from a plurality of input data. A program that controls a decoding device that decodes encoded input data that includes an operation result that is scrambled by the code by obtaining an exclusive OR of the generated code and the operation result and the code, A descrambling step for descrambling the operation result scrambled by a code included in the encoded input data, an error detection step for detecting an error in the code included in the encoded input data, and descrambling A storage control block that controls the storage of the calculation results descrambled in the step processing. Based on the calculation result used in the process when the error is not detected in the error detection step process, the storage is controlled by the process in the storage control step, Based on the estimation step for estimating the code and the error detection result in the error detection step, the calculation result descrambled in the descrambling step and the code included in the encoded input data, or And an operation result descrambled by the descrambling step, and a decoding step of decoding the encoded input data from the code estimated by the estimation step.

A second program of the present invention is input data which is image data, and is a code obtained by converting input data based on a calculation result obtained by calculating a dynamic range and a minimum value from a plurality of input data. And a computer that controls the decoding device that decodes the encoded input data including the operation result scrambled by the code by obtaining an exclusive OR of the operation result and the code. The descrambling step for descrambling the scrambled calculation result by the code included in the data, the error detection step for detecting the error of the code included in the encoded input data, and the descrambling step process A storage control step for controlling the storage of the scrambled computation results; Estimate that estimates the code from the scrambled calculation result based on the calculation result used in the process when the error is not detected in the error detection step process and the memory is controlled by the control process. Based on the error detection result in the step and the error detection step processing, the calculation result descrambled in the descrambling step processing and the code included in the encoded input data, or the descrambling step The present invention is characterized in that a calculation step that has been descrambled in the process and a decoding step for decoding the encoded input data from the code estimated in the estimation step are executed.

In the encoding apparatus and method of the present invention and the first program, input data that is image data, a dynamic range and a minimum value are calculated from a plurality of input data, and output as calculation results. On the basis of the input data is converted into a code, and by calculating the exclusive OR of the operation result and the code, the operation result is scrambled with the code , the operation result subjected to the scramble processing and the code are used, Input data is encoded.

In the decoding apparatus and method of the present invention, and the second program, input data that is image data, based on a calculation result obtained by calculating a dynamic range and a minimum value from a plurality of input data, By obtaining an exclusive OR of the code obtained by converting the input data and the operation result and the code, the code is scrambled by the code included in the encoded input data including the operation result scrambled by the code. The result of the calculation is descrambled, an error in the code included in the encoded input data is detected, the result of the operation descrambled is stored and stored, and the process when no error is detected The code is estimated from the scrambled computation results based on the computation results used in Based on the error detection result, the descrambled computation result and the code included in the encoded input data, or the descrambled computation result and the input encoded from the estimated code Data is decrypted.

  The encoding device and the decoding device of the present invention may be independent devices, or may be blocks that perform encoding and decoding.

  According to the present invention, it is possible to perform encoding with a high compression rate and high error tolerance.

  Embodiments of the present invention will be described below. The correspondence relationship between the invention described in this specification and the embodiments of the invention is exemplified as follows. This description is intended to confirm that the embodiments supporting the invention described in this specification are described in this specification. Therefore, although there is an embodiment which is described in the embodiment of the invention but is not described here as corresponding to the invention, it means that the embodiment is not It does not mean that it does not correspond to the invention. Conversely, even if an embodiment is described herein as corresponding to an invention, that means that the embodiment does not correspond to an invention other than the invention. Absent.

  Further, this description does not mean all the inventions described in this specification. In other words, this description is for the invention described in the present specification, which is not claimed in this application, that is, for the invention that will be applied for in the future or that will appear and be added by amendment. It does not deny existence.

That is, the encoding apparatus of the present invention is input data that is image data, and calculates a dynamic range and a minimum value from a plurality of input data, and outputs the result as a calculation result (for example, the VQ encoder 51 in FIG. 8). ) And code conversion means (for example, the VQ encoder 51 in FIG. 8) for converting input data into a code based on the calculation result of the calculation means, and calculating the exclusive OR of the calculation result and the code. A scramble unit (for example, scrambler 53 in FIG. 8) that scrambles the result with a code, an operation result that is scrambled by the scramble unit, and a code, and an encoding unit that encodes input data (for example, And a synthesizing unit 54) of FIG.

The encoding method of the present invention is input data that is image data, and calculates a dynamic range and a minimum value from a plurality of input data, and outputs the result as a calculation result (for example, step S42 in the flowchart of FIG. 9). Process), a code conversion step (for example, the process of step S42 in the flowchart of FIG. 9) for converting the input data into a code based on the calculation result of the calculation step, and the exclusive logic of the calculation result and the code By using the scramble step (for example, the process of step S45 in the flowchart of FIG. 9) , the operation result scrambled by the process of the scramble step, and the code by scrambling the operation result with the code by obtaining the sum , An encoding step for encoding input data (for example, the flowchart of FIG. 9). Characterized in that it comprises a process of step S46).

The decoding device of the present invention is input data that is image data, and a code obtained by converting input data based on a calculation result obtained by calculating a dynamic range and a minimum value from a plurality of input data, A decoding device that decodes encoded input data including an operation result scrambled by a code by obtaining an exclusive OR of the operation result and the code, and is included in the encoded input data The descrambling means (for example, the descrambler 72 in FIG. 12) for descrambling the scrambled calculation result by the code, and the error detecting means (for example, detecting an error of the code included in the encoded input data) The error detection unit 77) in FIG. 12 and the calculation result descrambled by the descrambling means are recorded. And a scrambled computation based on the computation results stored in the storage means (for example, the memory 73 in FIG. 12) and the computation results used in the process when no error is detected by the error detection means. Based on the result, the estimation means (for example, the error processing unit 74 in FIG. 12) for estimating the code, the calculation result descrambled by the descrambling means based on the error detection result of the error detection means, and the encoded result Decoding means (for example, VQ in FIG. 12) that decodes the encoded input data from the code included in the input data or the calculation result descrambled by the descrambling means and the code estimated by the estimation means And a decoder 76).

The decoding method of the present invention is input data that is image data, and a code obtained by converting input data based on a calculation result obtained by calculating a dynamic range and a minimum value from a plurality of input data, A decoding method of a decoding apparatus for decoding encoded input data including an operation result scrambled by a code by obtaining an exclusive OR of the operation result and a code, the encoded input data A descrambling step (for example, the process of step S62 in the flowchart of FIG. 13) for descrambling the scrambled calculation result by the code included in the code and an error in the code included in the encoded input data are detected. Error detection step (for example, the process of step S64 in the flowchart of FIG. 13), A storage step (for example, the process of step S66 in the flowchart of FIG. 13) that stores the calculation result descrambled by the process of the rumble step and an error detection process that is stored by the process of the storage step cause an error. An estimation step (for example, the processing in step S63 in the flowchart of FIG. 13) for estimating a code based on the calculation result obtained by the scramble processing based on the calculation result used in the processing when it is not detected, and an error detection step Based on the error detection result in the processing, the descrambling process is performed by the descrambling processing result and the code included in the encoded input data or by the descrambling step processing. The calculation result and the estimated value in the estimation step Doyori, decoding step of decoding the input data encoded (e.g., the processing in step S68 in the flowchart of FIG. 13), characterized in that it comprises a.

  FIG. 1 is a diagram showing a configuration of an embodiment of a communication system to which the present invention is applied.

  The encoding device 1 performs ADRC (Adaptive Dynamic Range Coding) encoding or VQ (Vector Quantization) encoding for each pixel block of the image and outputs the image data as input data.

  When the decoding device 2 acquires the image data encoded by the encoding device 1, the decoding device 2 performs ADRC decoding or VQ decoding in accordance with the encoding method for each block of the pixels in the image. Image data which is input data is reproduced from the digitized data and displayed on a display (not shown).

  Next, the configuration of the encoding device 1 will be described.

  The block forming unit 11 sequentially extracts a block of pixels for VQ encoding from the input image (for example, in raster scan order), supplies the block to the VQ encoding unit 12, and also provides a block of pixels for ADRC encoding. Extracted sequentially (for example, in raster scan order) and supplied to the ADRC encoding unit 13. For example, a pixel block for VQ encoding (hereinafter also referred to as a VQ encoding block) is a pixel block of 4 pixels × 4 pixels, and a pixel block for ADRC encoding (hereinafter referred to as ADRC encoding block). (Also referred to as a block) is 8 pixels × 8 pixels. Note that the pixel block size corresponding to each encoding method is not limited to this.

  The VQ encoding unit 12 refers to the code book 15 based on the pixel value of each pixel of the VQ encoding block supplied from the blocking unit 11, performs VQ encoding for each block, and selects the encoded data To the unit 14. Details of the VQ encoding process will be described later.

  The ADRC encoding unit 13 performs ADRC encoding for each block using the pixel value of each pixel block of the ADRC encoding pixel supplied from the blocking unit 11, and supplies the encoded data to the selection unit 14. To do.

  The selector 14 compares the VQ-encoded encoded data supplied from the VQ encoder 12 and the dynamic range (hereinafter also referred to as DR) of the ADRC-encoded encoded data with a predetermined threshold, Depending on the comparison result, ADRC encoded data or VQ encoded data is output.

  As a result, in the encoding method selected by the selection unit 14, encoded data having a different encoding method for each block is generated. For example, an image of one frame is generated for each block as shown in FIG. Images are encoded in different formats. That is, in FIG. 2, hatched cells are 4 × 4 pixel VQ encoding blocks, and white cells are 8 × 8 pixel ADRC encoding blocks. is there. More specifically, when ADRC encoded data is selected, ADRC encoded data for a block of 8 pixels × 8 pixels is used, but when VQ encoded data is selected, it is reduced to 8 pixels × 8 pixels. The VQ encoded data of the corresponding four VQ encoding blocks are used (the VQ encoding block is a block of 4 pixels × 4 pixels, so that 4 blocks are used to encode an equivalent area. Minutes).

  In FIG. 2, according to the selection result of the selection unit 14, pixels belonging to 10 ADRC encoding blocks are ADRC encoded in one image, and further, pixels belonging to 56 VQ encoding blocks are detected. It is shown that it is VQ encoded.

  Next, the configuration of the decoding device 2 will be described.

  When the determination unit 21 acquires the encoded data supplied from the encoding device 1, it determines whether the encoded data is VQ encoded data or ADRC encoded data. When it is determined that the data is VQ encoded data, the acquired encoded data is supplied to the VQ decoding unit 22. When it is determined that the acquired encoded data is ADRC encoded data, the determination unit 21 supplies the acquired encoded data to the ADRC decoding unit 23.

  The VQ decoding unit 22 VQ-decodes the encoded data supplied from the determination unit 21 based on the code book 25 and supplies it to the synthesis unit 24. The code book 25 is the same as the code book 15. The ADRC decoding unit 23 performs ADRC decoding on the encoded data supplied from the determination unit 21 and supplies the encoded data to the synthesis unit 24. The synthesizing unit 24 stores the VQ-decoded input image data supplied from the VQ decoding unit 22 in association with the VQ encoded block, and the ADRC-decoded input image data supplied from the ADRC decoding unit 23. Is stored for each block, and when all the data constituting one image is finally obtained, the decoded input image data is synthesized to generate and output the input image, not shown. Display on the display.

  Next, the encoding process by the encoding device 1 will be described with reference to the flowchart of FIG.

  In step S <b> 1, the blocking unit 11 extracts and supplies the VQ encoding unit 12 from the pixels of the input image in units of VQ encoding blocks, and supplies the ADRC encoding unit 13 with the ADRC code. Extracted from the pixels of the input image and supplied in units of conversion blocks.

  In step S <b> 2, the ADRC encoding unit 13 performs ADRC encoding of each pixel using the pixel value of each pixel of the ADRC encoding block supplied from the blocking unit 11 and supplies the pixel to the selection unit 14.

  That is, ADRC encoding is variable length encoding that outputs a variable length code adapted to the dynamic range (DR) of input image data. Therefore, first, the ADRC encoding unit 13 detects a dynamic range that is a difference between the maximum value and the minimum value of the pixel values included in the supplied ADRC encoding block.

  That is, for example, when an ADRC encoding block is shown in FIG. 4, it is calculated as follows. In FIG. 4, for convenience of explanation, the ADRC encoding block is a 2 pixel × 2 pixel block including pixels P1 to P4, and the pixel values of the pixels are indicated by P1 to P4. And For example, when the pixel value of each pixel in FIG. 4 is as shown in FIG. 5, DR (= MAX−MIN) is the difference between the pixel value P4 of the pixel P4 that is the maximum value and the pixel P3 that is the minimum value ( P4-P3). In FIG. 5, MAX represents the maximum pixel value of the pixels P1 to P4, and MIN represents the minimum value.

  Further, the ADRC encoding unit 13 re-quantizes each pixel value with a smaller number of bits than the original quantization bit based on the obtained DR. That is, in the case as shown in FIG. 5, when the DR is the smallest, when requantization is performed with 1 bit, the code of each pixel is determined by comparison with the threshold th1 (= MIN + DR / 2). That is, if the code is “1” when the value is larger than the threshold th1, and the code is “0” when the code is smaller than the threshold th1, the code of the pixel value of the pixel P1 is “0” and the code of the pixel value of the pixel P2 Is “1”, the pixel value code of the pixel P3 is “0”, and the pixel value code of the pixel P1 is “1”.

  Then, the ADRC encoding unit 13 sequentially arranges the codes of these pixels and generates an ADRC code for each block. In the case of FIG. 5, assuming that the ADRC encoding unit 13 generates a 1-bit ADRC code by arranging the codes in the order of the pixels P1 to P4, for example, the ADRC code of the block of FIG. "

The number of bits is set in proportion to DR. For example, when DR is large and the quantization bit is 2, in the case of FIG. 5, the threshold th0 (= MIN + 1 × DR / 4 = MIN + 1 × DR / ( 2 ² )) When (DR / (2 ⁿ ) is smaller than the quantization width and n is the number of quantization bits), the code is “00”, and the threshold th1 is equal to or greater than the threshold th0 (= MIN + 2 × DR / 4). ), The code is “01”, the code is “10” when the threshold is greater than or equal to the threshold th1 and less than the threshold th2 (= MIN + 3 × DR / 4), and the code is “11” when the threshold is greater than or equal to the threshold th2. Then, the code of the pixel P1 is “00”, the code of the pixel P2 is “10”, the code of the pixel P3 is “00”, and the code of the pixel P4 is “11”.

  Therefore, in such a case, the ADRC encoding unit 13 generates “00100011” as the encoded code of the block of FIG.

  Furthermore, as the DR increases, the number of bits used for requantization increases and is allocated to a maximum of 4 bits, for example.

  In this way, the ADRC encoding can be re-quantized with a smaller number of bits as the dynamic range is smaller, and only the redundancy of the pixel value of the pixel is removed while suppressing an increase in quantization distortion. It is possible to reduce the amount of data.

  The ADRC encoding unit adds DR and MIN information to the generated ADRC code and supplies the ADRC encoded data to the selection unit 14 as ADRC encoded data.

  In step S <b> 3, the VQ encoding unit 12 performs VQ encoding of each pixel using the pixel value of each pixel of the VQ encoding block supplied from the blocking unit 11 and supplies the pixel to the selection unit 14.

  That is, the VQ encoding unit 12 collectively quantizes a plurality of pixels of the VQ encoding block as a vector.

  That is, for example, when the VQ encoding block is as shown in FIG. 4, the VQ encoding unit 12 samples a value obtained by converting the code converted into the ADRC code into a decimal number, and uses this as a plurality of consecutive samples. A vector Vb having values as elements is generated. That is, in the case of FIG. 4, as described above, when the pixels P1 to P4 are ADRC-encoded with 2 bits, they become “00”, “10”, “00”, and “11”, respectively. Therefore, when these are converted to decimal, the code C (P1) corresponding to the pixel P1 is “0”, the code C (P2) corresponding to the pixel P2 is “1”, and the code C (P3) corresponding to the pixel P3. Is “2”, and the code C (P4) corresponding to the pixel P4 is “3”. Therefore, the VQ encoding unit 12 uses the sample value vector Vb = (C (P1), C (P2), C (P3), C (P4)) for the VQ encoding block of FIG. Vb = (C (P1), C (P2), C (P3), C (P4)) = (0, 1, 0, 3).

  Next, the VQ encoding unit 12 refers to the code book 15, and determines the VQ code corresponding to the registered representative vector and the representative vector closest to the vector Vb obtained by the calculation as the VQ code of the block. Determine as.

  Here, the code book 15 is, for example, as shown in FIG. In FIG. 6, the VQ code is shown on the left side, and in this case, “00”, “01”, “10”, and “11” are shown from the top. Also, on the right side, each element of the representative vector corresponding to each VQ code is shown. In this case, the representative vectors are (C (P1), C (P2), C (P3), C from the top. (P4)) = (5, 7, 2, 10), (6, 7, 10, 11), (2, 9, 10, 12), (0, 1, 0, 3). That is, in FIG. 6, the representative vector corresponding to the VQ code “00” is (5, 7, 2, 10), and the representative vector corresponding to the VQ code “01” is (6, 7, 10, 11), the representative vector corresponding to the VQ code “10” is (2, 9, 10, 12), and the representative vector corresponding to the VQ code “11” is (0, 1, 0, 3). It is shown that.

  In the case of FIG. 6, since the representative vector corresponding to the VQ code “11” and the vector Vb obtained by calculation are the same, the VQ encoding unit 12 determines the representative vector corresponding to the VQ code “11” as The representative vector closest to the vector Vb is selected, “11” is selected as the corresponding VQ code, and is supplied to the selection unit 14 as VQ encoded data.

  The VQ encoding unit 12 attaches DR and MIN information to the generated VQ code and supplies the information to the selection unit 14 as VQ encoded data, which will be described in detail later.

  Now, the description returns to the flowchart of FIG.

  In step S4, the selection unit 14 compares the DR attached to the ADRC encoded data supplied from the ADRC encoding unit 13 with a predetermined threshold, and determines that the DR is larger than the predetermined threshold. The process proceeds to step S5.

  In step S5, the selection unit 14 outputs the ADRC encoded data supplied from the ADRC encoding unit 13 to the transmission path.

  In step S6, the blocking unit 11 determines whether or not the input of the image has been lost. If it is not determined that the input of the image has been completed, the process returns to step S1, and the subsequent processing is repeated. .

  When it is determined in step S4 that DR is not larger than the predetermined threshold, in step S6, the selection unit 14 selects an ADRC encoding block corresponding to the ADRC encoded data supplied from the ADRC encoding unit 13. The VQ encoded data of the VQ encoding block in the area corresponding to is output to the transmission path. That is, VQ encoded data of four VQ encoding blocks corresponding to the ADRC encoding block used for the threshold comparison is output.

  By the above processing, when the DR of the ADRC encoding block is larger than a predetermined threshold, the ADRC encoded data having higher error resistance than the VQ encoded data is adopted, and conversely, the DR of the ADRC encoding block is When the value is smaller than the predetermined threshold value, it is possible to realize high-quality and error-resistant encoding by adopting a VQ encoding method that is higher in compression than ADRC encoded data. In other words, while maintaining the high error tolerance of encoding, which is a feature of the ADRC encoding method, the portion that does not affect much even at the expense of error tolerance with a small DR is used as the VQ encoded data with a high compression rate, so that Encoding of the compression rate can be realized.

  Next, decoding processing by the decoding processing device 2 will be described with reference to the flowchart of FIG.

  In step S <b> 21, the determination unit 21 acquires encoded data transmitted from the encoding device 1.

  In step S22, the determination unit 21 determines whether or not the acquired encoded data is ADRC encoded data. For example, if the determination unit 21 determines that the acquired encoded data is ADRC encoded data, This is supplied to the ADRC decoding unit 23.

  In step S <b> 23, the ADRC decoding unit 23 performs ADRC decoding on the acquired encoded data, and supplies image data as a decoding result to the synthesis unit 24. That is, the ADRC decoding unit 23 performs (DR / (2 ^ (quantization bit number)) × for each code based on the DR and MIN information for each ADRC encoding block attached to the encoded data. Each code is decoded by calculating (ADRC code + MIN). Here, “^” represents a power.

  On the other hand, if it is determined in step S22 that the obtained encoded data is not ADRC encoded, that is, is VQ encoded, in step S24, the VQ decoding unit 22 performs encoding. The VQ code included in the data is subjected to VQ decoding based on the code book 25, and image data as a decoding result is supplied to the synthesis unit 24. That is, the pixel value of each pixel is decoded from each element of the representative vector corresponding to the VQ code.

  In step S25, the synthesizer 24 determines whether or not one frame of decoded image data has been supplied. For example, if it is determined that one frame of image data has been supplied, in step S26, The decoded image data is synthesized and output as an image for one frame, and is displayed on a display (not shown).

  In step S27, the determination unit 21 determines whether or not the supply of encoded data has been completed. If it is determined that the encoded data has not been completed, the process returns to step S21, and the subsequent processing is repeated. If it is determined in step S27 that the supply of encoded data has been completed, the processing ends.

  If it is determined in step S25 that the decoded image data for one frame has not been stored, the process of step S26 is skipped. That is, only when encoded image data for one frame is stored, the image data is output by the process of step S26.

  As described above, since the decoding apparatus 2 determines the encoding method of the encoded data and decodes the encoded data, the VQ encoded data obtained by the VQ encoding method, ADRC, It becomes possible to decode the encoded data mixed with the ADRC encoded data obtained by the encoding method, and to obtain a high-quality decoded image.

  Note that whether the encoded data is VQ encoded data or ADRC encoded data is determined by attaching a flag for identifying each of the VQ encoded data and ADRC encoded data, for example. It is possible to make a determination based on the flag. It is also possible to adopt any method that does not use such a flag as to whether the encoded data is VQ encoded data or ADRC encoded data.

  Next, a detailed configuration of the VQ encoding unit 12 will be described with reference to FIG.

  The VQ encoder 51 generates a vector based on the pixel value of each pixel input as a VQ encoding block, and determines a VQ code corresponding to the representative vector of the codebook 15 closest to the vector, thereby performing VQ encoding processing. To generate VQ encoded data consisting of DR, MIN (DR and MIN are part of the operation result required when generating vector Vb), and VQ code generated as a result of encoding, Supply to the separation unit 52.

  Separating section 52 separates the portion consisting of DR and MIN and the portion consisting of VQ code from the VQ encoded data supplied from VQ encoder 51, and supplies the portion consisting of DR and MIN to scrambler 53. At the same time, the VQ code is supplied to the scrambler 53 and the synthesis unit 54.

  The scrambler 53 generates scrambled data F_VQ (DR, MIN) scrambled with the VQ code from the portion consisting of DR and MIN supplied from the separation unit 52 and outputs the scrambled data F_VQ (DR, MIN).

  The combining unit 54 combines the scrambled data F_VQ (DR, MIN) and the VQ code supplied from the separating unit 52, and outputs this as VQ encoded data.

  Next, the VQ encoding process by the VQ encoding unit 12 of FIG. 8 will be described with reference to the flowchart of FIG.

  In step S41, the VQ encoder 51 determines whether image data for one VQ encoding block has been supplied, and determines that image data for one VQ encoding block has been supplied. Until the process is repeated. If it is determined in step S41 that image data for one VQ encoding block has been supplied, the process proceeds to step S42.

  In step S42, the VQ encoder 51 obtains DR and MIN based on the acquired pixel value data of the VQ encoding block, encodes the vector Vb by the above-described ADRC encoding method, and then further calculates the vector Vb. Further, based on the code book 15, the VQ code corresponding to the representative vector closest to the vector Vb is determined.

  In step S43, the VQ encoder 51 generates VQ encoded data including DR, MIN, and VQ code, for example, as shown in FIG. In FIG. 10, DR and MIN are each 8 bits and the VQ code is 16 bits, but other numbers of bits may be used.

  In step S44, the separation unit 52 separates the DR and MIN portions supplied from the VQ encoder 51 and the VQ code portion, supplies the separated DR and MIN portions to the scrambler 53, and separates the separated VQ. The code portion is supplied to the scrambler 53 and the synthesis unit 54.

  In step S45, the scrambler 53 scrambles the separated DR and MIN portions with the separated VQ code, and supplies the scrambled data F_VQ (DR, MIN) generated as a result to the synthesizer 54. The scrambling process may be any method as long as it is scrambled in a reversible manner by the separated DR and MIN parts and the data of the VQ code part. Since the portion has a total of 16 bits and the VQ code is also 16 bits, EXOR (Exclusive OR: exclusive logic circuit) processing may be performed for each of these bits.

  In step S46, the synthesizer 54 synthesizes the scrambled data F_VQ (DR, MIN) supplied from the scrambler 53 and the VQ code supplied from the separator 52, for example, VQ as shown in FIG. Generate and output encoded data. In FIG. 11, the scrambled data F_VQ (DR, MIN) is composed of 16 bits, and the VQ code is 16 bits as in FIG.

  In step S47, the VQ encoder 51 determines whether or not the image data of the VQ encoding block has ended. If it is determined that the image data has not ended, the processing returns to step S41, and the subsequent processing Is repeated, and if it is determined that the image data has been completed, the processing ends.

  With the above processing, the DR and MIN data parts are scrambled by the VQ code and added to the VQ encoded data as scrambled data F_VQ (DR, MIN). When decoding, even if the VQ data is destroyed on the transmission path, the scrambled data F_VQ (DR) is based on the DR and MIN data of the VQ encoded block near the VQ encoded block where the VQ data is destroyed. , MIN), the VQ code can be estimated (restored), and as a result, the error resistance can be improved.

  Next, the details of the configuration of the VQ encoding unit 22 will be described with reference to FIG.

  The separation unit 71 acquires VQ encoded data composed of the scrambled data F_VQ (DR, MIN) and the VQ code synthesized by the synthesis unit 54 described above, and separates the scrambled data F_VQ (DR, MIN) from the VQ code. The scramble data F_VQ (DR, MIN) is supplied to the descrambler 72 and the error processing unit 74, and the VQ code is supplied to the descrambler 72, the terminal 75a of the switching unit 75, and the error detection unit 77.

  The descrambler 72 descrambles the scrambled data F_VQ (DR, MIN) supplied from the separating unit 71 with the VQ code, generates original DR and MIN data, and generates a memory 73 and a terminal 78a of the switching unit 78. To supply. A specific process is an inverse conversion process for the conversion process when the scramble process is performed by the scrambler 53 of FIG.

  The memory 73 stores two pieces of DR and MIN data supplied from the descrambler 72. When the data becomes full, the old data is supplied from the old data to the terminal 78b of the error processing unit 74 and the switching unit 78. And overwrite the new data. With such processing, the memory 73 supplies the DR and MIN data of the VQ encoding block processed before the VQ encoding block currently processed by the descrambler 72 to the error processing unit 74. To do.

  The memory 73 overwrites new data when the error detection unit 77 does not detect an error. In other words, if there is no error in the VQ code, the descrambler 72 cannot execute the correct descrambling process, and the descrambled DR and MIN may not be returned to the correct values. This is to prevent them from being stored in the memory.

  The error processing unit 74 estimates (restores) the VQ code from the scrambled data supplied from the separation unit 71 using the DR and MIN data read from the memory 73, and supplies the VQ code to the terminal 75b of the switching unit 75.

  The switching unit 75 is controlled by the error detection unit 77, and supplies the VQ code supplied from the separation unit 71 to the VQ decoder 76 when the switch 75c is connected to the terminal 75a. When the switch 75c is connected to the terminal 75b, the VQ code restored by the error processing unit 74 is supplied to the VQ decoder 76.

  The VQ decoder 76 refers to either the VQ code supplied from the switching unit 75 or the VQ code supplied from the separation unit 71 or the VQ code estimated by the error processing unit 74 with reference to the code book 25, and from the switching unit 78. Decode processing based on the supplied DR and MIN data, that is, determine the pixel value using the vector element of the representative vector corresponding to the VQ code, and output the decoded image data to a display (not shown), Display.

  The error detection unit 77 determines whether or not an error has occurred in the VQ code supplied from the separation unit 71, and controls the memory 73 and the switching units 75 and 78 based on the determination result.

  The switching unit 78 is controlled by the error detection unit 77, and supplies the DR and MIN data supplied from the descrambler 72 to the VQ decoder 76 when the switch 78c is connected to the terminal 78a. When the switch 78c is connected to the terminal 78b, the DR and MIN data supplied from the memory 73 is supplied to the VQ decoder 76.

  Next, the VQ decoding process by the VQ decoding unit 22 in FIG. 12 will be described with reference to the flowchart in FIG. In step S61, the separation unit 61 separates the VQ encoded data as shown in FIG. 11 into the scrambled data F_VQ (DR, MIN) and the VQ code, and the scrambled data F_VQ (DR, MIN) is descrambler 72. The VQ code is supplied to the descrambler 72, the terminal 75a of the switching unit 75, and the error detecting unit 77, respectively.

  In step S62, the descrambler 72 descrambles the scrambled data F_VQ (DR, MIN) using the VQ code, generates the original DR and MIN, and outputs them to the memory 73 and the terminal 78a of the switching unit 78. To do.

  In step S63, the error processing unit 74 reads out the latest DR and MIN out of DR and MIN generated by the previous scrambling process stored in the memory 73, and uses this to read the separation unit 71. The VQ code is restored from the scrambled data F_VQ (DR, MIN) supplied by the user.

  Here, assuming that the VQ encoding block to be processed at this time is the nth VQ encoding block n on one frame image, DR and MIN read from the memory 73 in this processing are: This is for the (n−X) th processed VQ encoding block (n−X) in which no error has occurred in the most recent VQ code. Here, if there is no error in the VQ code in the VQ encoding block processed immediately before, X = 1. Therefore, in a strict sense, it is not DR and MIN obtained by descrambling the supplied scrambled data F_VQ (DR, MIN). However, since DR and MIN have a high correlation between neighboring VQ coding blocks due to image characteristics, an error occurs in the VQ code as will be described later, and VQ corresponding to scrambled data F_VQ (DR, MIN) Even when a code is missing, it is possible to estimate a VQ code that is relatively close by the DR and MIN of neighboring VQ coding blocks.

  In step S64, the error detection unit 77 determines whether there is an error in the VQ code supplied from the separation unit 71, for example, whether the data has a bit number other than 16 bits. If it is determined that no has occurred, the process proceeds to step S65.

  In step S65, the error detection unit 77 controls the switches 75c and 78c of the switching units 75 and 78 to connect to the terminals 75a and 78a, respectively.

  In step S66, the error detection unit 77 considers that the DR and MIN values supplied from the descrambler 72 are reliable and stores them in the memory 73 by replacing them with the old DR and MIN values.

  In step S68, the VQ decoder 76 refers to the VQ code supplied from the switching unit 75 on the basis of the DR and MIN supplied from the switching unit 78, refers to the code book 25, and generates a pixel from each state of the corresponding representative vector. Decode by determining the value. That is, in this case, since DR and MIN are supplied from the descrambler 72 and the VQ code is supplied from the separation unit 71, the VQ decoder 76 does not need to process the VQ code to be originally processed. The VQ encoded data of the conversion block is decoded.

  In step S69, the separation unit 71 determines whether or not the supply of the VQ encoded data is completed. If it is determined that the supply is not completed, the process returns to step S61, and the subsequent processes are repeated. If it is determined that the supply of VQ encoded data has been completed, the process is terminated.

  On the other hand, if an error is detected in step S64, in step S67, the error detection unit 77 controls the switches 75c and 78c of the switching units 75 and 78 to connect to the terminals 75b and 78b.

  That is, since DR and MIN are supplied from the memory 73 and the VQ code is supplied from the error processing unit 74, in this case, in step S68, the VQ decoder 76 performs the original processing. The VQ code estimated (restored) from the scrambled data F_VQ (DR, MIN) using the DR and MIN of the VQ coding block in the vicinity of the VQ coding block to be (DR of the neighboring VQ coding block And MIN are used to decode the scrambled data F_VQ (DR, MIN) estimated VQ code).

  With the above processing, among the VQ encoded data, even if the VQ code is destroyed on the transmission line and an error occurs, DR and MIN of the VQ encoding block near the VQ encoding block to be processed are used. By doing so, it becomes possible to infer the VQ code that caused the error, and as a result, it is possible to improve error tolerance in the encoded communication.

  In the above description, the example in which the DR and MIN included in the VQ encoded data are scrambled with the VQ code has been described. However, when the VQ code is used to scramble the DR and MIN, the VQ code is adjacent. In such a case, if noise that cannot be detected by the error detection unit 77 affects the VQ code, DR and MIN cannot be correctly descrambled (interference occurs between the VQ codes). There is a fear.

  Therefore, the DR and MIN may be scrambled by a random function associated with the VQ code instead of being directly scrambled by the VQ code.

  FIG. 14 shows a configuration of the VQ encoding unit 12 in which DR and MIN are not scrambled directly by the VQ code, but are scrambled by a random function associated with the VQ code. The same components as those of the VQ encoding unit 12 in FIG. 8 are denoted by the same reference numerals, and the description thereof will be omitted as appropriate.

  14 is different from the VQ encoding unit 12 of FIG. 8 in that a random function generating unit 91 is newly provided and a scrambler 92 is provided in place of the scrambler 53. The random function generator 91 generates a code that corresponds to each VQ code but is not related to a change between the VQ codes. More specifically, the random function generation unit 91 generates a signal pattern consisting of “1” and “0” in an originally long circulation pattern, but the same from the beginning to a predetermined number of bits depending on a value given as an initial value. “1” or “0” occurs in the pattern. Here, the continuity of the initial value and the continuity of the code up to a predetermined number of generated bits are irrelevant (that is, for example, when 1, 2, 3 are considered as three initial values, Are continuous values (adjacent values), but there is no continuity in the random function pattern generated at each initial value).

  That is, for example, when the VQ code is a 2-bit code and this code is input to the random function generator 91 as an initial value, for example, a code having a pattern as shown in FIG. 15 is generated. FIG. 15 shows a pattern from the beginning to the 16th bit.

  That is, in FIG. 15, “00”, “01”, “10”, and “11” are shown as the 2-bit VQ code that is the initial value input to the random function generating unit 91. , Patterns corresponding to each of up to 16 bits from the head are shown. In FIG. 15, when the VQ code is “00” as the initial value, the random function generating unit 91 generates a pattern “01010101010101101”, and when the VQ code is “01” as the initial value, the random function generating unit 91 Generates a pattern of “0111000111000111”, and when the VQ code is “10” as an initial value, the random function generator 91 generates a pattern of “1110001110001110” and the VQ code is “11” as an initial value. It is shown that the random function generation unit 91 generates a pattern “1001001101101100”. As shown in FIG. 15, it is clear that there is no continuity between patterns of random functions generated by the random function generator 91 even if continuous VQ codes are used as initial values. It becomes difficult to occur.

  Therefore, when a random function generator 91 is given a VQ code as an initial value, it corresponds to each VQ code on a one-to-one basis, but generates random “1” and “0” patterns, Thus, the scrambler 92 scrambles DR and MIN.

  Next, the VQ encoding process by the VQ encoding unit 12 of FIG. 14 will be described with reference to the flowchart of FIG. The processes in steps S81 to S84 and steps S87 and S88 in the flowchart of FIG. 16 are the same as the processes in steps S1 to S4 and S46 and S47 described with reference to the flowchart in FIG. The description is omitted.

  In step S 85, the random function generation unit 91 generates a random function based on the VQ code supplied from the separation unit 52 and supplies the random function to the scrambler 92.

  In step S86, the scrambler 92 scrambles the separated DR and MIN portions with the random function generated by the random function generator 91, and the scrambled data F′_VQ (DR, MIN) generated as a result. Is supplied to the synthesis unit 54.

  With the above processing, it becomes possible to scramble DR and MIN with a random function. Therefore, even if some noise is included in the VQ code on the transmission line, the scrambled data F'_VQ (DR, MIN ) Can be descrambled, and error tolerance can be improved.

  Next, the VQ decoding unit 22 corresponding to the VQ encoding unit 12 of FIG. 14 described above will be described with reference to FIG. The same components as those in the VQ decoding unit 22 in FIG. 12 are denoted by the same reference numerals, and the description thereof will be omitted as appropriate.

  17 is different from the VQ decoding unit 22 of FIG. 12 in that a random function generation unit 101 is newly provided, and the descrambler 102, the memory 103, and the error processing unit 74 are replaced with a descrambler 102, a memory 103, In addition, an error processing unit 104 is provided.

  The random function generation unit 101 is the same as the random function generation unit 91 in FIG. 14, and the pattern generated by the VQ code that is the initial value is also the same. The generated random function is stored in the descrambler 102 and the memory 103. To supply.

  The descrambler 102 descrambles the scrambled data F′_VQ (DR, MIN) with the random function generated by the random function generation unit 101 and outputs the descrambled data to the terminal 78 a of the switching unit 78 and the memory 103.

  The memory 103 is basically the same as the memory 73, but stores a random function at that time in association with descrambled DR and MIN.

  The error detection unit 104 estimates (restores) the VQ code from the scrambled data supplied from the separation unit 71 using the DR and MIN read from the memory 103 and the corresponding random function data, and the switching unit 75. To the terminal 75a.

  Next, the VQ decoding process by the VQ decoding unit 22 of FIG. 17 will be described with reference to the flowchart of FIG. The processes in steps S101, S105, S106, and S108 to S110 in the flowchart of FIG. 18 are the same as those in steps S61, S64, S65, and S67 to S69 described with reference to the flowchart in FIG. Since it is the same as the processing, its description is omitted.

  In step S <b> 102, the random function generation unit 101 generates a random function based on the VQ code supplied from the separation unit 71 and supplies the random function to the descrambler 102.

  In step S103, the descrambler 102 descrambles the scrambled data F′_VQ (DR, MIN) using the random function generated by the random function generator 101, generates the original DR and MIN, and generates the memory 103. And to the terminal 78a of the switching unit 78.

  In step S104, the error processing unit 74 reads out the DR and MIN stored in the memory 73 and the random function, and uses the scrambled data F′_VQ (DR, MIN) supplied from the separation unit 71 using the read random function. Restore the VQ code.

  In step S107, the error detection unit 77 considers that the DR and MIN supplied from the descrambler 102 and the value of the random function supplied from the random function generation unit 101 are reliable and stores them in the memory 103. On the other hand, the old DR and MIN and random function values are replaced and stored.

  Through the above processing, DR and MIN scrambled by a random function are descrambled by a random function generated by a VQ code, so that interference that easily occurs during descrambling can be suppressed. Error tolerance can be improved.

  In the above, the case where DR and MIN are scrambled by a VQ code or a random function has been described. However, the scrambled value may not be DR and MIN, for example, a VQ coding block. An average value and a standard deviation obtained from the pixel value of each pixel may be used. Also, in the ADRC encoding method, values called DR and MIN can be said to be normalization coefficients and offset values when generating ADRC encoded data based on pixel values of each pixel of the VQ encoded block. May be scrambled.

  In the above description, DR and MIN are scrambled by a VQ code or a random function. This is because of the characteristics of image data, but between pixels or between VQ coding blocks. As long as the data has a correlation with a value in the vicinity thereof, only DR or only MIN may be scrambled with a VQ code or a random function.

  According to the above, when generating encoded data, between the VQ encoding blocks such as DR and MIN, the data correlated with the value in the vicinity thereof is changed between the VQ encoding blocks such as the VQ code. By scrambling with uncorrelated data with neighboring values, it is possible to embed uncorrelated data (eg VQ code) in correlated data (eg DR or MIN). Even if uncorrelated data may be missing, it is possible to estimate missing data based on the correlation of correlated data, resulting in a high compression ratio and high Enables communication with error-resistant encoded data.

  The series of processes described above can be executed by hardware, but can also be executed by software. When a series of processes is executed by software, a program constituting the software may execute various functions by installing a computer incorporated in dedicated hardware or various programs. For example, it is installed from a recording medium in a general-purpose personal computer or the like.

  FIG. 19 shows a configuration of an embodiment of a personal computer when the electrical internal configuration of the encoding device 1 and the decoding device 2 of FIG. 1 is realized by software. The CPU 201 of the personal computer controls the overall operation of the personal computer. Further, when a command is input from the input unit 206 such as a keyboard or a mouse from the user via the bus 204 and the input / output interface 205, the CPU 201 is stored in a ROM (Read Only Memory) 202 correspondingly. Run the program. Alternatively, the CPU 201 reads a program read from the magnetic disk 211, the optical disk 212, the magneto-optical disk 213, or the semiconductor memory 214 connected to the drive 210 and installed in the storage unit 208 into a RAM (Random Access Memory) 203. To load and execute. Thereby, the functions of the encoding device 1 and the decoding device 2 in FIG. 1 described above are realized by software. Further, the CPU 201 controls the communication unit 209 to communicate with the outside and exchange data.

  As shown in FIG. 19, the recording medium on which the program is recorded is distributed to provide the program to the user separately from the computer. The magnetic disk 211 (including the flexible disk) on which the program is recorded is distributed. By a package medium comprising an optical disk 212 (including compact disc-read only memory (CD-ROM), DVD (digital versatile disk)), a magneto-optical disk 213 (including MD (mini-disc)), or a semiconductor memory 214 In addition to being configured, it is configured by a ROM 202 on which a program is recorded, a hard disk included in the storage unit 208, and the like provided to the user in a state of being pre-installed in a computer.

  In this specification, the step of describing the program recorded on the recording medium is not limited to the processing performed in time series in the order described, but of course, it is not necessarily performed in time series. Or the process performed separately is included.

  Further, in this specification, the system represents the entire apparatus constituted by a plurality of apparatuses.

It is a figure which shows the structure of the communication system to which this invention is applied. It is a figure explaining block formation of image data. It is a flowchart explaining the encoding process of the encoding apparatus of FIG. It is a figure explaining ADRC. It is a figure explaining ADRC. It is a figure explaining a code book. It is a flowchart explaining the decoding process of the decoding apparatus of FIG. It is a block diagram which shows the structure of the VQ encoding part of FIG. It is a flowchart explaining the VQ encoding process by the VQ encoding part of FIG. It is a figure explaining VQ encoded data. It is a figure explaining the VQ encoding data by which DR and MIN were scrambled. It is a block diagram which shows the structure of the VQ decoding part of FIG. It is a flowchart explaining the VQ decoding process by the VQ decoding part of FIG. It is a block diagram which shows the other structure of the VQ encoding part of FIG. It is a figure explaining the random function generate | occur | produced by the random function generation part of FIG. It is a flowchart explaining the VQ encoding process by the VQ encoding part of FIG. It is a block diagram which shows the other structure of the VQ decoding part of FIG. It is a flowchart explaining the VQ decoding process by the VQ decoding part of FIG. It is a figure explaining a recording medium.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Encoding apparatus, 2 Decoding apparatus, 12 VQ encoding part, 22 VQ decoding part, 51 VQ encoder, 52 Separation part, 53 Scrambler, 54 Synthesis part, 71 Separation part, 72 Descrambler, 73 Memory, 74 Error processing Section, 75 switching section, 76 VQ decoder, 77 error detection section, 91 random function generation section, 92 scrambler, 101 random function generation section, 102 descrambler, 103 memory, 104 error detection section

Claims (8)

Calculation data that is input data that is image data, calculates a dynamic range and a minimum value from a plurality of input data, and outputs the result as a calculation result ;
Code conversion means for converting input data into a code based on the calculation result of the calculation means;
Scrambling means for scrambling the operation result with the code by obtaining an exclusive OR of the operation result and the code;
An encoding apparatus comprising: encoding means for encoding the input data using the calculation result scrambled by the scramble means and the code. A calculation step for calculating the dynamic range and the minimum value from a plurality of input data, and outputting as a calculation result, which is input data that is image data ;
A code conversion step of converting input data into a code based on the calculation result in the processing of the calculation step;
A scramble step of scrambling the operation result with the code by obtaining an exclusive OR of the operation result and the code;
An encoding method, comprising: an encoding step of encoding the input data using the calculation result scrambled in the scramble step and the code. A calculation step for calculating the dynamic range and the minimum value from a plurality of input data, and outputting as a calculation result, which is input data that is image data ;
A code conversion step of converting input data into a code based on the calculation result in the processing of the calculation step;
A scramble step of scrambling the operation result with the code by obtaining an exclusive OR of the operation result and the code;
A computer-readable program is recorded, comprising: an encoding step for encoding the input data using the calculation result scrambled in the scramble step process and the code. recoding media. A calculation step for calculating the dynamic range and the minimum value from a plurality of input data, and outputting as a calculation result, which is input data that is image data ;
A code conversion step of converting input data into a code based on the calculation result in the processing of the calculation step;
A scramble step of scrambling the operation result with the code by obtaining an exclusive OR of the operation result and the code;
A program that causes a computer to execute an encoding step of encoding the input data using the calculation result scrambled in the scramble step and the code. Input data that is image data, and a code obtained by converting the input data based on a calculation result obtained by calculating a dynamic range and a minimum value from a plurality of input data , the calculation result, and the code In the decoding device for decoding the encoded input data including the operation result scrambled by the code by obtaining an exclusive OR with :
A descrambling means for descrambling the scrambled computation result by a code included in the encoded input data;
Error detection means for detecting an error in a code included in the encoded input data;
Storage means for storing the calculation result descrambled by the descrambling means;
Estimation means for estimating the code from the scrambled calculation result based on the calculation result stored in the storage means and used in the processing when no error is detected by the error detection means When,
Based on the error detection result of the error detection means, the descrambling process by the descrambling means and the calculation result descrambled by the code included in the encoded input data or by the descrambling means A decoding apparatus comprising: decoding means for decoding the encoded input data from the calculated calculation result and the code estimated by the estimation means. Input data that is image data, and a code obtained by converting the input data based on a calculation result obtained by calculating a dynamic range and a minimum value from a plurality of input data , the calculation result, and the code In a decoding method of a decoding device for decoding encoded input data including the operation result scrambled by the code by obtaining an exclusive OR with :
A descrambling step for descrambling the scrambled computation result by a code included in the encoded input data;
An error detection step of detecting an error in a code included in the encoded input data;
A storage step for storing the calculation result descrambled in the descrambling step;
Based on the calculation result used in the process when no error is detected in the process of the error detection step, stored in the process of the storage step, the code is calculated from the calculation result subjected to the scramble process. An estimation step to estimate;
Based on the error detection result in the error detection step, the calculation result descrambled in the descrambling step and the code included in the encoded input data, or the descrambling A decoding method comprising: the calculation result descrambled in the step processing; and a decoding step of decoding the encoded input data from the code estimated in the estimation step processing. Input data that is image data, and a code obtained by converting the input data based on a calculation result obtained by calculating a dynamic range and a minimum value from a plurality of input data , the calculation result, and the code In a recording medium on which a program for controlling a decoding device that decodes encoded input data including the operation result scrambled by the code is recorded by obtaining an exclusive OR with :
A descrambling step for descrambling the scrambled computation result by a code included in the encoded input data;
An error detection step of detecting an error in a code included in the encoded input data;
A storage control step for controlling storage of the calculation result descrambled in the descrambling step;
Based on the calculation result used in the process when the error is not detected in the process of the error detection step, the storage is controlled by the process of the storage control step, from the calculation result subjected to the scramble process, An estimating step for estimating the code;
Based on the error detection result in the error detection step, the calculation result descrambled in the descrambling step and the code included in the encoded input data, or the descrambling And a decoding step for decoding the encoded input data from the code estimated in the estimation step. Medium on which various programs are recorded. Input data that is image data, and a code obtained by converting the input data based on a calculation result obtained by calculating a dynamic range and a minimum value from a plurality of input data , the calculation result, and the code A computer that controls a decoding device that decodes the encoded input data including the operation result scrambled by the code by obtaining an exclusive OR with :
A descrambling step for descrambling the scrambled computation result by a code included in the encoded input data;
An error detection step of detecting an error in a code included in the encoded input data;
A storage control step for controlling storage of the calculation result descrambled in the descrambling step;
Based on the calculation result used in the process when the error is not detected in the process of the error detection step, the storage is controlled by the process of the storage control step, from the calculation result subjected to the scramble process, An estimating step for estimating the code;
Based on the error detection result in the error detection step, the calculation result descrambled in the descrambling step and the code included in the encoded input data, or the descrambling A program for executing the operation result descrambled in the step process and a decoding step for decoding the encoded input data from the code estimated in the estimation step process.

Images