JP4662478B2 - Bit error measuring device - Google Patents

Description

  The present invention relates to a bit error measuring device for detecting error bits included in received input data.

  The bit error measurement device measures the bit error rate of a communication device, receives the same data as the reference data transmitted to the communication device, etc., receives the received input data and the reference data Are detected, and the bit error rate and the number of bit errors, which are the ratio of bits with errors to the bit string, are displayed on the display device.

The conventional bit error measuring device has a pattern display unit that can display 32 bits per line, displays the bit contents on the target line in the order received, and displays the 32-bit contents on the target line. When the display is completed, it is known that the contents of the subsequent bits are displayed on the next target line and repeated thereafter (see, for example, Patent Document 1). Further, in the bit error measuring device of Patent Document 1, when a received bit has an error, the bit having the error is colored and emphasized.
Japanese Patent Laid-Open No. 2001-111151 (page 3, FIG. 3)

  However, for example, when a regular phenomenon occurs in which a bit error occurs once per 100 bits, the above-described conventional bit error measuring device has the contents of “0” or “1” 32 per line. It is displayed repeatedly with a fixed length of bits. As a result, even if a phenomenon with regularity occurs, it seems as if a bit error has occurred at random, so there was a problem that such a phenomenon could not be easily noticed by testers. .

  The present invention has been made to solve the conventional problems, and an object of the present invention is to provide a bit error measuring apparatus capable of supporting easy analysis of factors that cause error bits.

The bit error measuring device according to the present invention is a bit error measuring device for detecting an error bit of input data received from a measurement object, and detecting an error bit for detecting whether each bit of received input data is an error bit or not. And a display block corresponding to one or a plurality of consecutive bits of the received input data in response to a detection result stored in the error bit detection unit, and an error bit is included in the corresponding bit A display processing unit for displaying on a display device a bit display diagram in which a plurality of display blocks that can be identified as to whether or not they are arranged are sequentially arranged into a display block row, and the display block row is further sequentially arranged in parallel; When the display processing unit is instructed to change the number of display blocks arranged in the display block row, which is the width of the bit display diagram, the instruction is given. And in accordance with the number, it has a configuration that displays the bit display view to rearrange the display blocks.
With this configuration, in accordance with an instruction to change the width of the bit display diagram, the display block is rearranged and the bit display diagram is displayed. If the width of the bit display diagram is appropriate, error bits are regularly arranged and displayed on the bit display diagram, and it is possible to assist in easily analyzing the cause of the error bit generation.

In the bit error measuring apparatus of the present invention, when the display processing unit is instructed to reduce or enlarge the contents displayed in the bit display diagram, the display processing unit 1 of the received input data corresponding to the display block. Alternatively, the bit display diagram is displayed by changing the number of a plurality of consecutive bits so that the number of bits corresponding to the scale of reduction or enlargement corresponds to one display block.
With this configuration, it is possible to assist in easily analyzing the cause of the error bit by reducing or enlarging the content displayed in the bit display diagram.

In the bit error measuring apparatus of the present invention, the error bit detection unit detects and stores whether the error bit is 1 error bit with 0 as 1 or 0 error bit with 1 as 0, and The display processing unit is configured to display the bit display diagram in which the display block in which the 1 or 0 error bit detected by the error bit detection unit is identified is arranged on the display device.
With this configuration, if each error bit is colored differently, the contents of the error bit can be accurately expressed.

In the bit error measuring device according to the present invention, the display processing unit may receive the received input data corresponding to the display block when a specific range is selected from the contents displayed in the bit display diagram. A new bit display diagram in which the number of bits corresponding to a predetermined scale for expanding the specific range is changed to correspond to one display block by changing the number of one or a plurality of consecutive bits is displayed on the display device It has the composition to do.
With this configuration, it is possible to easily analyze the cause of the error bit by selecting and enlarging a specific range from the contents displayed in the bit display diagram.

In the bit error measuring apparatus of the present invention, the display processing unit stores in advance the number of bits corresponding to the input data to be received, and stores the bit display diagram when the bit display diagram is displayed on the display device. The number of bits arranged in the display block row and the number of bits corresponding to the display block are determined based on the number of bits, and the bit display diagram is displayed on the display device.
With this configuration, the width derived from the frame size conforming to the communication standard is determined in advance, and the display block is rearranged according to the predetermined width to display the bit display diagram. When a repetitive regular phenomenon occurs, error bits are regularly arranged and displayed on the bit display diagram, and it is possible to support easy analysis of the factors that cause the error bits.

  The present invention provides a bit error measuring device that can support easy analysis of factors that cause error bits.

  Hereinafter, a bit error measuring apparatus according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a configuration diagram of a bit error measuring apparatus according to an embodiment of the present invention. In the embodiment of the present invention, the bit error measuring device 10 transmits a signal representing data serving as a reference to the measuring object 9, and the measuring object 9 receives and receives the signal transmitted from the bit error measuring device 10. The signal is transmitted to the bit error measuring device 10.
Note that the signal may be transmitted to the measurement target 9 by a device other than the bit error measurement device 10, or the measurement target 9 itself may generate and transmit a signal.

  The bit error measuring apparatus 10 detects an error bit by comparing input data received from the measurement object 9 with reference data. Further, the bit error measuring device 10 can calculate a bit error rate (BER) that is a ratio of error bits to the number of bits of input data.

  The measurement object 9 may be any object as long as it transmits a signal representing data consisting of a bit string. The signal transmitted / received between the bit error measuring apparatus 10 and the measurement target 9 may be an electrical signal or an optical signal.

Hereinafter, the bit error measuring apparatus 10 will be described. 1 includes a data storage unit 11, a signal transmission unit 12, a signal reception unit 13, a synchronization detection unit 14, an operation unit 21, an error bit detection unit 22, a display processing unit 23, and a display device. 19. The error bit detection unit 22 includes a comparison unit 15 and a comparison data storage unit 16, and the display processing unit 23 includes a display control unit 17, a display block specifying unit 18, and a width information storage unit 20. .
The data storage unit 11, the comparison data storage unit 16, and the width information storage unit 20 are configured by a memory such as a RAM. The signal transmission unit 12, the signal reception unit 13, the synchronization detection unit 14, the comparison unit 15, and the display processing unit 23 is constituted by an integrated circuit or the like.

  Further, as shown in FIG. 1, the bit error measuring apparatus 10 may be configured as an integrated unit, but is not necessarily integrated, and a display processing unit 23 such as a CPU, a keyboard, etc. The operation device 21 and the display device 19 having a liquid crystal screen or the like may be replaced by a personal computer, or the signal reception unit 13, the synchronization detection unit 14, the comparison unit 15, and the comparison data storage unit 16 may be configured as a package.

  The data storage unit 11 stores in advance data serving as a reference having, for example, a 128 Mbit size. The signal transmission unit 12 transmits a signal representing data read from the data storage unit 11 to the measurement target 9.

  The signal receiving unit 13 receives a signal transmitted from the measurement object 9 and outputs the received input data to the synchronization detecting unit 14.

  The synchronization detection unit 14 synchronizes the data read from the data storage unit 11 with the received input data. Then, the comparison unit 15 described later is notified that synchronization has been achieved.

  After synchronization is established by the synchronization detection unit 14, the comparison unit 15 performs synchronization in order from the bit of the data storage unit 11 at the position when the bit error measurement is started according to an instruction from the tester or the like via the operation unit 21. An error bit is detected by comparison with the bit output from the detection unit 14.

  The comparison unit 15 sequentially compares the bit output from the synchronization detection unit 14 and the bit stored in the data storage unit 11, for example, sets an error bit that does not match each bit to 1 and sets a bit without error. As 0, the presence or absence of an error bit is stored in the comparison data storage unit 16.

  The display block specifying unit 18 specifies whether or not there is an error bit in the contents of the display block when displaying the bit display diagram in which the display blocks corresponding to the bits of the received input data are arranged. Yes. Here, FIG. 2 is a diagram for explaining the bit display diagram. FIG. 2A shows an example of a bit display diagram having 32 columns in which one square corresponds to one display block. When the bit display diagram is one display block per bit, it represents the contents of 1 bit received in the order of the numbers in the display block.

  When there is one display block per bit, the display block specifying unit 18 specifies the content of the display block as it is from the presence or absence of error bits stored in the comparison data storage unit 16. Further, when the display block specifying unit 18 specifies that the content of the display block is an error bit, the display block specifying unit 18 further determines from the data in the data storage unit 11 1 error bit that was originally set to 0 by mistake, It is designed to identify whether the error bit is 0 which has been erroneously set to 0.

  Furthermore, when the examiner or the like is instructed to reduce or enlarge the content displayed in the bit display diagram via the operation unit 21, the display block specifying unit 18 sets the designated number of bits according to the scale of reduction or enlargement. It comes to ask for. The designated bit number is the number of bits corresponding to one display block. For example, when the designated number of bits is 4, that is, one display block per 4 bits, if k is a natural number, the bits received from the (4k−3) th to the 4kth are used as the kth display block. When there is one or more error bits in the allocated bits from the (4k-3) th to the 4kth, the contents of the kth display block are specified as error bits. When the contents of one display block are mixed with 1 error bit and 0 error bit, the display block specifying unit 18 specifies the mixed error bit.

  The display control unit 17 displays a bit display diagram on the display device 19 so that the presence or absence of the error bit specified by the display block specifying unit 18 can be identified by the display block. For example, as shown in FIG. 2B, the display control unit 17 colors and displays a display block indicating that there is an error bit. Note that in the bit display diagram illustrated in FIG. 2A, not all display blocks may be displayed on the screen. A part of the display blocks in the range surrounded by the broken line in FIG. 2B may be displayed, and this range may be scrolled.

  When distinguishing error bits as 1 error bits and 0 error bits, the display control unit 17 colors the display blocks with different colors. Further, when the content of the display block is a mixed error bit, the display control unit 17 adds an intermediate color between the color corresponding to the 1 error bit and the color corresponding to the 0 error bit to the display block. You may make it display with coloring.

  Further, when the tester or the like instructs the change of the width of the bit display diagram via the operation unit 21, the display control unit 17 displays the display corresponding to the received bit in accordance with the display column corresponding to the designated width. The block is rearranged to display the bit display diagram. Here, the width of the bit display diagram is the number of display blocks in one display column (display block column). For example, when changing the display column from 32 bits to the display column 16 bits, the display control unit 17 displays the 1st to 16th received bits in the 1st row and the 17th to 32nd received bits in the 2nd row. And then repeatedly.

  As shown in FIG. 3A, the bit display diagram when the display column 32 having the display block indicating that there is an error bit is changed to the display column 50 is shown in FIG. Shown in B). In FIG. 3 (A), although there is a regularity that one bit error is repeatedly generated for every 50 bits, it seems that error bits are generated randomly. In FIG. 3 (B), The error bits appear in the first column, and it is easy to see that the error bits are regularly generated.

The display control unit 17 may display a bit display diagram by arranging display blocks corresponding to the received bits in accordance with a display column corresponding to a predetermined width. Note that the predetermined width is derived from the size of a frame having a fixed length conforming to the communication standard.
In this case, the number of bits derived from the frame size is stored in advance in the width information storage unit 20 in the display processing unit 23, and the number of display blocks arranged in one display block row which is the width of the bit display diagram Based on this, the number of bits corresponding to one display block is determined, and the bit display diagram is displayed accordingly.

  Furthermore, when the tester or the like selects a specific range from the contents displayed in the bit display diagram via the operation unit 21, the display block specifying unit 18 corresponds to a scale for expanding the specific range. The number of bits may correspond to one display block, and it may be specified whether or not there is an error bit in the bit corresponding to a specific range.

For example, FIG. 4 shows a bit display diagram in which a display block (one square) has three display columns, and in FIG. 4A, there is one display block for every four bits. The numbers in the display block are the order of the received bits. When the display block corresponding to the 1st to 4th, 5th to 8th, 33rd to 36th, and 37th to 40th bits is selected, the display block specifying unit 18 is enlarged by a factor of four, for example, one display block per bit And whether or not there is an error bit in the bits corresponding to the selected display block, that is, the 1st to 4th, 5th to 8th, 33rd to 36th, and 37th to 40th bits. After that, as shown in FIG. 4B, the display control unit 17 colors and displays the display block indicating that there is an error bit.
Furthermore, when the tester or the like selects a specific range from the contents displayed in the bit display diagram via the operation unit 21, the display control unit 17 displays the content of the input data corresponding to the specific range. You may do it.
For example, as described above, when an area is selected in FIG. 4A, the bit of the input data corresponding to the area is displayed as 1/0 as shown in FIG. In the example of FIG. 4C, the 1st to 8th bits of the input data are displayed in the upper stage, and the 33rd to 40th bits are displayed in the lower stage.

  Here, the operation of the bit error measuring apparatus according to the embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a flowchart showing an example of the operation of the bit error measuring apparatus according to the embodiment of the present invention.

  First, after the comparison unit 15 finishes storing the presence or absence of error bits for all received bits in the comparison data storage unit 16, a tester or the like displays a bit display diagram indicating the presence or absence of error bits via the operation unit 21. Suppose you give an instruction to do so. At this time, the display block specifying unit 18 determines whether or not there is an error bit in the bit corresponding to one selected display block (S1).

  Next, if there is even one error bit in step S1, the display block specifying unit 18 specifies the display color of the display block of the bit display diagram to be displayed (S2). For example, from the information acquired by the display block specifying unit 18, there are three cases: only one error bit, only 0 error bits, and 0 and 1 error bits mixed. The display color of the display block is specified according to each case.

  If there is no error bit in step S1, the display block specifying unit 18 sets the display block to white (S3).

  The display block specifying unit 18 determines whether or not the display colors of all the display blocks included in the bit display diagram to be displayed are specified (S4), and does not specify the display colors of all the display blocks. If so, the next display block is selected (S5). When the display colors of all the display blocks are specified, the display control unit 17 displays a bit display diagram according to the display colors specified by the display block specifying unit 18 and the set columns (S6).

  When the bit display diagram is displayed, it is determined whether or not there is an instruction for reducing or enlarging the content displayed in the bit display diagram (S7). When there is an instruction for reducing or enlarging, the display block is specified. The unit 18 sets the designated number of bits according to the scale of reduction or enlargement (S8), and is executed from step S1.

  Also, it is determined whether or not there is an instruction to change the width of the bit display diagram (S9), and when there is an instruction to change the width of the bit display diagram, the display control unit 17 corresponds to the instructed width. A column to be displayed is set (S10), and the process is executed from step S1, and the display block is rearranged to display the bit display diagram.

  As described above, the bit error measuring apparatus according to the embodiment of the present invention displays the bit display diagram by rearranging the display blocks in accordance with the instruction to change the width of the bit display diagram. When a regular phenomenon in which bit errors occur repeatedly occurs, if the width of the bit display diagram is appropriate, the error bits are regularly displayed in the bit display diagram, making it easy to determine the cause of error bits. Can support analysis.

  As described above, the present invention has an effect that it is possible to easily analyze the cause of occurrence of error bits, and is useful as a bit error measurement device that measures the bit error rate of a digital signal.

Configuration diagram of bit error measuring apparatus according to an embodiment of the present invention Diagram for explaining the bit display diagram The figure for demonstrating rearranging an error bit according to the width | variety of a bit display figure Diagram for explaining expansion of a specific range when a display block in a specific range is selected The flowchart showing an example of operation | movement of the bit error measuring apparatus which concerns on embodiment of this invention

Explanation of symbols

DESCRIPTION OF SYMBOLS 9 Measurement object 10 Bit error measuring apparatus 11 Data storage part 12 Signal transmission part 13 Signal reception part 14 Synchronization detection part 15 Comparison part 16 Comparison data storage part 17 Display control part 18 Display block specific part 19 Display apparatus 20 Width information storage part 21 Operation unit 22 Error bit detection unit 23 Display processing unit

Claims (5)

In a bit error measuring device for detecting an error bit of input data received from a measurement object (9),
An error bit detector (22) for detecting and storing whether or not each bit of the received input data is an error bit;
It is a display block corresponding to one or a plurality of consecutive bits of the received input data in response to the detection result stored in the error bit detection unit, and whether there is an error bit in the corresponding bit A display processing section (23) for displaying a bit display diagram in which a plurality of display blocks that can be identified are sequentially arranged as a display block row and a plurality of the display block rows are sequentially arranged in parallel on the display device (19); With
When the display processing unit is instructed to change the number of display blocks arranged in the display block row which is the width of the bit display diagram, the display processing unit replays the plurality of display blocks according to the instructed number. Arranging and displaying the bit display diagram, and when reduction or enlargement of the content displayed in the bit display diagram is instructed, one or a plurality of consecutive bits of the received input data corresponding to the display block The bit error measurement device is characterized in that the bit display diagram is displayed in correspondence with one display block with the number of bits corresponding to the scale of reduction or enlargement . In a bit error measuring device for detecting an error bit of input data received from a measurement object (9),
An error bit detector (22) for detecting and storing whether or not each bit of the received input data is an error bit;
It is a display block corresponding to one or a plurality of consecutive bits of the received input data in response to the detection result stored in the error bit detection unit, and whether there is an error bit in the corresponding bit A display processing section (23) for displaying a bit display diagram in which a plurality of display blocks that can be identified are sequentially arranged as a display block row and a plurality of the display block rows are sequentially arranged in parallel on the display device (19); With
When the display processing unit is instructed to change the number of display blocks arranged in the display block row which is the width of the bit display diagram, the display processing unit replays the plurality of display blocks according to the instructed number. Arranging and displaying the bit display diagram, and when a specific range is selected from the contents displayed in the bit display diagram, one or a plurality of continuous input data of the received input data corresponding to the display block The number of bits is changed, and a new bit display diagram in which the number of bits corresponding to a predetermined scale for expanding the specific range is associated with one display block is displayed on the display device. Bit error measuring device. The display processing unit
Pre-store the number of bits corresponding to the input data to be received;
When displaying the bit display diagram on the display device, the number of bits arranged in the display block column and the number of bits corresponding to the display block are determined based on the stored number of bits, and the bit display The bit error measuring device according to claim 1 or 2 , wherein a figure is displayed on the display device. In a bit error measuring device for detecting an error bit of input data received from a measurement object (9),
An error bit detector (22) for detecting and storing whether or not each bit of the received input data is an error bit;
It is a display block corresponding to one or a plurality of consecutive bits of the received input data in response to the detection result stored in the error bit detection unit, and whether there is an error bit in the corresponding bit A display processing section (23) for displaying a bit display diagram in which a plurality of display blocks that can be identified are sequentially arranged as a display block row and a plurality of the display block rows are sequentially arranged in parallel on the display device (19); With
The display processing unit stores in advance the number of bits corresponding to the input data to be received, and when an instruction is given to change the number of display blocks arranged in the display block row which is the width of the bit display diagram The plurality of display blocks are rearranged in accordance with the instructed number, and the number of bits arranged in the display block row based on the stored number of bits and the number of bits corresponding to the display block And the bit display diagram is displayed. The error bit detector is
Detect and store whether the error bit is 1 error bit with 0 as 1 or 0 error bit with 1 as 0,
The display processing unit
Claims 1 to 4, characterized in that displaying the bit display diagram the error bit detection unit is disposed said display block error bit is to allow identification of the 1 or 0 is detected on the display device The bit error measuring device according to any one of the above.

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