JP4768314B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4768314B2 JP4768314B2 JP2005142886A JP2005142886A JP4768314B2 JP 4768314 B2 JP4768314 B2 JP 4768314B2 JP 2005142886 A JP2005142886 A JP 2005142886A JP 2005142886 A JP2005142886 A JP 2005142886A JP 4768314 B2 JP4768314 B2 JP 4768314B2
- Authority
- JP
- Japan
- Prior art keywords
- organic material
- substrate
- semiconductor chip
- material substrate
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/877—Bump connectors and die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
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- Wire Bonding (AREA)
Description
Claims (4)
- 有機材料系基板と、
前記有機材料系基板の一方の面のほぼ中央に、一方の面がフリップチップ接続された半導体チップと、
前記半導体チップと前記有機材料系基板との隙間を充填して設けられた樹脂と、
前記有機材料系基板を挟んで前記半導体チップに対向する前記有機材料系基板の他方の面に設けられた、該半導体チップとほぼ同じ主面面積を有する、キャパシタ素子が作り込まれているチップ部材と、
前記有機材料系基板の前記一方の面の、前記半導体チップが位置する領域の外側周縁領域に固定され、かつ、前記半導体チップの前記一方の面とは反対の側の面に対しても固定されているリッド部材と、
前記有機材料系基板の前記一方の面とは反対の側の面に突起して設けられた基板支持部材と
を具備することを特徴とする半導体装置。 - 有機材料系基板と、
前記有機材料系基板の一方の面のほぼ中央に、一方の面がフリップチップ接続された半導体チップと、
前記半導体チップと前記有機材料系基板との隙間を充填して設けられた樹脂と、
前記有機材料系基板を挟んで前記半導体チップに対向する前記有機材料系基板の他方の面に設けられた、該半導体チップとほぼ同じ主面面積を有する、キャパシタ素子が作り込まれているチップ部材と、
前記有機材料系基板の前記一方の面の、前記半導体チップが位置する領域の外側周縁領域に固定され、かつ、前記半導体チップの前記一方の面とは反対の側の面に対しても固定されているリッド部材と、
前記リッド部材の前記有機材料系基板に固定される部位の付近から延設され、前記有機材料系基板の厚み方向にその厚みを超えるように突起して設けられた基板支持部材と
を具備することを特徴とする半導体装置。 - 前記有機材料系基板が、前記基板支持部材からの逃げに切り欠きまたは貫通孔を有する形状であることを特徴とする請求項2記載の半導体装置。
- 前記リッド部材が、
前記有機材料系基板の前記一方の面の、前記半導体チップが位置する領域の前記外側周縁領域に固定されたスティフナーと、
前記半導体チップの前記一方の面とは反対の側の前記面に対して固定されており、かつ前記スティフナーに対しても固定されているカバープレートと
を有することを特徴とする請求項1または2記載の半導体装置。
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005142886A JP4768314B2 (ja) | 2005-05-16 | 2005-05-16 | 半導体装置 |
| US11/433,424 US7521787B2 (en) | 2005-05-16 | 2006-05-15 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005142886A JP4768314B2 (ja) | 2005-05-16 | 2005-05-16 | 半導体装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2006319266A JP2006319266A (ja) | 2006-11-24 |
| JP4768314B2 true JP4768314B2 (ja) | 2011-09-07 |
Family
ID=37418360
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2005142886A Expired - Fee Related JP4768314B2 (ja) | 2005-05-16 | 2005-05-16 | 半導体装置 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US7521787B2 (ja) |
| JP (1) | JP4768314B2 (ja) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7378733B1 (en) | 2006-08-29 | 2008-05-27 | Xilinx, Inc. | Composite flip-chip package with encased components and method of fabricating same |
| KR20090056044A (ko) * | 2007-11-29 | 2009-06-03 | 삼성전자주식회사 | 반도체 소자 패키지 및 이를 제조하는 방법 |
| US7473618B1 (en) * | 2008-04-22 | 2009-01-06 | International Business Machines Corporation | Temporary structure to reduce stress and warpage in a flip chip organic package |
| US7731079B2 (en) * | 2008-06-20 | 2010-06-08 | International Business Machines Corporation | Cooling apparatus and method of fabrication thereof with a cold plate formed in situ on a surface to be cooled |
| JPWO2011121779A1 (ja) * | 2010-03-31 | 2013-07-04 | 富士通株式会社 | マルチチップモジュール、プリント配線基板ユニット、マルチチップモジュールの製造方法およびプリント配線基板ユニットの製造方法 |
| JP6199601B2 (ja) * | 2013-05-01 | 2017-09-20 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| JP6157998B2 (ja) * | 2013-09-03 | 2017-07-05 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| JP6356450B2 (ja) * | 2014-03-20 | 2018-07-11 | 株式会社東芝 | 半導体装置および電子回路装置 |
| JP1579162S (ja) * | 2016-08-05 | 2020-06-15 | ||
| US11569156B2 (en) | 2019-10-27 | 2023-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device, electronic device including the same, and manufacturing method thereof |
| DE102020108575B4 (de) | 2019-10-27 | 2023-07-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Halbleiter-bauelement, elektronische vorrichtung mit diesem und verfahren zu deren herstellung |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001035960A (ja) | 1999-07-21 | 2001-02-09 | Mitsubishi Electric Corp | 半導体装置および製造方法 |
| JP3367554B2 (ja) * | 1999-10-13 | 2003-01-14 | 日本電気株式会社 | フリップチップパッケージ |
| JP3414342B2 (ja) | 1999-11-25 | 2003-06-09 | 日本電気株式会社 | 集積回路チップの実装構造および実装方法 |
| JP2001210674A (ja) * | 2000-01-28 | 2001-08-03 | Hitachi Ltd | ベアチップicの実装方法 |
| JP3300698B2 (ja) * | 2000-05-17 | 2002-07-08 | 松下電器産業株式会社 | 半導体実装対象中間構造体及び半導体装置の製造方法 |
| JP2001339037A (ja) * | 2000-05-26 | 2001-12-07 | Matsushita Electric Ind Co Ltd | 半導体素子の実装構造体 |
| US7323767B2 (en) * | 2002-04-25 | 2008-01-29 | Micron Technology, Inc. | Standoffs for centralizing internals in packaging process |
| JP2004063532A (ja) * | 2002-07-25 | 2004-02-26 | Kyocera Corp | 半導体素子収納用パッケージおよび半導体装置 |
| US20050077080A1 (en) * | 2003-10-14 | 2005-04-14 | Adesoji Dairo | Ball grid array (BGA) package having corner or edge tab supports |
-
2005
- 2005-05-16 JP JP2005142886A patent/JP4768314B2/ja not_active Expired - Fee Related
-
2006
- 2006-05-15 US US11/433,424 patent/US7521787B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| US20060255472A1 (en) | 2006-11-16 |
| US7521787B2 (en) | 2009-04-21 |
| JP2006319266A (ja) | 2006-11-24 |
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