JP4897281B2 - 配線基板の製造方法及び電子部品実装構造体の製造方法 - Google Patents
配線基板の製造方法及び電子部品実装構造体の製造方法 Download PDFInfo
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- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
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- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
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- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
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- H05K2201/03—Conductive materials
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- H05K2203/01—Tools for processing; Objects used during processing
- H05K2203/0147—Carriers and holders
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- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
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- H05K2203/0522—Using an adhesive pattern
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- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/15—Position of the PCB during processing
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- H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
- H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
- H10P72/7424—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self-supporting substrates
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49128—Assembling formed circuit to base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49147—Assembling terminal to base
- Y10T29/49149—Assembling terminal to base by metal fusion bonding
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
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Description
図1〜図4は本発明の第1実施形態の配線基板の製造方法を順に示す断面図である。
図6及び図7は本発明の第2実施形態の電子部品実装構造体の製造方法を示す断面図である。第2実施形態では、本発明の配線基板の製造方法の技術思想に基づいて、配線基板上に電子部品を実装する好適な方法について説明する。
Claims (9)
- ガラス不織布に樹脂を含侵させた仮基板を用意する工程と、
前記仮基板上の配線形成領域の外周部に銅からなる金属箔の周縁側を接着層で選択的に接着することにより、前記仮基板の少なくとも片面に前記金属箔を仮固定する工程と、
前記金属箔の上に、所要部に開口部が設けられためっきレジスト膜を形成する工程と、
前記金属箔をめっき給電層に利用する電解めっきにより、前記開口部内に露出する金属箔の上に接続パッドを形成する工程と、
前記めっきレジスト膜を除去する工程と、
前記金属箔及び前記接続パッドの上に、樹脂からなる絶縁層と銅からなる配線層とを積層して、前記接続パッドを含むビルドアップ配線層を形成する工程と、
前記仮基板上に前記金属箔及びビルドアップ配線層が形成された構造体の前記接着層より内側部分を切断することにより、前記金属箔を前記仮基板から分離して、前記金属箔の上に前記ビルドアップ配線層が形成された配線部材を得る工程と、
前記配線部材を構成する前記ビルドアップ配線層の前記接続パッドに対して前記金属箔を選択的に除去して前記接続パッドを露出させる工程とを有し、
前記仮基板の熱膨張係数は30乃至50ppm/℃であり、前記ビルドアップ配線層の熱膨張係数は20乃至50ppm/℃であることを特徴とする配線基板の製造方法。 - 前記ビルドアップ配線層の前記接続パッドが電子部品を実装するための内部接続パッドとなり、前記ビルドアップ配線層の最上の配線層が外部接続パッドとなることを特徴とする請求項1に記載の配線基板の製造方法。
- 前記ビルドアップ配線層の前記接続パッドが外部接続パッドとなり、前記ビルドアップ配線層の最上の配線層が電子部品を実装するための内部接続パッドとなることを特徴とする請求項1に記載の配線基板の製造方法。
- 前記接続パッドは、金、錫、又はニッケルからなることを特徴とする請求項1乃至3のいずれか一項に記載の配線基板の製造方法。
- 前記仮基板の両面側に、前記金属箔及び前記ビルドアップ配線層が形成され、前記仮基板の両面側から前記配線部材がそれぞれ得られることを特徴とする請求項1乃至4のいずれか一項に記載の配線基板の製造方法。
- ガラス不織布に樹脂を含侵させた仮基板を用意する工程と、
前記仮基板上の配線形成領域の外周部に銅からなる金属箔の周縁側を接着層で選択的に接着することにより、前記仮基板の少なくとも片面に前記金属箔を仮固定する工程と、
前記金属箔の上に、所要部に開口部が設けられためっきレジスト膜を形成する工程と、
前記金属箔をめっき給電層に利用する電解めっきにより、前記開口部内に露出する金属箔の上に接続パッドを形成する工程と、
前記めっきレジスト膜を除去する工程と、
前記金属箔及び前記接続パッドの上に、樹脂からなる絶縁層と銅からなる配線層とを積層して、前記接続パッドを含むビルドアップ配線層を形成する工程と、
前記仮基板上に前記金属箔及びビルドアップ配線層が形成された構造体の前記接着層より内側部分を切断することにより、前記金属箔を前記仮基板から分離して、前記金属箔の上に前記ビルドアップ配線層が形成された配線部材を得る工程と、
前記配線部材の最上の前記配線層に電子部品を電気的に接続して実装する工程と、
前記配線部材を構成する前記ビルドアップ配線層の前記接続パッドに対して前記金属箔を選択的に除去して前記接続パッドを露出させる工程とを有し、
前記仮基板の熱膨張係数は30乃至50ppm/℃であり、前記ビルドアップ配線層の熱膨張係数は20乃至50ppm/℃であることを特徴とする電子部品実装構造体の製造方法。 - ガラス不織布に樹脂を含侵させた仮基板を用意する工程と、
前記仮基板上の配線形成領域の外周部に銅からなる金属箔の周縁側を接着層で選択的に接着することにより、前記仮基板の少なくとも片面に前記金属箔を仮固定する工程と、
前記金属箔の上に、所要部に開口部が設けられためっきレジスト膜を形成する工程と、
前記金属箔をめっき給電層に利用する電解めっきにより、前記開口部内に露出する金属箔の上に接続パッドを形成する工程と、
前記めっきレジスト膜を除去する工程と、
前記金属箔及び前記接続パッドの上に、樹脂からなる絶縁層と銅からなる配線層とを積層して、前記接続パッドを含むビルドアップ配線層を形成する工程と、
前記ビルドアップ配線層の最上の配線層に電気的に接続される電子部品を実装する工程と、
前記仮基板上に前記金属箔及びビルドアップ配線層が形成された構造体の前記接着層より内側部分を切断することにより、前記金属箔を前記仮基板から分離して、前記金属箔上に形成された前記ビルドアップ配線層に前記電子部品が実装された配線部材を得る工程と、
前記配線部材を構成する前記ビルドアップ配線層の前記接続パッドに対して前記金属箔を選択的に除去して前記接続パッドを露出させる工程とを有し、
前記仮基板の熱膨張係数は30乃至50ppm/℃であり、前記ビルドアップ配線層の熱膨張係数は20乃至50ppm/℃であることを特徴とする電子部品実装構造体の製造方法。 - 前記仮基板の両面側に、前記金属箔及び前記ビルドアップ配線層が形成され、前記仮基板の両面側から前記配線部材がそれぞれ得られることを特徴とする請求項6又は7に記載の電子部品実装構造体の製造方法。
- 前記接続パッドは、金、錫、又はニッケルからなることを特徴とする請求項6乃至8のいずれか一項に記載の電子部品実装構造体の製造方法。
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| Application Number | Priority Date | Filing Date | Title |
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| JP2005353142A JP4897281B2 (ja) | 2005-12-07 | 2005-12-07 | 配線基板の製造方法及び電子部品実装構造体の製造方法 |
| KR1020060108201A KR20070059945A (ko) | 2005-12-07 | 2006-11-03 | 배선 기판의 제조 방법 및 전자 부품 실장 구조체의 제조방법 |
| TW095141489A TWI399153B (zh) | 2005-12-07 | 2006-11-09 | 配線基板的製造方法及電子組件安裝結構的製造方法(一) |
| US11/595,916 US7543374B2 (en) | 2005-12-07 | 2006-11-13 | Method of manufacturing wiring substrate |
| CNA2006101467609A CN1980542A (zh) | 2005-12-07 | 2006-11-22 | 制造布线基板的方法和制造电子元件安装结构的方法 |
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| JP2005353142A JP4897281B2 (ja) | 2005-12-07 | 2005-12-07 | 配線基板の製造方法及び電子部品実装構造体の製造方法 |
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| JP4897281B2 true JP4897281B2 (ja) | 2012-03-14 |
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| KR100969412B1 (ko) * | 2008-03-18 | 2010-07-14 | 삼성전기주식회사 | 다층 인쇄회로기판 및 그 제조방법 |
| US8104171B2 (en) | 2008-08-27 | 2012-01-31 | Advanced Semiconductor Engineering, Inc. | Method of fabricating multi-layered substrate |
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- 2006-11-13 US US11/595,916 patent/US7543374B2/en active Active
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| TWI399153B (zh) | 2013-06-11 |
| US7543374B2 (en) | 2009-06-09 |
| US20070124925A1 (en) | 2007-06-07 |
| JP2007158150A (ja) | 2007-06-21 |
| CN1980542A (zh) | 2007-06-13 |
| KR20070059945A (ko) | 2007-06-12 |
| TW200730064A (en) | 2007-08-01 |
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