JP5352437B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5352437B2 JP5352437B2 JP2009271258A JP2009271258A JP5352437B2 JP 5352437 B2 JP5352437 B2 JP 5352437B2 JP 2009271258 A JP2009271258 A JP 2009271258A JP 2009271258 A JP2009271258 A JP 2009271258A JP 5352437 B2 JP5352437 B2 JP 5352437B2
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC]
- H05K1/185—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC] associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards
- H05K1/186—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC] associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards manufactured by mounting on or connecting to patterned circuits before or during embedding
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W44/00—Electrical arrangements for controlling or matching impedance
- H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
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- H—ELECTRICITY
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09118—Moulded substrate
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/04—Soldering or other types of metallurgic bonding
- H05K2203/041—Solder preforms in the shape of solder balls
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/015—Manufacture or treatment of bond wires
- H10W72/01515—Forming coatings
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
- H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
- H10W72/5524—Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/59—Bond pads specially adapted therefor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/01—Manufacture or treatment
- H10W74/016—Manufacture or treatment using moulds
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
- H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
- H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Adhesives Or Adhesive Processes (AREA)
- Conductive Materials (AREA)
- Combinations Of Printed Boards (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
少なくとも2枚の配線基板間に電子部品が搭載され、前記2枚の配線基板の内の少なくとも1枚の前記配線基板と前記電子部品とが電気的に接続されており、前記2枚の配線基板同士が電気的に接続され、かつ、前記電子部品を含む前記2枚の配線基板間が樹脂封止され、前記2枚の配線基板同士の電気的接続に導電性材料が用いられている半導体装置である。
2 高周波パワーアンプチップ
3 フリップチップバンプ
4 アンテナスイッチ
5 フィルタ
6 有機金属柱
6a 有機金属ペースト
7 印刷マスク
8 開口部
9 空間
10 下層側配線基板
11 金型
12 ボンディングパッド
13 マイコンチップ
14 バンプ
15 メモリチップ
16 回路部品
20 上層側配線基板
30 電子部品(半導体素子)
32 電極
40 半田ボール
42 Cuコア
44 半田
45 封止樹脂
46 ボンディングワイヤ
47 樹脂
48 電子部品内蔵基板
L1 直径
L2、L4 接続ピッチ
L3 高さ
Claims (5)
- 以下の工程を含む半導体装置の製造方法:
(a)表面、および前記表面とは反対側の裏面を有する第1配線基板を用意する工程;
(b)前記(a)工程の後、前記第1配線基板の前記表面に第1電子部品を搭載する工程;
(c)前記(b)工程の後、上面、前記上面とは反対側の下面、および前記上面から前記下面までそれぞれ貫通する複数の開口部を有するマスクを、前記第1配線基板の前記表面に配置し、複数の金属粒子を有する金属ペーストを前記マスクの前記複数の開口部のそれぞれの内部に配置する工程;
(d)前記(c)工程の後、前記マスクを除去する工程;
(e)前記(d)工程の後、前記(d)工程により形成された複数の柱状金属ペーストを介して、表面、前記表面とは反対側の裏面、および前記表面に搭載された第2電子部品を有する第2配線基板を、前記第2配線基板の前記裏面が前記第1配線基板の前記表面と対向するように、かつ、前記第2配線基板の前記裏面に形成された複数の電極が前記第1配線基板の前記表面に形成された複数の電極および前記複数の柱状金属ペーストとそれぞれ重なるように、前記第1配線基板の前記表面上に積層する工程;
(f)前記(e)工程の後、前記複数の柱状金属ペーストを加熱することで、前記複数の柱状金属ペーストと前記第1配線基板の前記表面に形成された前記複数の電極および前記第2配線基板の前記裏面に形成された前記複数の電極とを溶着焼結し、複数の金属柱を形成する工程;
(g)前記(f)工程の後、前記第1配線基板と前記第2配線基板との隙間および前記第2配線基板上に封止樹脂を供給し、前記第1電子部品、前記第2電子部品および前記複数の金属柱を封止する工程;
(h)前記(g)工程の後、前記第1配線基板の前記裏面に複数のバンプを接合する工程。 - 前記マスクの前記開口部の前記下面側の開口径は、前記上面側の開口径よりも大きく、
前記(c)工程では、前記マスクの前記下面が前記第1配線基板の前記表面と対向するように、前記第1配線基板の前記表面に配置する請求項1記載の半導体装置の製造方法。 - 前記(g)工程で使用する前記封止樹脂の部材は、ガラスシリカフィラーを含んだエポキシもしくはビフェニールである請求項1記載の半導体装置の製造方法。
- 前記金属粒子は、直径が10nm以下であることを特徴とする請求項1記載の半導体装置の製造方法。
- 前記金属ペーストは、Ag、CuまたはAuを含むことを特徴とする請求項1記載の半導体装置の製造方法。
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009271258A JP5352437B2 (ja) | 2009-11-30 | 2009-11-30 | 半導体装置の製造方法 |
| US12/956,224 US8763242B2 (en) | 2009-11-30 | 2010-11-30 | Semiconductor device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009271258A JP5352437B2 (ja) | 2009-11-30 | 2009-11-30 | 半導体装置の製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2011114259A JP2011114259A (ja) | 2011-06-09 |
| JP2011114259A5 JP2011114259A5 (ja) | 2012-09-27 |
| JP5352437B2 true JP5352437B2 (ja) | 2013-11-27 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2009271258A Expired - Fee Related JP5352437B2 (ja) | 2009-11-30 | 2009-11-30 | 半導体装置の製造方法 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US8763242B2 (ja) |
| JP (1) | JP5352437B2 (ja) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5421863B2 (ja) * | 2010-06-28 | 2014-02-19 | 新光電気工業株式会社 | 半導体パッケージの製造方法 |
| US9131634B2 (en) * | 2011-11-15 | 2015-09-08 | Qualcomm Incorporated | Radio frequency package on package circuit |
| JP5942273B2 (ja) * | 2013-01-29 | 2016-06-29 | パナソニックIpマネジメント株式会社 | 無線モジュール及び無線モジュールの製造方法 |
| US9016552B2 (en) * | 2013-03-15 | 2015-04-28 | Sanmina Corporation | Method for forming interposers and stacked memory devices |
| KR101673259B1 (ko) * | 2015-02-17 | 2016-11-07 | 엘지전자 주식회사 | 반도체 발광 소자를 이용한 디스플레이 장치 |
| US9971970B1 (en) * | 2015-04-27 | 2018-05-15 | Rigetti & Co, Inc. | Microwave integrated quantum circuits with VIAS and methods for making the same |
| EP3376537A4 (en) * | 2015-11-11 | 2019-04-17 | KYOCERA Corporation | PACKAGING FOR AN ELECTRONIC COMPONENT |
| JP2017175000A (ja) * | 2016-03-24 | 2017-09-28 | ローム株式会社 | 電子部品およびその製造方法、ならびに、インターポーザ |
| JP6770331B2 (ja) * | 2016-05-02 | 2020-10-14 | ローム株式会社 | 電子部品およびその製造方法 |
| DE102016110862B4 (de) * | 2016-06-14 | 2022-06-30 | Snaptrack, Inc. | Modul und Verfahren zur Herstellung einer Vielzahl von Modulen |
| US11121301B1 (en) | 2017-06-19 | 2021-09-14 | Rigetti & Co, Inc. | Microwave integrated quantum circuits with cap wafers and their methods of manufacture |
| CN109087909B (zh) * | 2018-08-10 | 2024-08-02 | 浙江熔城半导体有限公司 | 具有金属柱的多腔室封装结构及其制作方法 |
| CN108831881B (zh) * | 2018-08-10 | 2024-08-02 | 浙江熔城半导体有限公司 | 带有腔室的上下堆叠式多芯片封装结构及其制作方法 |
| CN109087912B (zh) * | 2018-08-10 | 2024-07-26 | 浙江熔城半导体有限公司 | 带有腔室的多芯片封装结构及其制作方法 |
| CN108807350B (zh) * | 2018-08-10 | 2024-08-02 | 浙江熔城半导体有限公司 | 放大器芯片电极外设的多腔室封装结构及其制作方法 |
| CN109087911B (zh) * | 2018-08-10 | 2024-08-02 | 浙江熔城半导体有限公司 | 带有容纳功能芯片腔室的多芯片封装结构及其制作方法 |
| KR102703392B1 (ko) * | 2019-11-25 | 2024-09-04 | 현대자동차주식회사 | 전력모듈 및 전력모듈에 적용되는 기판 구조 |
| US11664300B2 (en) * | 2019-12-26 | 2023-05-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fan-out packages and methods of forming the same |
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2009
- 2009-11-30 JP JP2009271258A patent/JP5352437B2/ja not_active Expired - Fee Related
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| Publication number | Publication date |
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| JP2011114259A (ja) | 2011-06-09 |
| US20110128713A1 (en) | 2011-06-02 |
| US8763242B2 (en) | 2014-07-01 |
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