JP6877290B2 - 被処理体を処理する方法 - Google Patents
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
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- Formation Of Insulating Films (AREA)
- Separation By Low-Temperature Treatments (AREA)
- Heating, Cooling, Or Curing Plastics Or The Like In General (AREA)
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Description
条件(i):工程ST1ebにおける犠牲膜EXおよび第2の絶縁膜IS2に対するエッチングの実行時間は、ビア孔VH1の深さ(ビア孔VH1の底面BFからビア孔VH1の開口までのビア孔VH1の側面SFの長さ)を犠牲膜EXのエッチングレートで割って得られる商の値以上である。
条件(ii):犠牲膜EXのエッチングレートと第2の絶縁膜IS2のエッチングレートとは同程度である。
Claims (12)
- 被処理体を処理する方法であって、該被処理体は、配線を有する配線層、該配線層上に設けられた拡散防止膜、該拡散防止膜上に設けられた絶縁膜、該絶縁膜上に設けられ開口を提供する金属マスクを備え、該絶縁膜は、該開口から露出される箇所の一部に設けられたトレンチ、および該トレンチの一部に設けられた第1のビア孔を備え、該方法は、
前記被処理体の前記トレンチと前記第1のビア孔の側面とに犠牲膜を形成する第1の工程と、
前記犠牲膜および前記絶縁膜に対しエッチングを行って、前記第1のビア孔の底面の更に深い位置に第2のビア孔を形成し、該トレンチおよび該第1のビア孔から該犠牲膜を除去する第2の工程と、
を備える方法。 - 第2の工程が完了したとき、前記トレンチの深さは更に深くなり、且つ、前記第1のビア孔はエッチングによって消滅している、
請求項1に記載の方法。 - 前記第1の工程において、前記犠牲膜はコンフォーマルに形成される、
請求項1または請求項2に記載の方法。 - 前記第1の工程は、
ALD(Atomic Layer Deposition)方式を用いて前記トレンチの側面を含む前記被処理体の表面に前記犠牲膜を形成する第3の工程と、
前記被処理体の表面に形成された前記犠牲膜に対しエッチングを行って、前記トレンチの底面を露出させる第4の工程と、
を備える、
請求項1〜3の何れか一項に記載の方法。 - 前記絶縁膜は、シリコン酸化膜、低誘電率の特性を有するシリコン含有膜、または、シリコン酸化膜と低誘電率の特性を有するシリコン含有膜とが積層される膜である、
請求項1〜4の何れか一項に記載の方法。 - 前記犠牲膜は、低誘電率の特性を有する、
請求項1〜5の何れか一項に記載の方法。 - 前記犠牲膜は、シリコン酸化膜である、
請求項1〜6の何れか一項に記載の方法。 - 前記第1の工程から前記第2の工程までは、真空一貫の環境において実行される、
請求項1〜7の何れか一項に記載の方法。 - 前記第1の工程から前記第2の工程までは、単一の処理容器内で実行される、
請求項1〜8の何れか一項に記載の方法。 - 前記絶縁膜の材料が細孔を有する多孔質材である場合に、前記第1の工程は、前記犠牲膜を形成する前に、前記トレンチの表面に露出される該多孔質材の表層に位置する該細孔を封孔する処理を行う、
請求項1〜9の何れか一項に記載の方法。 - 前記ビア孔が前記拡散防止膜に至るまで、前記第1の工程と前記第2の工程とを含むシーケンスを繰り返し実行する、
請求項1〜10の何れか一項に記載の方法。 - 前記第2の工程において行われる前記犠牲膜および前記絶縁膜に対するエッチングの実行時間は前記トレンチの深さを該犠牲膜のエッチングレートで割って得られる商の値以上であり、該犠牲膜のエッチングレートと該絶縁膜のエッチングレートとは同程度である、
請求項1〜11の何れか一項に記載の方法。
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2017150927A JP6877290B2 (ja) | 2017-08-03 | 2017-08-03 | 被処理体を処理する方法 |
| TW107125297A TWI780185B (zh) | 2017-08-03 | 2018-07-23 | 處理被處理體之方法 |
| US16/050,525 US10998223B2 (en) | 2017-08-03 | 2018-07-31 | Method for processing target object |
| KR1020180089802A KR102678853B1 (ko) | 2017-08-03 | 2018-08-01 | 피처리체를 처리하는 방법 |
| CN201810877048.9A CN109390274B (zh) | 2017-08-03 | 2018-08-03 | 对被处理体进行处理的方法 |
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| JP2017150927A JP6877290B2 (ja) | 2017-08-03 | 2017-08-03 | 被処理体を処理する方法 |
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| Publication Number | Publication Date |
|---|---|
| JP2019029619A JP2019029619A (ja) | 2019-02-21 |
| JP6877290B2 true JP6877290B2 (ja) | 2021-05-26 |
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| Country | Link |
|---|---|
| US (1) | US10998223B2 (ja) |
| JP (1) | JP6877290B2 (ja) |
| KR (1) | KR102678853B1 (ja) |
| CN (1) | CN109390274B (ja) |
| TW (1) | TWI780185B (ja) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US10204829B1 (en) * | 2018-01-12 | 2019-02-12 | International Business Machines Corporation | Low-resistivity metallic interconnect structures with self-forming diffusion barrier layers |
| CN109860432B (zh) * | 2018-12-17 | 2021-01-15 | 深圳市华星光电技术有限公司 | 显示器封装结构及其制造方法 |
| US11631589B2 (en) * | 2021-05-04 | 2023-04-18 | Applied Materials, Inc. | Metal etch in high aspect-ratio features |
Family Cites Families (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW411503B (en) * | 1999-07-23 | 2000-11-11 | Taiwan Semiconductor Mfg | Method of forming bottom anti-reflective coating on substrate |
| JP2001358218A (ja) * | 2000-04-13 | 2001-12-26 | Canon Inc | 有機膜のエッチング方法及び素子の製造方法 |
| JP4477750B2 (ja) * | 2000-06-26 | 2010-06-09 | 東京エレクトロン株式会社 | エッチング方法 |
| JP2002373937A (ja) * | 2001-06-15 | 2002-12-26 | Fujitsu Ltd | 半導体装置及びその製造方法 |
| JP3962339B2 (ja) * | 2002-03-27 | 2007-08-22 | 松下電器産業株式会社 | 電子デバイスの製造方法 |
| DE10228807B4 (de) * | 2002-06-27 | 2009-07-23 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung von Mikrostrukturelementen |
| US7701060B2 (en) * | 2003-05-29 | 2010-04-20 | Nec Corporation | Wiring structure and method for manufacturing the same |
| JP4057972B2 (ja) * | 2003-07-25 | 2008-03-05 | 富士通株式会社 | 半導体装置の製造方法 |
| KR100632473B1 (ko) * | 2004-08-03 | 2006-10-09 | 삼성전자주식회사 | 염기성 물질 확산 장벽막을 사용하는 미세 전자 소자의듀얼 다마신 배선의 제조 방법 |
| JP2006156486A (ja) * | 2004-11-25 | 2006-06-15 | Tokyo Electron Ltd | 基板処理方法および半導体装置の製造方法 |
| US7309653B2 (en) * | 2005-02-24 | 2007-12-18 | International Business Machines Corporation | Method of forming damascene filament wires and the structure so formed |
| US7491647B2 (en) * | 2005-03-08 | 2009-02-17 | Lam Research Corporation | Etch with striation control |
| JP4197691B2 (ja) * | 2005-06-21 | 2008-12-17 | 株式会社東芝 | 半導体装置の製造方法 |
| JP2007123766A (ja) | 2005-10-31 | 2007-05-17 | Tokyo Electron Ltd | エッチング方法、プラズマ処理装置及び記憶媒体 |
| CN101667555B (zh) * | 2005-12-07 | 2012-06-27 | 佳能株式会社 | 使用双镶嵌工艺制造半导体器件的方法以及制造具有连通孔的制品的方法 |
| JP4666308B2 (ja) * | 2006-02-24 | 2011-04-06 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
| CN100517606C (zh) * | 2006-12-22 | 2009-07-22 | 中芯国际集成电路制造(上海)有限公司 | 通孔刻蚀方法 |
| US7767578B2 (en) * | 2007-01-11 | 2010-08-03 | United Microelectronics Corp. | Damascene interconnection structure and dual damascene process thereof |
| US7741218B2 (en) * | 2007-02-27 | 2010-06-22 | Freescale Semiconductor, Inc. | Conductive via formation utilizing electroplating |
| JP5342811B2 (ja) * | 2008-06-09 | 2013-11-13 | 東京エレクトロン株式会社 | 半導体装置の製造方法 |
| US8236684B2 (en) * | 2008-06-27 | 2012-08-07 | Applied Materials, Inc. | Prevention and reduction of solvent and solution penetration into porous dielectrics using a thin barrier layer |
| JP5391594B2 (ja) * | 2008-07-02 | 2014-01-15 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
| US8435901B2 (en) * | 2010-06-11 | 2013-05-07 | Tokyo Electron Limited | Method of selectively etching an insulation stack for a metal interconnect |
| US9184054B1 (en) * | 2014-04-25 | 2015-11-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for integrated circuit patterning |
| JP6373150B2 (ja) | 2014-06-16 | 2018-08-15 | 東京エレクトロン株式会社 | 基板処理システム及び基板処理方法 |
| JP2017059750A (ja) * | 2015-09-18 | 2017-03-23 | 東京エレクトロン株式会社 | 被処理体を処理する方法 |
| JP6537473B2 (ja) * | 2015-10-06 | 2019-07-03 | 東京エレクトロン株式会社 | 被処理体を処理する方法 |
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| US20190043753A1 (en) | 2019-02-07 |
| US10998223B2 (en) | 2021-05-04 |
| TW201911415A (zh) | 2019-03-16 |
| KR20190015132A (ko) | 2019-02-13 |
| KR102678853B1 (ko) | 2024-06-26 |
| JP2019029619A (ja) | 2019-02-21 |
| CN109390274B (zh) | 2023-09-05 |
| TWI780185B (zh) | 2022-10-11 |
| CN109390274A (zh) | 2019-02-26 |
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