JP7147570B2 - 半導体積層体および受光素子 - Google Patents
半導体積層体および受光素子 Download PDFInfo
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Description
最初に本願発明の実施態様を列記して説明する。本願の半導体積層体は、InP(インジウムリン)からなる基板と、基板上に配置され、1×1021cm-3未満のSbを含むInPからなる第一バッファ層と、第一バッファ層上に配置され、InGaAs(インジウムガリウム砒素)からなる第二バッファ層と、を備える。第一バッファ層は、基板側の主面である第1主面を含むように配置され、基板よりもSbの濃度が高い第一の層を含む。第二バッファ層は、第一バッファ層側の主面である第2主面を含むように配置され、第一の層よりもSbの濃度が低い第二の層を含む。
含んでいる。そのため、受光層の結晶性を優れたものとすることができる。その結果、受光素子の暗電流を低減することができる。したがって、本願の受光素子によれば、高感度な受光素子を得ることができる。
次に、本発明にかかる半導体積層体の実施の形態を、以下に図面を参照しつつ説明する。なお、以下の図面において同一または相当する部分には同一の参照番号を付しその説明は繰返さない。
図1を参照して、実施の形態1における半導体積層体10は、基板20と、バッファ層30と、受光層40と、ブロック層50と、コンタクト層60とを備えている。
第一の層31Dは、第一バッファ層31全体に形成される他、厚み方向の一部分に形成されるようにしてもよい。図3は、本実施の形態における半導体積層体10の変形例を示す。図3を参照して、第一の層31Dが厚み方向の一部分に形成されている。第一バッファ層31において、第一の層31Dの、基板に面する側とは反対側の主面311上に接触するように、第一の層31DよりもSbの濃度が低い第三の層31Eが配置されている。上述のように第一バッファ層31の表面平坦性を向上させる観点から、基板20に接触する領域にSbの濃度が高い第一の層31Dを配置することが重要である。したがって、第一バッファ層31の全体が第一の層31Dであることは必ずしも必要ではなく、第一の層31Dを基板20に接触する部分に形成する構造を採用した場合でも、表面平坦性に優れた第一バッファ層31を形成することができる。
次に、本発明にかかる半導体装置の他の実施の形態である実施の形態2における受光素子について説明する。図11および図2を参照して、実施の形態2の赤外線受光素子1は、図2に示す構造を単位構造とし、当該単位構造が、基板20の一方の主面20Aに沿う方向に複数繰り返される構造を有している。そして、赤外線受光素子1は、画素に対応する複数のp側電極92を有する。一方、n側電極91は1つだけ配置される。
次に、本願の受光素子の実施の形態3について説明する。実施の形態3の赤外線受光素子1は基本的には実施の形態2の赤外線受光素子1と同様の構造を有し、同様の効果を奏する。しかしながら、実施の形態3においては、赤外線受光素子1の画素に対応する単位構造がトレンチ99により分離される構造に代えて、不純物が拡散されていない領域により分離される構造が採用される点において、実施の形態2の場合とは異なっている。以下、実施の形態2の場合とは異なっている点について主に説明する。
10 半導体積層体
20 基板
20A,31A,32A,40A,50A,60A,83A,311 主面
30 バッファ層
31 第一バッファ層
31B 第1主面
31D 第一の層
32D 第二の層
31E 第三の層
32E 第四の層
32 第二バッファ層
32B 第2主面
40 受光層
41,131 第1要素層
42,132 第2要素層
50 ブロック層
60 コンタクト層
61 拡散領域
62 領域
70 読み出し回路
71 本体
72,73,76,77 バンプ
75 配線
80,85 パッシベーション膜
81,82,84,86 開口部
83 マスク層
91,94 n側電極
92,93 p側電極
98,99 トレンチ
98A,99A 側壁
98B,99B 底壁
100 赤外線センサ
Claims (10)
- InPからなる基板と、
前記基板上に配置され、1×1021cm-3未満のSbを含むInPからなる第一バッファ層と、
前記第一バッファ層上に配置され、InGaAsからなる第二バッファ層と、を備え、
前記第一バッファ層は、前記基板側の主面である第1主面を含むように配置され、前記基板よりもSbの濃度が高い第一の層を含み、
前記第二バッファ層は、前記第一バッファ層側の主面である第2主面を含むように配置され、前記第一の層よりもSbの濃度が低い第二の層を含む、半導体積層体。 - 前記第一の層のSbの濃度は、1×1016cm-3以上である、請求項1に記載の半導体積層体。
- 前記第一の層のSbの濃度は、1×1017cm-3以上である、請求項2に記載の半導体積層体。
- 前記第二の層のSbの濃度は、1×1020cm-3以下である、請求項1に記載の半導体積層体。
- 前記第一バッファ層の厚み方向におけるSbの濃度の分布において、Sbの濃度の最大値と最小値との差の前記最大値に対する割合が、50%以下である、請求項1から請求項4のいずれか1項に記載の半導体積層体。
- 前記第一バッファ層の厚みは、10nm以上50nm以下である、請求項1から請求項5のいずれか1項に記載の半導体積層体。
- 前記第二バッファ層上に配置され、III-V族化合物半導体からなる受光層をさらに備える、請求項1から請求項6のいずれか1項に記載の半導体積層体。
- 前記受光層は、タイプII量子井戸構造である、請求項7に記載の半導体積層体。
- 前記タイプII量子井戸構造は、InxGa1-xAs(xは0.38以上1以下)層とGaAs1-ySby(yは0.36以上1以下)層とのペア、またはGa1-uInuNvAs1-v(uは0.4以上0.8以下、vは0を超え0.2以下)層とGaAs1-ySby(yは0.36以上0.62以下)層とのペアを含む多重量子井戸構造である、請求項8に記載の半導体積層体。
- 請求項1から請求項9のいずれか1項に記載の半導体積層体と、
前記半導体積層体上に形成された電極と、を備える、受光素子。
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100258894A1 (en) | 2009-04-08 | 2010-10-14 | Sumitomo Electric Industries, Ltd. | Photodiode array and image pickup device using the same |
| JP2011060853A (ja) | 2009-09-07 | 2011-03-24 | Sumitomo Electric Ind Ltd | Iii−v族化合物半導体受光素子、及びiii−v族化合物半導体受光素子を作製する方法 |
| JP2011100770A (ja) | 2009-11-04 | 2011-05-19 | Sumitomo Electric Ind Ltd | 受光素子アレイの製造方法及び受光素子アレイ、並びにエピタキシャルウェハの製造方法及びエピタキシャルウェハ |
| JP2015082573A (ja) | 2013-10-22 | 2015-04-27 | 住友電気工業株式会社 | エピタキシャルウエハおよびその製造方法 |
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| JP2011100770A (ja) | 2009-11-04 | 2011-05-19 | Sumitomo Electric Ind Ltd | 受光素子アレイの製造方法及び受光素子アレイ、並びにエピタキシャルウェハの製造方法及びエピタキシャルウェハ |
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