JP7389037B2 - 時間同期装置、電子機器、時間同期システム及び時間同期方法 - Google Patents

時間同期装置、電子機器、時間同期システム及び時間同期方法 Download PDF

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JP7389037B2
JP7389037B2 JP2020536774A JP2020536774A JP7389037B2 JP 7389037 B2 JP7389037 B2 JP 7389037B2 JP 2020536774 A JP2020536774 A JP 2020536774A JP 2020536774 A JP2020536774 A JP 2020536774A JP 7389037 B2 JP7389037 B2 JP 7389037B2
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frequency
time
output
signal
circuit
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JP2021526320A (ja
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シィアンイェ ウェイ
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BOE Technology Group Co Ltd
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    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/14Time supervision arrangements, e.g. real time clock
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12Synchronisation of different clock signals provided by a plurality of clock generators
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/02Details
    • H04J3/06Synchronising arrangements
    • H04J3/0635Clock or time synchronisation in a network
    • H04J3/0638Clock or time synchronisation among nodes; Internode synchronisation
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01Shaping pulses
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L1/00Stabilisation of generator output against variations of physical values, e.g. power supply
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L1/00Stabilisation of generator output against variations of physical values, e.g. power supply
    • H03L1/02Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only
    • H03L1/022Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only by indirect stabilisation, i.e. by generating an electrical correction signal which is a function of the temperature
    • H03L1/027Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only by indirect stabilisation, i.e. by generating an electrical correction signal which is a function of the temperature by using frequency conversion means which is variable with temperature, e.g. mixer, frequency divider, pulse add/subtract logic circuit
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/099Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/099Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • H03L7/0996Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/02Details
    • H04J3/06Synchronising arrangements
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/027Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/02Details
    • H04J3/06Synchronising arrangements
    • H04J3/0635Clock or time synchronisation in a network
    • H04J3/0638Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658Clock or time synchronisation among packet nodes
    • H04J3/0661Clock or time synchronisation among packet nodes using timestamps
    • H04J3/0667Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Electric Clocks (AREA)
JP2020536774A 2018-06-11 2019-04-16 時間同期装置、電子機器、時間同期システム及び時間同期方法 Active JP7389037B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CN201810596413.9 2018-06-11
CN201810596413.9A CN110581743B (zh) 2018-06-11 2018-06-11 电子设备、时间同步系统及时间同步方法
PCT/CN2019/082926 WO2019237825A1 (fr) 2018-06-11 2019-04-16 Dispositif de synchronisation temporelle, dispositif électronique, système de synchronisation temporelle et procédé de synchronisation temporelle

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JP2021526320A JP2021526320A (ja) 2021-09-30
JP7389037B2 true JP7389037B2 (ja) 2023-11-29

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US (1) US11429137B2 (fr)
EP (1) EP3806355B1 (fr)
JP (1) JP7389037B2 (fr)
KR (1) KR102391323B1 (fr)
CN (1) CN110581743B (fr)
AU (1) AU2019285968B2 (fr)
BR (1) BR112020013384A2 (fr)
MX (1) MX2020006929A (fr)
RU (1) RU2758838C1 (fr)
WO (1) WO2019237825A1 (fr)

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WO2020213190A1 (fr) * 2019-04-19 2020-10-22 三菱電機株式会社 Système de communication, dispositif maître, dispositif esclave et dispositif intermédiaire
JP7493581B2 (ja) 2020-01-19 2024-05-31 京東方科技集團股▲ふん▼有限公司 時刻同期方法及び装置、ネットワークノード機器
CN111446962B (zh) * 2020-04-03 2023-12-12 京东方科技集团股份有限公司 时钟信号产生电路、时钟信号产生方法及电子设备
KR102400761B1 (ko) 2020-11-10 2022-05-23 주식회사 스카이칩스 저전력 주파수 합성 장치
US12470531B2 (en) * 2020-12-24 2025-11-11 Beijing Boe Technology Development Co., Ltd. Interactive authentication method, system, computer device, and non-volatile readable storage medium
CN113391333B (zh) * 2021-06-15 2023-10-03 郑州轻大产业技术研究院有限公司 一种基于异频群量子化相位处理的北斗高精度时间同步芯片
CN113641213B (zh) * 2021-07-29 2023-04-25 中国人民解放军战略支援部队信息工程大学 一种基于els帧的时间同步装置与方法
US11764834B2 (en) 2022-02-15 2023-09-19 Raytheon Company Device for and method of synchronizing multiple beamforming devices
CN114785442B (zh) * 2022-04-26 2026-04-07 上海博联智电科技有限公司 一种Modbus主从设备的同步控制方法、设备及存储介质
CN117221175B (zh) * 2022-06-02 2025-11-11 中兴通讯股份有限公司 时延测量方法及其装置、存储介质、程序产品
US11990982B2 (en) * 2022-06-02 2024-05-21 Qualcomm Incorporated Signaling model parameters that indicate a time correction and/or a frequency correction for an uplink transmission
CN115966162B (zh) * 2022-12-30 2026-03-31 裕太微电子股份有限公司 一种拼接屏中的phy间干扰消除方法
CN117155507A (zh) * 2023-09-01 2023-12-01 广州市迪士普音响科技有限公司 一种时钟同步系统及方法

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JP2015082815A (ja) 2013-10-24 2015-04-27 日本電波工業株式会社 発振器
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Publication number Publication date
CN110581743B (zh) 2021-01-22
AU2019285968A1 (en) 2020-06-25
CN110581743A (zh) 2019-12-17
KR20200093012A (ko) 2020-08-04
BR112020013384A2 (pt) 2020-12-01
US20210356985A1 (en) 2021-11-18
RU2758838C1 (ru) 2021-11-02
KR102391323B1 (ko) 2022-04-28
WO2019237825A1 (fr) 2019-12-19
AU2019285968B2 (en) 2021-06-10
US11429137B2 (en) 2022-08-30
EP3806355A1 (fr) 2021-04-14
EP3806355B1 (fr) 2025-02-12
EP3806355A4 (fr) 2022-03-02
JP2021526320A (ja) 2021-09-30
MX2020006929A (es) 2020-09-09

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