JPH01100202U - - Google Patents
Info
- Publication number
- JPH01100202U JPH01100202U JP19481987U JP19481987U JPH01100202U JP H01100202 U JPH01100202 U JP H01100202U JP 19481987 U JP19481987 U JP 19481987U JP 19481987 U JP19481987 U JP 19481987U JP H01100202 U JPH01100202 U JP H01100202U
- Authority
- JP
- Japan
- Prior art keywords
- input
- gate
- output
- external
- interface circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000008878 coupling Effects 0.000 claims 2
- 238000010168 coupling process Methods 0.000 claims 2
- 238000005859 coupling reaction Methods 0.000 claims 2
- 230000003287 optical effect Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 9
- 238000000034 method Methods 0.000 description 1
Landscapes
- Programmable Controllers (AREA)
Description
第１図は本考案の一実施例を示すＰＣのブロツ
ク図、第２図および第３図は第１図に示した入出
力インターフエース回路の詳細を示す回路図、第
４図は実施例における入／出力設定処理および入
／出力データ更新処理を示すフローチヤート、第
５図および第６図はそれぞれ本考案における入／
出力設定処理の他の実施例を示す説明図、第７図
は一般的なＰＣの構成を示すブロツク図、第８図
は従来の入力モジユールのブロツク図、第９図は
従来の出力モジユールのブロツク図、第１０図は
従来の入力インターフエース回路の回路図、第１
１図は従来の出力インターフエース回路の回路図
である。
１……ＰＣの基本ユニツト、２……ＰＣの増設
ユニツト、３……ＣＰＵ、３Ａ……ＲＡＭ、４…
…システムプログラムメモリ、５……ユーザープ
ログラムメモリ、６……データメモリ、７……増
設カード、８……電源回路、９……入／出力モジ
ユール、１０……増設ケーブル、１１……内部バ
ス、２１……入力インターフエース回路、２２…
…入力ゲート群、３１……出力インターフエース
回路、３２……フリツプフロツプ回路、３３……
出力ゲート群、４１……入出力インターフエース
回路、５１……スイツチ群、５２……入力ゲート
群、２１１，３１１……フオトカプラ、２１８，
３１６……フオトトライアツク、２１９，３１７
……ＡＣ電源、２１７，３１５……ＤＣ電源。
Fig. 1 is a block diagram of a PC showing an embodiment of the present invention, Figs. 2 and 3 are circuit diagrams showing details of the input/output interface circuit shown in Fig. 1, and Fig. 4 is a block diagram of a PC showing an embodiment of the present invention. Flowcharts illustrating input/output setting processing and input/output data updating processing, FIGS.
An explanatory diagram showing another embodiment of the output setting process, FIG. 7 is a block diagram showing the configuration of a general PC, FIG. 8 is a block diagram of a conventional input module, and FIG. 9 is a block diagram of a conventional output module. Figure 10 is a circuit diagram of a conventional input interface circuit.
FIG. 1 is a circuit diagram of a conventional output interface circuit. 1...Basic unit of PC, 2...Expansion unit of PC, 3...CPU, 3A...RAM, 4...
...System program memory, 5... User program memory, 6... Data memory, 7... Extension card, 8... Power supply circuit, 9... Input/output module, 10... Extension cable, 11... Internal bus, 21...Input interface circuit, 22...
...Input gate group, 31...Output interface circuit, 32...Flip-flop circuit, 33...
Output gate group, 41... Input/output interface circuit, 51... Switch group, 52... Input gate group, 211, 311... Photocoupler, 218,
316...Photo trial, 219,317
...AC power supply, 217,315...DC power supply.
Claims (1)
結合素子における受光素子とを直列に連結するこ
とによつて構成され、外部入力機器および外部出
力機器のいずれをも接続可能な入出力インターフ
エース回路と、 前記入出力インターフエース回路からの、また
は前記入出力インターフエース回路への信号経路
を開閉するゲートと、 前記入出力インターフエース回路を、前記外部
入力機器からの信号入力あるいは前記外部出力機
器への信号出力のいずれに用いるかの設定を行う
入／出力設定手段と、 該入／出力設定手段の設定に基づいて前記ゲー
トの開閉を制御するゲート制御手段と を具えたことを特徴とするプログラマブルコン
トローラ。[Claims for Utility Model Registration] It is constructed by connecting the light emitting element in one optical coupling element and the light receiving element in the other optical coupling element in series, and can be connected to both external input equipment and external output equipment. a gate that opens and closes a signal path from or to the input/output interface circuit; and a gate that connects the input/output interface circuit to a signal from the external input device. An input/output setting means for setting whether to use the gate for input or outputting a signal to the external output device, and a gate control means for controlling opening/closing of the gate based on the settings of the input/output setting means. A programmable controller characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19481987U JPH01100202U (en) | 1987-12-24 | 1987-12-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19481987U JPH01100202U (en) | 1987-12-24 | 1987-12-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01100202U true JPH01100202U (en) | 1989-07-05 |
Family
ID=31485527
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19481987U Pending JPH01100202U (en) | 1987-12-24 | 1987-12-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01100202U (en) |
-
1987
- 1987-12-24 JP JP19481987U patent/JPH01100202U/ja active Pending
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