JPH0110040Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to a signal processing circuit for removing large amplitude unnecessary signals.

[Technical background of the invention]

Conventionally, for example, in a signal processing circuit configured as shown in Figure 1, multiple analog signal input AI
is supplied to the bandpass filter BF, which is converted into a time-divided serial signal by the switch S1.

This band filter BF extracts only a predetermined signal and then compares it with a predetermined reference value by a level determiner LD, and pulse trains exceeding the reference value are supplied to a counter C1.

The counter C1 counts the input pulse train according to the gate signal synchronized with the time division signal of the switch S1, and supplies the counting result to the comparator CO. The comparator CO that receives this counting result is a reference number generator.
A determination is made based on the magnitude of the number of times compared to a predetermined reference number generated from the RE, and an output O1 of the processing result is sent out.

The above is an explanation of Fig. 1. Here, we will use a "predetermined signal" as an analog input as shown in Fig. 2 a, and an "unnecessary signal" as shown in Fig. 2 d.
Consider the case where is supplied. First, since the "predetermined signal" has a frequency within the pass band of the band filter BF, a signal as shown in FIG. 2b corresponding to the input is obtained as the band filter output.

The output signal of the band filter BF is level judged by the level judger 4, and a pulse train as shown in FIG. CO is supplied to the vessel.

The comparator CO compares the counting result with a predetermined reference number, and outputs an output O1 as a processing result indicating that a "predetermined signal" is present. In this way, for the "predetermined signal", it operates normally as described above.

Next, the large-amplitude "unnecessary signal" shown in Figure 2 d causes a ringing response of the band filter due to the transient response of the band filter BF, and a signal as shown in Figure 2 e appears as the band filter output. . In FIG. 2e, L1 is a level determination threshold level.

The level of the "unnecessary signal" obtained by this ringing response is determined by the level determiner LD, and a pulse train as shown in FIG. 2f is supplied to the counter C1.

[Problems with background technology]

Since the counter C1 counts only the number of pulses, it supplies the counting result to the comparator as the same number of pulses as the "predetermined signal" despite the discontinuity of the pulse train.

The comparator CO misidentifies the "unnecessary signal" as the predetermined signal and sends out an output because the count result is comparable to that of the predetermined signal.

In this way, the bandpass filter BF responds with a ringing response due to a large-amplitude transient signal.
There was a drawback that even "unnecessary signals" were regarded as predetermined signals and the processing results were sent out.

[Purpose of invention]

This invention was made in order to eliminate the above-mentioned conventional drawbacks, and the purpose is to provide a signal processing circuit that prevents the transmission of erroneously recognized processing results for transient large-amplitude "unnecessary signals." do.

[Summary of the idea]

The signal processing circuit of this invention switches multiple analog signal inputs using a switch, extracts a signal in a predetermined frequency band using a band filter, and then uses a level judge to judge the level of the output signal of the band filter. The gate switch is activated in response to the gate input synchronized with the divided signal, the pulse train of the output of the level judge is counted by a counter, and the result of this counting is compared with a predetermined reference number comparator to calculate the number from the reference number. It is designed to output when the value is large.

[Example of idea]

Embodiments of the signal processing circuit of this invention will be described below with reference to the drawings. FIG. 3 is a block diagram showing the configuration of one embodiment. In FIG. 3, in order to avoid duplication, the same parts as in FIG. 1 will be given the same reference numerals and their explanation will be omitted, and the parts different from FIG. 1 will be mainly described.

As is clear from comparing Fig. 3 with Fig. 1, in Fig. 3 the gate switch GS is inserted between the level determiner LD and the counter C1, which is different from Fig. 1. This is different and is a characteristic feature of this invention. That is, the gate input GI with a predetermined period and time width is input to the gate switch GS, and this gate input GI is input to the counter C1 as a reset signal. It's summery. The other configurations are the same as in FIG. 1.

Next, the operation of the signal processing circuit of this invention constructed as described above will be explained. In Figure 3, the "predetermined signal" up to the output of the level judger LD
and the responses corresponding to "unnecessary signals" operate in the same manner as described in the prior art section.

That is, the "predetermined signal" (Figure 4a) and the "unnecessary signal" (Figure 4e) output from the level determiner LD have the pulse train states shown in Figures 4a and 4e. It exists as such.

Here, focusing on the continuity of both signals, the "predetermined signal" shown in Figure 4a is a continuous pulse train, whereas the "unnecessary signal" shown in Figure 4e is a discontinuous pulse train. It is becoming. As a means of determining this continuity, a gate input GI synchronized with a time-division signal as shown in FIGS. 4b to 4d is applied to the "predetermined signal" shown in FIG. 4a.
1 to GI3 are added to the gate switch GS.

In addition, for "unnecessary signals" as shown in Fig. 4e, gate inputs GI4 to GI6 synchronized with the time-sharing signals shown in Fig. 4f to Fig. 4h are input to the gate switch GS. be done.

As a result, the gate of the gate switch GS opens in response to gate inputs GI1 to GI3, and the pulse train of the "predetermined signal" shown in FIG. It is input to C1.

Similarly, a pulse train of "unnecessary signals" as shown in FIG. 4e is input to the counter C1 in correspondence with gate inputs GI4 to GI6 shown in FIGS. 4f to 4h.

Of the pulse train input to this counter C1,
In the pulse train corresponding to the "predetermined signal" shown in FIG. 4a, the gate input GI1 in FIG.
, 2 at gate input GI2 in Figure 4c, and 2 at gate input GI3 in Figure 4c are each counter C.
1 is input.

On the other hand, in the pulse train corresponding to the "unnecessary signal" shown in FIG. 4e, there are three pulses at gate input GI4 in FIG. 4f and three pulses at gate input GI5 in FIG. 4g.
, zero is input to the counter C1, and three are input to the counter C1 at the gate input GI6 in FIG. 4h.

The count output of this counter C1 is sent to the comparator CO, where it is compared with the reference number generated from the reference number generator RE. As a result of this comparison, if the count value is greater than the reference value, it is output as output O1. be done. This makes it possible to prevent false recognition transmission due to "unnecessary signals." In the example of FIG. 4, the count result of "unnecessary signals" for the gate input GI5 shown in FIG. 4g becomes zero, thereby preventing erroneous recognition and transmission.

Note that, after outputting the count value, the counter C1 is reset at the falling edge of the gate signal. Then, each gate input GI1 to GI3 and GI4 to GI6 are sequentially switched.

[Effect of idea]

As described above, according to the signal processing circuit of this invention, after switching a plurality of analog signal inputs with a switch and extracting a signal in a predetermined frequency band with a band filter, the output signal of the band filter is extracted with a level judger. The level is determined, the gate switch is operated in response to the gate input synchronized with the time division signal, the pulse train of the output of the level determination device is counted by a counter, and the result of this counter is set as a predetermined reference number. Since the comparison is made using a comparator and the signal is output when the number is larger than the reference number, it is possible to prevent erroneously recognizing and transmitting an "unnecessary signal" with a large transient amplitude.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional signal processing circuit, Fig. 2 is a waveform diagram for explaining the operation of the first signal processing circuit, and Fig. 3 shows the configuration of an embodiment of the signal processing circuit of this invention. The block diagram shown in FIG. 4 is a waveform diagram for explaining the operation of the signal processing circuit of FIG. 3. S1...Switcher, BF...Band filter, LD...
...Level judge, GS...Gate switch, C1...
…Counter, CO…Comparator, RE…Reference number generator.

Claims (1)

[Scope of utility model registration request] A switch that switches between multiple analog signal inputs, a band filter that selects the analog signal switched by this switch, a level judge that judges the level of the output of this band filter, and a pulse with a predetermined period and time width. a gate switch that is switched by the gate input and passes the pulse train output from the level determiner; a counter that counts the number of pulses of the pulse train that has passed through the gate switch each time the gate input is switched; A signal processing circuit comprising a comparator that compares the output of the counter with a reference number and outputs a signal when the output of the counter is greater than the reference number.