JPH01101420A - Optical sensor circuit - Google Patents

Abstract

PURPOSE:To easily adjust the detection sensitivity of light by obtaining a voltage corresponding to the difference between a 2nd reference voltage and a voltage obtained relatively to light irradiation as an output voltage. CONSTITUTION:While a clock signal phi is at H level, a 1st reference voltage V1 is biased reversely to a photodiode 3 to charge the depletion layer capacity of the diode 3. Then when the clock signal phi falls to L level, only a transmission gate 4 turns on and the voltage of a coupling capacitor 8 on the side of an impedance converting circuit 11 is varied from the output voltage of the circuit 11 which inputs the 2nd reference voltage V2 to a voltage V1' generated by outputting the voltage V1' applied to said depletion layer capacity of the diode 3 through the circuit 11. Consequently, the difference voltage between the reference voltage V2 and voltage V1' is amplified by an inverter 5.

Description

[Detailed description of the invention]

[Industrial Field of Application] The present invention relates to an optical sensor circuit, and more particularly to an optical sensor circuit capable of controlling the high and low thresholds of the output signals of No.7.

[Conventional technology]

FIG. 3 is a (b) schematic diagram showing an example of a conventional optical sensor circuit. In the figure, l is a reference voltage input terminal to which a reference voltage v1 is applied. This reference voltage input 1m F 1
is connected to the cathode terminal of a photodiode 30 via a transmission gate (hereinafter referred to as TG) 2 composed of an N-channel A/11108 transistor, and the anode terminal of the photodiode 3 is grounded. Also,
The lower end t of the photodiode 3 is N-channel A/M.
It is connected to the input terminal of the inverter circuit 5 via Te3 formed of an O8 transistor and to one side of Te3 formed by an N-channel lvMO8) fungistor. and,
The other side of Te3 is grounded, and the output side of the inverter circuit 5 is connected to the output terminal 7. 21 and 41.61 are respectively Te2. Te3. The gate terminal 21.61 of Te3 is supplied with a clock signal -, and the other gate terminal t41 is supplied with a clock signal 91 that is set so as not to overlap with the clock signal -. As a result, Te2. On/off of Te3 is controlled by clock signal 9, while Te3 is controlled by clock signal 9.
- controls the on/off of Y:″%TG2.T
G6 and Te3 are turned on and off in a complementary manner. These Te2. Te3゜Te3 and photodiode 3
c. An input control circuit that controls the input voltage to the inverter circuit 5 is configured. The operation of this optical sensor circuit will be explained next. Now, the reference voltage v1 is applied to the reference voltage input terminal 1, and each TG2,
It is assumed that the above clock signal -2- is applied to the gate terminals "P21 and 41.6IC= of 4.6, respectively. First, the darkness where the clock signal 9- is at the rHJ level ~ is T
e2. '['G6 turns on, and lock signal @
Since the level μ reaches 7arLJ, Te3 is turned off. As a result, a reverse bias voltage based on the reference voltage vl is applied to the photodiode 3, and a charge is added to the depletion layer capacitance of the photodiode 3 't11k. At this time, if the photodiode 3 is not irradiated with light, the reference voltage vl will remain 7 and will be applied to the depletion layer capacitance, but if the photodiode 3 (binary) is irradiated, the photodiode A photocurrent flows through the photodiodes 3 and the voltage applied to the depletion layer capacitance becomes smaller than the reference voltage vl.Thus, while the photodiode 3 & 2 reference voltage Vl is reverse biased, the inverter circuit 5 receives an input voltage of 7. ,Te
A ground potential rLJ level is applied through the inverter circuit 3, so that the output voltage of the inverter circuit 5 becomes rHJ level. Next ζ2, when the clock signal - becomes "L" level, '1
1'G2 and 6 are in the off state and Te3 is in the on state, and the voltage applied to the depletion layer capacitance 62 in the photodiode 3 is applied to the input terminal of the inverter circuit 50 via Te3. At this time, if the photodiode 3 is not irradiated with light, the reference voltage v
Since l is still applied at 7, this reference voltage vl is applied to the input terminal C of the inverter circuit 50, and the output voltage of the inverter circuit 5 becomes rLJ level. On the other hand, when the photodiode 3 is irradiated with light, as shown above, 1: Since a voltage smaller than the reference voltage v1 is applied to the depletion layer capacitance, this voltage is applied to the inverter circuit 5.
The output voltage of the inverter circuit 5 does not fall to the rLJ level, but reaches the rHJ level A'.
I was left stunned. Therefore, the presence or absence of light irradiation can be detected based on the output voltage of the inverter circuit 5, in other words, the output voltage applied to the output terminal 74. That is, output terminal 7
When the g2rHJ level signal is output continuously, it can be determined that there is light irradiation, and conversely, when the rHJ level and rLJ level are output repeatedly, it can be determined that there is no light irradiation. . [Problem to be solved by the invention J] However, in the conventional optical sensor circuit as described above, when the intensity of the light irradiated to the photodiode 3 is weak, the voltage applied to the depletion layer capacitance of the photodiode 3 becomes lower than the reference voltage. V,
Since the voltage does not decrease sufficiently compared to , and the voltage remains at 7 and is applied to the inverter circuit 5 at the rHJ level, light is irradiated. The level is broken and it is determined that there is no light irradiation. In addition, the charge stored in the photodiode 3 is redistributed between the large combined capacitance of the parasitic capacitances of the inverter 5 and Te3.6 and the capacitance of the photodiode 3's own descendants, so that the input feeling of the inverter 5 = The voltage becomes smaller. That is, conventional optical sensor circuits have a problem in that they cannot detect light with low intensity and can only detect light with an intensity above a certain level. The present invention has been made to solve these problems, and it is an object of the present invention to provide a light sensor circuit that can adjust the light detection sensitivity and detect even low-intensity light. [Means for Solving Problems J] The optical sensor circuit of the present invention has a capacitance q whose capacitance at the time of reverse bias changes depending on the light irradiation. In order to achieve the above object, the first voltage obtained from C.62 and a predetermined second voltage are alternately input to the impedance conversion circuit. Set a reference voltage, insert a 5-capacitor between the output side of the impedance conversion circuit and the input terminal of the inverter circuit,
Another switch means is connected between the input and output terminals of the inverter circuit, and is conductive only during the period when the second reference voltage is output from the switch means. [Operation] According to the present invention, when the second reference voltage is applied to the capacitor via the impedance conversion circuit, the switch means is simultaneously turned on and a bias is applied to the inverter circuit to increase its gain. Then, when a first voltage having a voltage value related to light irradiation is applied to the capacitor instead of the second reference voltage through the impedance conversion circuit, the first voltage and the second reference voltage are By rounding, the difference between the above-mentioned gain is amplified by the multiplier inverter circuit, and by appropriately changing the voltage value of the second reference voltage, the threshold value at which the output voltage o1-HJrLJ level of the optical sensor circuit changes is determined. can be adjusted. [Embodiment] FIG. 1 is a circuit diagram showing an optical sensor circuit according to an embodiment of the present invention. In the figure, a coupling capacitor 8 is connected to the output part between the θ output side of the part consisting of Te2,4°6 and the photodiode 3 and the input end of the inverter circuit 5, and a nine impedance conversion circuit 11 is inserted. In addition, an N-channel l is connected between the input and output terminals of the inverter circuit 50.
'Te3 composed of a ViOB transistor is connected, and the second reference voltage input terminal LO to which the reference voltage V of @2 is applied is connected to the side of Te3. 91- is T2
A clock signal - is applied to this gate terminal 91 to control on/off of Te3. Since the other configuration of 7 is the same as that of the conventional example, the same parts 4, 2, and 9 will be given the same reference numerals, and the explanation thereof will be omitted. Next, two operations of this optical sensor circuit will be explained. Now, the reference voltage input terminals 1 and 10 have a reference voltage Vl. It is assumed that clock signal -1- is applied to each of Te2, 4, and 6.9j, and clock signal -1- is applied to each of Te2, 4, and 6.9j. The operation of the sensor circuit is almost the same as that of the conventional optical sensor circuit, but the following points are achieved. That is, while the clock signal - is at "H" level /L/, the reference voltage V of III is maintained through Te2 which is in the on state.
1 is reverse biased and the depletion layer capacitance of the photodiode 3 is charged. At this time, since Te3 is also in the on state, the voltage on the impedance conversion circuit 11 side of the coupling capacitor 8 is When the second reference voltage v2 is input, the output voltage is 9 impedance conversion circuits 1%11. Also, since Te3 is also in the on state, the input and output terminals of the inverter circuit 5 are conductive, and the coupling capacitor 8 The voltage on the inverter circuit 5 side is adjusted to a value that makes the input voltage and output voltage of the inverter circuit 5 equal.
The figure shows an example of a relational characteristic diagram between the input voltage and the output voltage of the inverter circuit 5. In this example, the voltage at point b where the input voltage and the output voltage are equal is applied to the inverter circuit 5 side of the coupling capacitor 8. . In other words, the inverter circuit 5 is biased to point b where the gain is high. Next, when the clock signal becomes rLJt/befi/,
Te2 and 6.9 are in the off state and only Te3 is in the on state, and the impedance conversion of the coupling capacitor 8 @
The voltage on the side of path 11 is the voltage V, l applied to the depletion layer capacitance of photodiode 3 from the output voltage of impedance conversion circuit 11 with reference voltage V2 of $2 as input, which is the voltage output through impedance conversion circuit 11. It changes to vl'. This ζ: Therefore, the voltage difference between the second reference voltage v2 and the depletion layer capacitance of the photodiode 3, voltage v11, acts on the inverter circuit 5 (2) through the inverter impedance conversion circuit. The differential voltage is amplified by the inverter circuit 542, which is biased at the point ζ2 with a high gain.As explained in the conventional example, the voltage vlI is the reference voltage when the photodiode 3 is not irradiated with light. The voltage VI (equal to 2, becomes lower than the reference voltage Vl as the light irradiation increases. In this way, the second reference voltage v2 and the photodiode 3
Since the voltage difference between the voltage vl' and the voltage vl' existing in the depletion layer capacitance of The output voltage of the optical sensor circuit can be freely adjusted by adjusting the difference voltage between the reference voltage v2 and the voltages V and l. In other words, the output voltage applied to the output terminal F 7 gml in relation to the voltage across the terminals of the photodiode 3 can be adjusted by the second reference voltage V2 (2), and thus the output of the photosensor circuit can be adjusted according to the characteristics of the photodiode 3. It is possible to adjust the threshold value for switching between the "H" and "L" levels of the voltage. By adjusting this threshold value, the light detection sensitivity of the optical sensor circuit can be controlled, and light detection is possible even for weak-intensity light ζ2. cvff
! , becomes. In the above embodiment, TGs 2, 4, and 6.9 are all constructed of N channel #MO8) Funji Nuta, but T
G may be composed of a P-channel lvMO8 transistor, or of course may be composed of a 0MO8) range nut including an N-channel and a P-channel. In that case, it is necessary to select the clock signal -1- given to each gate terminal so that each TG performs the same operation as in the above embodiment. Further, in the above embodiment (2), the first reference voltage V. It is sufficient to use a variable capacitance element whose capacitance is variable according to light irradiation (2). [Effects of the Invention] As described above, according to the optical sensor circuit of the present invention, the second
Since nine voltages are obtained as the output voltage according to the difference between the reference voltage of
It is possible to adjust the threshold value at which the Pel changes, or in other words, to adjust the light ejection sensitivity, so that even low-intensity light can be detected with Iv capability. Furthermore, the charge stored in the photodiode 3 does not have to be redistributed to a large capacitor such as the gate capacitance of the 5-in-parter as in the conventional example, so that the ejection sensitivity is improved.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an optical sensor circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing input/output characteristics of an inverter circuit, and FIG. 3 is a circuit diagram of a conventional optical sensor circuit. In the figure (=, 1.10 is the reference voltage input terminal, 2゜4.6
．． 9 is a transmission VH unit, 3 is a photodiode, 5 is a photosensor circuit, 7 is an output terminal, 8 is a coupling capacitor, 11 is an impedance conversion circuit, 21,
41, 61.91 are gate terminals, V is a first reference voltage, v2 is a second reference voltage, and -9- is a clock signal. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (2)

[Claims] (1) The anode terminal of the variable capacitance element whose capacitance during reverse bias changes according to light irradiation is grounded, the cathode terminal is connected to the first switching means, and the first reference voltage is applied to the input side terminal. The output side terminal is connected to the output side terminal of the first switch means, and the output side terminal is connected to the input terminal of the impedance conversion buffer circuit, and is turned on and off in a complementary manner to the first switch means. A second reference voltage is applied to the input terminal of the impedance conversion circuit via a third switch means that turns on and off complementary to the second switch means. , and the output terminal of the impedance conversion circuit is connected via a coupling capacitance to the input terminal of an inverter circuit connected by a fourth switch means that turns the output terminal on and off in the same phase as the third switch means. optical sensor circuit. (2) The variable capacitance element is composed of a photodiode, and the switch means is controlled by a clock signal.
The optical sensor circuit according to claim 1, comprising an OS transistor.