JPH01102780U - - Google Patents
Info
- Publication number
- JPH01102780U JPH01102780U JP19582987U JP19582987U JPH01102780U JP H01102780 U JPH01102780 U JP H01102780U JP 19582987 U JP19582987 U JP 19582987U JP 19582987 U JP19582987 U JP 19582987U JP H01102780 U JPH01102780 U JP H01102780U
- Authority
- JP
- Japan
- Prior art keywords
- socket
- stage
- external connection
- pins
- board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000523 sample Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Connecting Device With Holders (AREA)
Description
第１図は、本考案の一実施例の２段ソケツトの
正面、上面、及び側面図、第２図は、本考案の一
実施例を説明するための基板と被試験ｉＣと本考
案に係る２段ソケツトとｉＣソケツト、及びオシ
ロスコープのプローブの関係を示す正面図である
。
符号の説明、１…ｉＣ、２…ｉＣピン差込口、
３…２段目のｉＣソケツト、４…外部接続用ピン
、５…１段目のｉＣソケツト、６…足ピン、７…
受ピン、８…ｉＣソケツト、９…基板、１０…オ
シロスコープのプローブ。
FIG. 1 is a front, top, and side view of a two-stage socket according to an embodiment of the present invention, and FIG. 2 is a diagram showing a board, an IC to be tested, and an IC to be tested according to an embodiment of the present invention. FIG. 3 is a front view showing the relationship between a two-stage socket, an iC socket, and an oscilloscope probe. Explanation of symbols, 1...iC, 2...iC pin insertion port,
3...2nd tier iC socket, 4...external connection pin, 5...1st tier iC socket, 6...leg pin, 7...
Receiving pin, 8...iC socket, 9...board, 10...oscilloscope probe.
Claims (1)
装置において、ｉＣソケツトを２段にし、１段目
のｉＣソケツトと２段目のｉＣソケツト間をそれ
ぞれ複数個の外部接続用ピンで接続し、２段目の
ｉＣソケツトの受ピンにｉＣを差込み１段目のｉ
Ｃソケツトの足ピンを上記基板上のｉＣソケツト
の受ピンに差込むことにより、外部接続用ピンか
ら容易に信号を取出すことができ、又、外部接続
用ピンによる回路を切断することにより信号をオ
ープンにすることを可能にして上記基板の回路試
験ができるようにしたことを特徴とする２段ソケ
ツト。 In a device in which an iC is mounted on a board via an iC socket, the iC socket is arranged in two stages, and the first stage iC socket and the second stage iC socket are each connected with a plurality of external connection pins. Insert the iC into the receiving pin of the iC socket of the first stage.
By inserting the leg pins of the C socket into the receiving pins of the iC socket on the above board, signals can be easily taken out from the external connection pins, and signals can also be taken out by disconnecting the circuit caused by the external connection pins. A two-stage socket characterized in that it can be opened to enable circuit testing of the board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19582987U JPH01102780U (en) | 1987-12-25 | 1987-12-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19582987U JPH01102780U (en) | 1987-12-25 | 1987-12-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01102780U true JPH01102780U (en) | 1989-07-11 |
Family
ID=31486485
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19582987U Pending JPH01102780U (en) | 1987-12-25 | 1987-12-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01102780U (en) |
-
1987
- 1987-12-25 JP JP19582987U patent/JPH01102780U/ja active Pending
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