JPH01102901U - - Google Patents

Info

Publication number
JPH01102901U
JPH01102901U JP19745887U JP19745887U JPH01102901U JP H01102901 U JPH01102901 U JP H01102901U JP 19745887 U JP19745887 U JP 19745887U JP 19745887 U JP19745887 U JP 19745887U JP H01102901 U JPH01102901 U JP H01102901U
Authority
JP
Japan
Prior art keywords
input command
limiter
closed
loop
processing device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19745887U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP19745887U priority Critical patent/JPH01102901U/ja
Publication of JPH01102901U publication Critical patent/JPH01102901U/ja
Pending legal-status Critical Current

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  • Feedback Control In General (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図乃至第6図は本考案の一実施例を示すも
のであつて、第1図は実施例装置の概略構成図、
第2図は実施例装置における各部の信号波形図、
第3図は本考案が適用されるシステムの一例を示
す構成図、第4図は入力コマンドに対する操作量
の関係を示す図、第5図はリミツト値rLの設定
を説明する為の図、第6図は時定数τの設定を説
明する為の図である。また第7図は従来システム
の構成図であつて、第8図は従来システムの問題
点を説明する為の図である。 1…制御器、2…制御対象、4…入力コマンド
処理装置、5…リミツター、6…一次遅れフイル
ター。
1 to 6 show an embodiment of the present invention, in which FIG. 1 is a schematic configuration diagram of the embodiment device;
FIG. 2 is a signal waveform diagram of each part in the embodiment device,
FIG. 3 is a block diagram showing an example of a system to which the present invention is applied, FIG. 4 is a diagram showing the relationship between input commands and operation amounts, FIG. 5 is a diagram for explaining the setting of the limit value rL, and FIG. FIG. 6 is a diagram for explaining the setting of the time constant τ. Further, FIG. 7 is a block diagram of a conventional system, and FIG. 8 is a diagram for explaining problems in the conventional system. DESCRIPTION OF SYMBOLS 1...Controller, 2...Controlled object, 4...Input command processing device, 5...Limiter, 6...First-order delay filter.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 閉ループ系を構成してフイードバツク制御を行
うシステムの入力コマンドラインに設けられ、入
力コマンドの値を制限するリミツタ、およびこの
リミツタを介して与えられる上記入力コマンドに
所定の応答遅れを与える一次遅れフイルタを具備
したことを特徴とする閉ループ系の入力コマンド
処理装置。
A limiter is provided on the input command line of a system that configures a closed loop system to perform feedback control, and limits the value of the input command, and a first-order lag filter that provides a predetermined response delay to the input command given through the limiter. A closed-loop input command processing device characterized by:
JP19745887U 1987-12-28 1987-12-28 Pending JPH01102901U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19745887U JPH01102901U (en) 1987-12-28 1987-12-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19745887U JPH01102901U (en) 1987-12-28 1987-12-28

Publications (1)

Publication Number Publication Date
JPH01102901U true JPH01102901U (en) 1989-07-12

Family

ID=31488008

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19745887U Pending JPH01102901U (en) 1987-12-28 1987-12-28

Country Status (1)

Country Link
JP (1) JPH01102901U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62199904A (en) * 1986-02-27 1987-09-03 Fuji Electric Co Ltd Output controller for steam turbine

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62199904A (en) * 1986-02-27 1987-09-03 Fuji Electric Co Ltd Output controller for steam turbine

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