JPH01102934U

JPH01102934U -

Info

Publication number: JPH01102934U
Application number: JP19674887U
Authority: JP
Priority date: 1987-12-25
Filing date: 1987-12-25
Publication date: 1989-07-12

Description

[Brief explanation of the drawing]

第１図はこの考案による実施例の原理構成図、
第２図は実機の要部構成図、第３図は第２図のタ
イムチヤート、第４図は従来のＩＣＥの要部構成
図、第５図は第４図のタイムチヤート、第６図は
第１図のタイムチヤート、第７図はクロツク位相
調整回路７の実施例の構成図、第８図は第７図の
タイムチヤート、第１０図はクロツク位相調整回
路７のほかの実施例の構成図、第１０図は第９図
のタイムチヤートである。１……クロツク発生回路、２……ソケツト、３
……ＭＰＵ、４……ＭＰＵ、５……ケーブル、６
……ＥＭＰＵ、７……クロツク位相調整回路、７
１Ａ……遅延素子、７１Ｂ……位相検波回路、７
２Ｂ……増幅機、７３Ｂ……発振器、７４……電
源、１０……実機、１１……実機、１２……ＩＣ
Ｅ、１３……ＩＣＥ。 Figure 1 is a diagram of the principle configuration of an embodiment based on this invention.
Figure 2 is a configuration diagram of the main parts of the actual machine, Figure 3 is a time chart of Figure 2, Figure 4 is a diagram of the main parts of a conventional ICE, Figure 5 is a time chart of Figure 4, and Figure 6 is a diagram of the main parts of a conventional ICE. 1 is a time chart, FIG. 7 is a configuration diagram of an embodiment of the clock phase adjustment circuit 7, FIG. 8 is a time chart of FIG. 7, and FIG. 10 is a configuration of another embodiment of the clock phase adjustment circuit 7. 10 is a time chart of FIG. 9. 1...Clock generation circuit, 2...Socket, 3
...MPU, 4...MPU, 5...Cable, 6
...EMPU, 7...Clock phase adjustment circuit, 7
1A...Delay element, 71B...Phase detection circuit, 7
2B... Amplifier, 73B... Oscillator, 74... Power supply, 10... Actual machine, 11... Actual machine, 12... IC
E, 13...ICE.

補正昭６３．３．２５図面の簡単な説明を次のように補正する。明細書第１１ページ第１４行の「第１０図」を
「第９図」と補正する。Amendment March 25, 1983 The brief description of the drawing is amended as follows. "Figure 10" on page 11, line 14 of the specification is corrected to "Figure 9."

Claims

[Claims for Utility Model Registration] (1) An ICE having a clock phase adjustment circuit that receives clock B output from an actual device and outputs a clock C having the same phase as clock A in the actual device. (2) An ICE having a clock phase adjustment circuit according to claim 1, wherein the clock phase adjustment circuit is a delay element. (3) Utility model registration claim 1 in which the clock phase adjustment circuit is an oscillator with a phase lock loop
ICE having the clock phase adjustment circuit described in Section 1.