JPH0110567Y2 - - Google Patents

Description

[Detailed Description of the Invention] This invention relates to an output stabilizing device in a phase shift type position detection device.

An example of an output stabilizing device in a phase shift type position detecting device is shown in the specification of the earlier application No. 158243/1983. In this prior application, frequent fluctuations in the output count value (latch data) that can occur when the rotational position of the machine shaft comes to rest at a position corresponding to the switching point of the phase difference count value in the phase difference detection circuit (this fluctuation is caused by (which may occur every sampling period of the count value). Therefore, the range of fluctuations that can be absorbed is extremely narrow.
For example, the output signal can be stabilized only when the fluctuation range in one sampling period for phase difference measurement is less than 1/4 period of the clock pulse for phase difference counting. Therefore, if the amount of phase shift detected by the position detection device changes due to vibrations being applied as a disturbance to a machine shaft that is stationary at a certain rotational position, it is not possible to absorb the fluctuation in the amount of phase shift due to such disturbance. I can't do it and I react sensitively. By the way, depending on the purpose of use of the phase shift type position detection device, it may not be necessary to generate an output signal with the same accuracy as the phase difference measurement accuracy, and in such cases, a certain degree of variation in the machine axis may be ignored. It is desirable to produce a stable output signal. However, as mentioned above, it was difficult to absorb the wobbling of the machine shaft with the stabilizing device as shown in the prior application.

This idea was made in view of the above points,
The present invention aims to provide an output stabilizing device that can ignore mechanical fluctuations caused by external disturbances and supply a stable output signal in a phase shift type position detection device.

An embodiment of this invention will be described in detail below with reference to the accompanying drawings.

In FIG. 1, counter 1 is modulo M-adic (M is any integer), and clock generation circuit 2
Count the high-speed clock pulses CP given by CP. A signal from a predetermined frequency-divided output stage of this counter 1 is given to a sine/cosine generation circuit 3,
A sine signal sinωt and a cosine signal cosωt are generated from the circuit 3. Here, it is possible to synchronize one period of the sine signal sinωt with the period in which the count value of counter 1 changes from 0 to the maximum value, and then the count value of counter 1 has a phase of "360/M degrees". Corresponds to the corner. Signals sinωt and cosωt output from the circuit 3 are input to the primary sides 4a and 4b of the phase shift type sensor 4, respectively. The phase shift type sensor 4 outputs an output signal Y=sin(ωt−θ) from the secondary side 4c, which is obtained by shifting the input signals sinωt and cosωt by a phase angle θ corresponding to the rotational position of the machine shaft. For example, a variable magnetoresistive sensor as disclosed in Japanese Patent Application No. 147425/1984 can be used.

The output signal Y of the sensor 4 is applied to an inverting input terminal of an analog comparator 5 for zero-cross detection. A reference voltage Vref is applied to the non-inverting input terminal of the comparator 5, and a rectangular pulse signal _S0 of "1" or "0" is output depending on the magnitude of the sensor output signal Y and the reference voltage Vref. do. The output signal _S0 of the comparator 5 is latched by a D flip-flop 6 in synchronization with the clock pulse CP, and its latch output _S1 is used as a latch pulse for the latch circuit 7. The latch circuit 7 latches the count value of the counter 1 when a latch pulse is applied from the flip-flop 6 (when the signal rises to "1"). In this way, the data D〓 indicating the phase difference θ corresponding to the rotational position of the mechanical shaft is latched in the latch circuit 7.

Phase difference data D latched in latch circuit 7
is given to the address input of ROM (abbreviation for read only memory) 8. ROM8 is 2 sets of ROM
Contains #1 and #2. One ROM#1 is
It stores a predetermined output signal corresponding to the rotational position of the machine shaft, and the other ROM #2 stores data for output stabilization. ROM#1
The value of the data stored in the address is the same for each consecutive address. for example,
When ROM#1 functions to convert rotational position data (phase difference data) D〓 with an accuracy of 2048 divisions into angle information of 0 degrees to 360 degrees, 0 degrees, 1 degree, 2
Assign each angle information called degrees. Data is stored in ROM#2 with a weight that is 1/2 of the lowest weight of the data stored in ROM#1. In other words, ROM
Assuming that the data stored in #1 is angle information with a minimum unit of 1 degree, the data with a weight of 0.5 degrees is
It is stored in ROM #2. An example of the storage format of ROM #1 and #2 is shown in Figure 2. Multiple consecutive addresses for reading the same value from ROM #1 are divided into two, and the ROM
#2 stores "0" (or "1") corresponding to one address group, and stores "1" (or "0") corresponding to the other address group.

The output signal of the D flip-flop 6 is applied to the data input (SI) of the shift register 9, and the output of an appropriate lower bit (for example, the second lower bit) of the output of the counter 1 is applied as the clock pulse CK of the shift register 9. It will be done. The output Q1 of the first stage of the shift register 9 is the latch circuit 1.
The output Q2 of the second stage is applied to the ROM 8 as a switching signal between ROM #1 and #2, and the output Q3 of the third stage is applied to the latch circuit 11 as a latch pulse.
When the switching signal given to ROM8 is “0”
ROM#1 is selected, and when it is "1", ROM#2 is selected.

When the output signal of the D flip-flop 6 rises to "1", a new count value D≦ is latched in the latch circuit 7. Thereafter, when several clock pulses CP are generated, a clock pulse CK is applied to the shift register 9, and "1" is taken into the first stage Q1. When the output signal of the first stage Q1 rises to "1", the data read from the ROM #1 is latched into the latch circuit 10 in accordance with the count value D. At this time, the second stage
The output of Q2 is "0" and ROM #1 is selected. Next, when clock pulse CK is applied, the output signal of second stage Q1 of shift register 9 rises to "1" and ROM #2 is selected. Furthermore, when the next clock pulse CK is applied, the third stage Q3 of the shift register 9
The output signal rises to “1” and the data (“1”) read from ROM#2 according to the count value D
or "0") is latched in the latch circuit 11.

The output terminal of the latch circuit 11 is connected to the non-inverting input terminal of the comparator 5 via a feedback resistor R _f . If the level of the reference voltage Vref when the output signal of the latch circuit 11 is "0" is Vref ₀ , and the level when it is "1" is Vref ₁ , then there is a relationship of Vref ₀ <Vref ₁ . Therefore, the level of the reference voltage Vref of the comparator 5 is switched depending on the value "1" or "0" of the data latched in the latch circuit 11.

As an example, consider a case where the mechanical axis is stationary at a position corresponding to the count value "13" of counter 1. Corresponds to addresses 11 to 16
Assuming that the output data value of ROM#1 is "2", the ROM corresponding to addresses 11, 12, and 13
#2 data is “0”, address 14, 15, 1
It is assumed that the data in ROM #2 corresponding to 6 is "1". Figure 3a shows the output signal Y=sin of sensor 4
(ωt-θ), and b shows the state of change in the count value of the counter 1 before and after the latch timing to the latch circuit 7 on a larger scale than the time scale of a. FIGS. 3c and 3d show the outputs of ROM #1 and #2 corresponding to addresses 11 to 16, and these are shown without regard to the time axis.

At the latch timing indicated by A, the count value "13" is latched in the latch circuit 7, and the ROM#1
Data with value “2” is read from ROM
“0” is read from #2. Therefore, the reference voltage Vref of comparator 5 is at the lower level.
Vref Set to ₀ . Assume that vibration is applied to the mechanical shaft as a disturbance, and the sensor 4 sensitively responds to this, causing the phase shift θ of the output signal Y to fluctuate somewhat. As a result, if, for example, the count value "16" is latched in the latch circuit 7 as shown in timing B, the data with the value "2" is read out from ROM#1 in the same way as last time, but the data with the value "2" is read out from ROM#2 as before. 1”
is read out. As a result, the reference voltage Vref of the comparator 5 is switched to the higher level _Vref1 . Therefore, at the next C timing, the latch timing will be somewhat earlier, for example, the count value will be "15".
is latched in the latch circuit 7. Here, if the level of the reference voltage Vref remains Vref ₀ , the latch timing may be delayed and the count value "17" may be latched in the latch circuit 7, as shown by the broken line, and in that case, the ROM The value of the output data of #1 switches to "3", and the disturbance vibration applied to the machine shaft causes a measurement error. However, as in this invention, such malfunctions can be prevented by switching the reference voltage level and advancing the latch timing.

Note that ROM#2 is not limited to a storage circuit, but may be a decoder or other conversion circuit. Also, ROM
If #1 data changes every 2 addresses,
The data of ROM#2 is “1” for each address,
Of course, "0" is assigned alternately.

As explained above, according to this invention, the reference voltage level of the analog comparator is alternately switched for every one or more consecutive phase difference count values, so vibrations caused by disturbances applied to the machine shaft are It is particularly effective when there is no need to generate an output signal with the same precision as the phase difference count value (when the precision of the output signal is coarser than the phase difference count value).

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of this invention, FIG. 2 is a diagram showing an example of the storage format of the ROM shown in FIG. 1, and FIG. 3 is a diagram for explaining an example of the operation of the same embodiment. It is. 1...Counter, 2...Clock generation circuit, 3
...Sine/cosine generation circuit, 4...Phase shift type sensor, 5...Analog comparator, 6...
...D flip-flop, 7, 10, 11... latch circuit, 8... ROM, 9... shift register.

Claims (1)

[Claims for Utility Model Registration] A phase-shift type sensor that generates an output signal that is a phase-shifted reference AC signal according to the position of a machine axis; a counting means that counts a predetermined clock pulse; an analog comparator that compares the phase with a reference voltage corresponding to the phase and outputs a pulse signal synchronized with a predetermined phase of the output signal; and a count value of the counting means is held in response to the output pulse signal of the analog comparator. , a phase shift type position detection device comprising count value holding means for obtaining data indicating a phase difference between the reference AC signal and the output signal, wherein "1" is set for every one or more consecutive count values.
and "0" data are alternately assigned in advance, and outputs data according to the assignment according to the count value held by the count value holding means; Value “1”
or a control circuit that switches the predetermined phase by switching the level of the reference voltage of the analog comparator in response to "0", thereby giving a hysteresis characteristic to the generation condition of the output pulse signal in the analog comparator. An output stabilizing device for a phase shift type position detection device, characterized in that: