JPH01106251A - Data transfer control system - Google Patents

Abstract

PURPOSE:To attain rapid data transfer control operation by simultaneously using plural information transfer routes when rapid data transfer is required. CONSTITUTION:Each of information processors 101, 102 has a CPU 105 and a main memory part 106 and is connected to a peripheral controller 103 by plural information transfer routes 104 through respective channel parts 107 and an interface control part 110. The controller 103 is constituted of a control processor 108, a common memory part 109, a control processor 108 capable of controlling plural information transfer routes 104, a peripheral device control part 111, and a line control part 112. When rapid data transfer which can not be transferred only by one information transfer route 104 is required, plural routes 104 are simultaneously used to execute rapid transfer processing.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a data transfer control method, and in particular, to a data transfer control system that provides multiple information transfer routes between information processing devices or between an information processing device and a peripheral control device. The present invention relates to a data transfer control method within a peripheral control device of an information processing device 2 when the information processing device 2 has a peripheral control device.

[Conventional technology]

The information processing devices and the information processing devices or the information processing devices and the peripheral control devices are connected by one or more information transfer routes for transferring control information and data. Information transfer processing is performed between the information processing devices or between the information processing devices and peripheral control devices according to a certain transfer control procedure using the interface signal line prepared as the information transfer route. ing.

However, with improvements in data transfer speeds of peripheral devices connected to subordinate devices and improvements in the performance of information processing systems, there has been an increase in the number of connections between information processing devices, or between information processing devices.

A situation has arisen in which a transfer rate higher than the maximum executable data transfer rate between an information processing device and a peripheral control device is required.

In general, the methods to improve the data transfer speed of the interface between devices are as follows: (1) For example, by increasing the width of the data transfer signal line, such as expanding the bus width from 1 byte to 2 bytes, simultaneous transfer is possible. Increase the amount of data.

(2) The data transfer cycle is shortened by speeding up the channel (CI-1) device etc. that executes transfer control and shortening the time required for one data transfer/response process.

(3) Change the data transfer control procedure, for example, from a control procedure that transfers data in 1-byte units and confirms a response to n
By changing the control procedure to one in which data is transferred in byte units and response confirmation is performed, the number of response confirmations is reduced and the data transfer speed is improved.

(4) By performing data transfer synchronized with the same clock on the data sending side and the data receiving side, and by synchronizing the data transfer process and the response process, the next The waiting time required for data transfer response confirmation processing is t.
g Oyt to improve data transfer speed.

Various methods are used, such as:

[Problem that the invention seeks to solve]

However, as mentioned above, when expanding the data bus width and increasing the speed of the CH table device, restrictions on variations in data transfer speed (skew) between interface signal lines become stricter. There is a problem in that it is necessary to shorten the . Furthermore, a peripheral control device to which conventional low-speed peripheral devices are connected is also required to support a high-speed data transfer control function, resulting in an expensive system.

On the other hand, when transferring multiple pieces of data at once, the recovery process for errors that occur during data transfer becomes complicated. In this case, a buffer mechanism is required to temporarily hold the data being transferred until the data transfer response confirmation operation is completed, which increases the device cost. In addition, in order to achieve synchronous data transfer, it is necessary to always use clocks with the same phase between the data sending and receiving sides, which requires a clock transfer function 9 phase comparison function between devices. This increases the complexity of the hardware.

Between other information processing devices.

Alternatively, a method that allows connection and accommodation of nine lines of peripheral devices with a data transfer speed higher than that supported by the interface without changing the data transfer speed between the information processing device and the peripheral control device is to By temporarily retaining the data transferred to the controller in a buffer within the control device, the high-speed data transfer speed of peripheral devices etc. can be absorbed, and the data transfer speed between the buffer and the other device is reduced to an executable data transfer speed as an interface. There is a method to perform data transfer operation.

This method of absorbing data transfer speed differences by preparing a buffer is useful for devices such as sector-based magnetic disk drives, where the data length is divided into certain lengths and data transfer requests occur at certain time intervals. is effective for connections, but data is transferred continuously that overwhelms the buffer capacity.
There is a problem in that when continuous data transfer is performed from a high-speed line, data is lost due to buffer overflow, making it impossible to use this method. Furthermore, data transfer between information processing devices is performed at a speed lower than the data transfer speed originally possessed by peripheral devices, etc.
There is also the problem that the high speed performance of peripheral devices cannot be utilized as a system.

The present invention has been made in view of the above circumstances, and its purpose is to solve the above-mentioned problems in the conventional data transfer control system and to In a system that has multiple information transfer routes between a peripheral controller and a peripheral control device, the multiple information transfer routes are usually used by multiple independent devices to simultaneously control multiple devices, and to control multiple devices simultaneously. If high-speed data transfer that cannot be transferred using the book information transfer route is required, the multiple information transfer routes described above can be used simultaneously to perform high-speed data transfer processing, and the multiple information transfer routes described above can be transferred as if Data transfer control that can be controlled from a host device (software) like a single information transfer route and achieves high-speed data transfer operations without changing the data transfer control function performed by conventional software. The goal is to provide a method.

[Means for solving problems]

The above-mentioned object of the present invention is to provide an information processing system having a plurality of information transfer routes between devices, in which each of the plurality of information transfer routes is used independently to execute control operations and data transfer operations for different devices. one control means;
a second control means for performing a high-speed data transfer operation using the plurality of information transfer routes simultaneously, and a second control means for performing a high-speed data transfer operation using the plurality of information transfer routes; A means for arbitrarily setting an information transfer route to be used is provided, and the plurality of information transfer routes are used as independent information transfer routes to transfer control information or data of separate devices according to the settings of the setting means. data, characterized in that it is configured to be switchable between a first mode used for data transfer and a second mode that realizes high-speed data transfer operation using a plurality of information transfer routes for which use permission is set. This is achieved by a transfer control method.

[Effect]

As will be described in detail below, in the data transfer control method according to the present invention, in a system having a plurality of information transfer routes between an information processing device and between an information processing device or between an information processing device and a peripheral control device, This information transfer route is normally used by multiple independent devices to control multiple devices simultaneously, and when high-speed data transfer that cannot be transferred using a single information transfer route is required, , the above-mentioned plurality (n) of information transfer routes can be controlled from the host device (software) as if they were a single information transfer route, without changing the data transfer control function performed by conventional rough l-ware. In addition, it achieved high-speed data transfer operation.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 shows an example of a connection configuration between the information processing device 1 and the peripheral control device.
2 is the peripheral control device 103 and the plurality of information transfer routes L.
A configuration connected by O4 is shown.

The information processing device 101 includes a central processing unit (CPU) 105
, a main memory section (MEM) 106, and a plurality of channel sections (CH) 107, and is connected to the peripheral control device 103 via a plurality of information transfer routes 104 via the channel section 107. .

The information processing device 102 is composed of a central processing unit (CPU) 105, a main memory unit (MEM) 106, and an interface control unit (IFC) 110. and are connected by a plurality of information transfer routes 104.

The peripheral control device 103 includes a control processor 108, a common memory section 109, an interface control section (IFC) 110 that can control a plurality of information transfer routes 104, a peripheral device control section (IOC) 111, and a line control section (L).
C) consists of 112.

FIG. 3 shows a block configuration of the interface control section 110.
0 is.

(1) Control processor 108 in peripheral control device 103,
A system bus interface section 201 having a system bus control function for realizing an interface with the common memory section 109, peripheral device control section 111, line control section 112, etc., and a driver/receiver function between system buses.

(2) Analyzing and executing interface operation instruction commands from the control processor 10g, issuing commands and managing the status of multiple signal line control units 203 (described later), and executing data transfer operations using multiple information transfer routes 104 IFC controller 2 that performs control, management of the internal state of the interface control unit 110, reporting of abnormal states, etc.
(3) It has registers necessary to control the interface signal lines of each information transfer route 104.

An interface signal line control function 210 that sets/resets signal lines, a data transfer function 211 that actually executes data transfer, has a transfer counter necessary for executing data transfer, a common memory address, a counter remaining during data transfer, etc. , detects a processing request from the other device, and performs the above I
Processing request detection function 2 that reports to the FC controller 202
(4) a plurality of signal line control units 203 and a common memory unit 109;
(5) holding internal states necessary for the operation of the IFC controller 202, holding instructions, commands, etc. transferred from the control processor 108; Maintaining the operating mode of each information transfer route 104, configuration conditions at the time of data transfer execution, and I
and a local memory unit 205 used to hold the status of each part in the FC controller 202, failure information, etc.

(6) Consists of driver/receiver circuits 206 for each interface signal line of the information transfer route 104.

FIG. 1 shows a processing example for explaining the operation of the peripheral control device 103 described above, in which data is input from a line having a data transfer rate higher than the data transfer rate of the information transfer route 104, and This figure shows the flow of processing when data is transferred to the other party's device via the .

The flow of processing within the peripheral control device 103 will be described below with reference to FIG. 1, taking as an example the case where data is transferred from the peripheral control device 103 to the information processing device 101 or 102.

(1) Immediately after the power is turned on, or when a failure is detected in the peripheral control device and a reset operation is executed, the configuration conditions for the information transfer route 104 between the interface control unit 110 and the channel unit 107 are not set. . For this reason,
In order to execute data transfer using a plurality of information transfer routes 104 , the control processor 108 instructs the interface control unit 110 to set configuration conditions for the information transfer routes 104 301 . Interface control unit 110
Upon receiving the configuration condition setting instruction, performs a link establishment operation 302 for the information transfer route 104 with the channel unit 107 and reports 303 the processing results to the control processor 108 .

FIG. 4(,) shows an example of a link establishment operation performed between the interface control section 110 and the channel section 107.

The interface control unit 110 controls the control processor 108
ATT (Attention) 40 via signal line control unit 203 in order to receive control information 401 necessary for link operation from and notify processing request to the other party's information processing device.
Enable 2. The control information 401 is a parameter to be notified to the other party's device, and includes a control code 403 indicating a link establishment request. Transfer parameter length 404. Transfer data block length when executing data transfer: 405° Maximum transfer speed: 406.
It consists of a maximum waiting time 407 to wait for securing an information transfer route at the time of a data transfer request, and specification 408 of the information transfer route to be used and the data transfer execution order between each route.

FIG. 4(b) shows control information 401 and information transfer route 1.
Route numbers #1 to #4 assigned to 04 are used in the order, and the block length that each information transfer route 104 transfers at one time is 512 bytes.

An example is shown in which the maximum waiting time for securing a channel is set to 5011S.

The partner information processing device that received the above-mentioned ATT402 sends RE A, D commands to obtain parameters4.
09. The interface control unit 110
When a command is detected, control information is sent out 41O, and an end status signal 411 indicating completion of sending is enabled.

In response to the received control information, the other party's information processing device
If you want to permit all use of the information transfer route 104 specified by the parameter, - Return the received parameters as they are to the peripheral control bag 22103, and use the information transfer route 104 as is.
- 104, or if only part of the requested information transfer route 104 is permitted, issue a WRITE command 412 to change the parameter contents and return the parameters. ,respond.

The interface control unit 110 receives the returned parameters and sends an end status signal 4 confirming parameter reception.
13, the operation mode of each information transfer route 104 is determined based on the parameters sent from the other device.
retains the configuration conditions at the time of data transfer execution in the local memory 205 and reports the results to the control processor 108 415;
End link operation.

(2) When the link establishment is completed, the control processor 108 instructs the interface control unit 110 to wait for a command transfer from the channel unit 107 (304), and the interface control unit 110 enters a command waiting state 305. Thereafter, when the channel unit 107 issues a control command 306 that instructs input of data from the line and an instruction to transfer the data input from the line to the channel unit 107 using the control command, the interface control unit 110 sends the RE
It receives the AD command 307 and restarts internal operations.

Note that before entering the waiting state 305, the control command 30
6. When the interface control unit 110 detects a command such as the READ command 307, the interface control unit 110 reports the detection of an asynchronous processing request from the other device to the control processor 108, and the control processor 108
In response to a command reception instruction from the device, the device receives the command transferred from the other device.

The interface control unit 110 receives the control command 30 described above.
6 and the processor 108 that controls the READ command 307.
308, the control processor 108 analyzes the reported command and issues an instruction 3 to the interface control unit 110 to start a data transfer operation (WRITE operation).
09 and an instruction 310 to the line control unit 112 to start inputting data from the line.

(3) The line control unit 112 starts data input operation from the specified line, and stores the input data in the common memory 10.
9 to the interface control unit 110 via 311
do. The interface control unit 110 executes the data transfer operation based on the instruction 309 to start the data transfer operation and the transfer data from the line control unit 112.

FIG. 5 shows the flow when executing a data transfer operation between the channel section 107 and the interface control section 110 using a plurality of information transfer routes 104.

When the interface control unit 110 is configured and set to perform high-speed data transfer using a plurality of information transfer routes 104, the interface control unit 110 receives the WRITE command given by the control processor IO8 at the time of data transfer start instruction 309. Based on the parameters, the IFC controller 202:
Calculate the data length to be transferred on each information transfer route 104 and the common memory address where the transfer data exists 501 L,
, is set 502 in the register in the data transfer function 211 of each signal line control unit.

Thereafter, the IFC controller 202 performs data transfer in units of specified block length for each information transfer route when the right to use the information transfer route is established for all the information transfer routes 104 used for data transfer. .

When requesting 503 for preferential use of the information transfer routes 1 and 04, if the right to use the information transfer route 104 is not immediately granted because the information transfer route 104 is in the process of data transfer or control operation,
The signal line control unit 203 issues an interface release request 504 to the channel unit 107 on the other side, or waits for the completion of the processing being executed and then releases the information transfer route 1-! Secure the right to use 04. At this time, if the right to use the information transfer route 104 cannot be acquired within the specified specified time 407, an error is reported 505 to the control processor 108 and the process is terminated.

Each signal line control unit 203 independently reads data from the line input to the common memory 109 via the data transfer control unit 204, divides it into a plurality of blocks, and performs a data transfer operation on each block in succession. is executed 506.

When each signal line control unit 203 successfully transfers all the set data blocks, it reports the data transfer completion to the other channel unit 107 (507), and restores the right to use the information transfer route 104 (508). IFC completes processing
The IFC controller 202 waits for data transfer completion reports from all the signal line control units 203 and then reports the completion to the control terocessor 108.

FIG. 6 shows an example of the relationship between the WRITE command given from the control processor 108 at the time of the data transfer start instruction 309 and the channel commands substantially executed by each information transfer route 104.

It is assumed that each information transfer route 104 is configured based on control information 401 shown in FIG. In other words, using information transfer routes #1 to #4, the data block length is 512 bytes, and the data to be transferred on each route is arranged in 512-byte units in the order of addresses #1 → #4 assigned to each route. Assume that data transfer is performed using

Each data area 606 of the common memory unit lO9 specified by the issued WRITE command 601 is divided into a plurality of equivalently data chained channel commands 602 to 605 in each information transfer route #1 to #4, It is held in a register in the data transfer function 211 of each signal line control unit 203.

Channel commands 602 to 605 transfer data in the common memory section 109 with a data length of 512 bytes and data addresses separated by 2048 bytes, and specify a data chain of control flags to transfer each block continuously.

For example, information transfer route #1 includes 512-byte blocks A (address: ABCD), E
(Address: ABCD+2048), I (Address:
A B CD +4096) are transferred in this order, and the data chain is specified as a control flag. As a result, information transfer route #1 has three WRITE
Controlled by channel program by command.

FIG. 7 shows an example of state transition of each route when data is transferred using four information transfer routes.

It is assumed that the information transfer route #1 (701) is configured and set based on the parameters 401 shown in FIG.

At the time of this configuration/setting, information transfer route #1 (
701) starts requesting use of other information transfer routes #2 to #4 in order to start high-speed data transfer 702
When this occurs, #2 is executing an operation related to controlling peripheral devices (control operation) 703, #3 is executing its own data transfer operation 704, and #4 is not being used. 705.

#1 is #2. #3. Requests #4 for the right to use the interface 706 L, Receives permission to use the interface due to the end of control operations and temporary suspension of data transfer operations from #2 and #3 that are currently in use 707, and transfers data from the line. Sequentially, information transfer route #1 ~ block by block
Data transfer is executed 70g using #4.

Data is allocated to each information transfer route 104 when channel commands 602 to 605 shown in FIG. #C, #D, #E,・
... (each block length is 512 bytes) are sequentially routed to root #1. #2゜#3. #4. #1. #2. Transferred via...

Each information transfer route sends a completion report 709 of the transfer of the allocated data amount to the other channel unit 107, sends a completion report 710 to the information transfer route #1 (701) that requested the data transfer, and sends a completion report 710 to the information transfer route #1 (701) that requested the data transfer. 1 (701
) waits for all data transfers to be completed and reports 711 the completion of the data transfer operation to the control processor 108.

After the completion report 709, the information transfer route #3 resumes the interrupted data transfer operation 712.

(4) When all data transfer operations specified by each information transfer route 104 have been successfully completed, the interface control unit 110 controls the channel unit 107 and the control processor 10.
8, a READ command end report 312 and a data transfer end report 313 are performed, and the READ operation specified by the channel unit 107 is ended.

(5) After this, the control processor 108 again issues 1, an instruction 314 to wait for a command, or an instruction to request processing to the other device to the interface control unit 110, and continues processing.

In the above embodiment, the case of data transfer operation from a peripheral control device to an information processing device was taken as an example, but data transfer from an information processing device to a peripheral control device can also be realized using the same control method.

Further, as shown in the above embodiment, the present data transfer control method can be applied regardless of the control method of the partner device (channel, etc.). Therefore, even if the control method of the other device is a method in which a data transfer operation is executed by using one channel and a channel command to turn multiple information transfer routes into one high-speed information transfer route, as shown in this operation example, The single data transfer control method can also be applied to conventional control methods in which channel commands are issued as a plurality of independent information transfer routes and data transfer operations are executed while synchronizing the plurality of information transfer routes.

〔Effect of the invention〕

As described above, according to the present invention, in an information processing system having a plurality of information transfer routes between devices, each of the plurality of information transfer routes is used independently to perform control operations and data transfer operations of different devices. a first control means for executing a high-speed data transfer operation that simultaneously uses the plurality of information transfer routes; and a second control means for executing a high-speed data transfer operation that simultaneously uses the plurality of information transfer routes; means for arbitrarily setting an information transfer route to be used when performing a data transfer operation, and according to the setting contents of the setting means, the plurality of information transfer routes can be set as independent information transfer routes and separated from each other. It is possible to switch between the first mode, which is used for transferring device control information and data transfer, and the second mode, which uses multiple information transfer routes for which usage permissions are set to achieve high-speed data transfer operation. Normally, by using the multiple information transfer routes mentioned above with multiple independent devices, simultaneous control of multiple devices can be executed, as well as high-speed data transfer that cannot be transferred using a single information transfer route. When it becomes necessary to perform high-speed data transfer processing using the multiple information transfer routes at the same time, the multiple information transfer routes can be controlled from the host device as if they were a single information transfer route. This has the remarkable effect of realizing high-speed data transfer control operations without changing the data transfer control functions performed by conventional software.

This makes it possible to suppress the increase in hard costs associated with preparing high-speed data transfer routes, and to synchronize each information transfer route within a channel program that executes high-speed data transfer using multiple information transfer routes. This eliminates the need for complex synchronous control processing for control, and has the effect that control programs can be easily created.

Furthermore, since the execution results of data transfer using a plurality of information transfer routes are reported in one input/output interrupt to the CPU, CPU overhead associated with interrupt processing is reduced. On the other hand, in the case of processing that does not require particularly high-speed data transfer, such as control operations, one peripheral device, etc. can be used as an independent interface for each information transfer route, and one peripheral control etc. can be executed simultaneously on each information transfer route. ,
It is possible to realize simultaneous operation of peripheral devices, etc., and as a result, there is an effect that the response time of peripheral devices, etc. can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the basic processing flow in a data transfer control method according to an embodiment of the present invention, and FIG. A diagram showing an example of a connection configuration, FIG. 3 is a block diagram of an interface control unit, FIG. 4(a) is a diagram showing an example of an operation for establishing a link of an information transfer route, and FIG. 4(b) is an example of control information. Figure 5 is a diagram showing the flow when executing a data transfer operation using multiple information transfer routes, Figure 6 is a diagram showing the flow of the channel commands executed on each information transfer route and the channel commands given from the control processor. FIG. 7 is a diagram showing an example of the relationship, and is a diagram showing an example of state transition of each route when data transfer is performed using the information transfer route. 101.102: Information processing device, 103: Peripheral control device, 104: Information transfer route, 105: Central processing unit,
106: Main memory section, 107: Channel section, 108: Control processor, 109: Common memory section, 110: Interface control section, 111: Peripheral device control section, 112: Line control section, 201 System bus interface section ,2
02: IFC controller, 203: Signal line control section, 2
04: Data transfer control unit, 205: Local memory unit,
206: Driver/receiver circuit, 210: Interface signal line control function, 211: Data transfer function, 212
: Processing request detection function. Patent Applicant Nippon Telegraph and Telephone Corporation Figure 2 Figure 6 Figure 6 (a) WRITE: 2 Mandoro 01 (1)) Information Transfer Route +1 for Chaki Leando 602 No. 6
Figure (C) Channel command for information transfer rooter 2)'6
03(d) Information transfer route +3 chia tree command "6"
04 (e) Information transfer route + raw channel command'' 605 Figure 6 (f) Contents of common memory 606

Claims (1)

[Claims] (1) In an information processing system having a plurality of information transfer routes between devices, a first control means that independently uses the plurality of information transfer routes to execute control operations and data transfer operations for different devices; , a second control means for performing a high-speed data transfer operation using the plurality of information transfer routes simultaneously; and a case where the data transfer operation using the plurality of information transfer routes is performed from the host device to the data transfer control means. means for arbitrarily setting information transfer routes to be used for transfer of control information and data of separate devices as independent information transfer routes according to the settings of the setting means. The device is characterized in that it is configured to be switchable between a first mode used for transfer and a second mode that realizes high-speed data transfer operation using a plurality of information transfer routes for which usage permission is set. Data transfer control method.