JPH01106455A - Semiconductor integration circuit device - Google Patents

Semiconductor integration circuit device

Info

Publication number
JPH01106455A
JPH01106455A JP62263433A JP26343387A JPH01106455A JP H01106455 A JPH01106455 A JP H01106455A JP 62263433 A JP62263433 A JP 62263433A JP 26343387 A JP26343387 A JP 26343387A JP H01106455 A JPH01106455 A JP H01106455A
Authority
JP
Japan
Prior art keywords
integrated circuit
lead frame
circuit device
circuit element
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62263433A
Other languages
Japanese (ja)
Inventor
Mitsuaki Uenishi
上西　光明
Tatsuo Kikuchi
菊池　立郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP62263433A priority Critical patent/JPH01106455A/en
Publication of JPH01106455A publication Critical patent/JPH01106455A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H10W72/01308—Manufacture or treatment of die-attach connectors using permanent auxiliary members, e.g. using alignment marks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07311—Treating the bonding area before connecting, e.g. by applying flux or cleaning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
    • H10W72/07353—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/331—Shapes of die-attach connectors
    • H10W72/334—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 産業上の利用分野 本発明はＩＣカード等に使用する半導体集積回路装置に
関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a semiconductor integrated circuit device used in IC cards and the like.

従来の技術 近年、記憶容量の大きさ、機密保持の点から。Conventional technology In recent years, there has been an increase in storage capacity and confidentiality.

マイクロコンピュータ、メモリなどの集積回路素子を内
蔵したＩＣカードが実用化されつつある。IC cards containing integrated circuit elements such as microcomputers and memories are being put into practical use.

このＩＣカードは、塩化ビニル等のプラスチックカード
に、リーダー・ライター等の外部機器との接続のための
端子を有する半導体集積回路装置が埋設される構成であ
シ、この半導体集積回路装置は、プラスチックカードの
厚み以下の極めて薄型に構成することが必要とされる。This IC card has a structure in which a semiconductor integrated circuit device having terminals for connection with external equipment such as a reader/writer is embedded in a plastic card such as vinyl chloride. It is required to have an extremely thin structure that is less than the thickness of the card.

このため、従来の半導体集積回路装置は、第３図に示す
ように、フィルム状の絶縁基板１１に、外部接続用の端
子ハタ−フッ０１回路パターン９及びスルーホール８等
の配線導体を形成した薄型配線基板に、集積回路素子１
４を接着剤１３によりダイスボンディングし、集積回路
素子１４の入出力電極と回路パターン９とをワイヤポン
ディング方式等によシ金属線１５で接続する。また、樹
脂封止の際に、樹脂流れを防止するために封止枠１２を
絶縁基板１１に接着して設け、エポキシ樹脂等の封止材
１６によシ各部材を封止して得られる（参照：特開昭５
５−５６６４７号公報、特開昭５８−９２５９７号公報
）。For this reason, in the conventional semiconductor integrated circuit device, as shown in FIG. 3, wiring conductors such as a terminal foot 01 circuit pattern 9 and a through hole 8 for external connection are formed on a film-like insulating substrate 11. Integrated circuit element 1 on a thin wiring board
4 is dice-bonded using an adhesive 13, and the input/output electrodes of the integrated circuit element 14 and the circuit pattern 9 are connected with a metal wire 15 by a wire bonding method or the like. Further, during resin sealing, a sealing frame 12 is provided by adhering to the insulating substrate 11 to prevent resin flow, and each member is sealed with a sealing material 16 such as epoxy resin. (Reference: Japanese Patent Publication No. 5
5-56647, JP-A-58-92597).

発明が解決しようとする問題点 Ｉ（ｉカードに搭載される半導体集積回路装置において
は、薄型化と同時に、高寸法精度でかつ低コストである
ことが求められている。しかしながら、前述したような
集積回路装置においては、用いられる配線基板が、絶縁
基板１１０両面に配線導体を形成し、スルーホール８に
よって接続したスルーホール付両面配線基板であるので
次のような問題点を有している。（１）配線基板が高価
である。Problem to be Solved by the Invention I (Semiconductor integrated circuit devices mounted on i-cards are required to be thin, have high dimensional accuracy, and be low in cost. However, the above-mentioned problems In the integrated circuit device, the wiring board used is a double-sided wiring board with through holes, in which wiring conductors are formed on both sides of an insulating substrate 110 and connected by through holes 8, so that the following problems occur. (1) The wiring board is expensive.

（巧スルーホール形成はめっきにより行うので、この時
のめっき厚のバラツキが配線基板の総厚のバラツキとな
り、良好な厚み寸法精度が得にくい。(Since through-hole formation is performed by plating, variations in the plating thickness at this time result in variations in the total thickness of the wiring board, making it difficult to obtain good thickness dimensional accuracy.

（３）集積回路素子１４の樹脂封止の時、樹脂がスルー
ホールより流出するので、流出防止のためにスルーホー
ルを封口する手段が必要である。(3) When the integrated circuit element 14 is sealed with resin, the resin flows out from the through hole, so a means for sealing the through hole is required to prevent the resin from flowing out.

本発明は、上記問題点に鑑みてなされたもので、高寸法
精度でかつ高能率に製造でき、しかも安価な半導体集積
回路装置を提供するものである。The present invention has been made in view of the above problems, and it is an object of the present invention to provide a semiconductor integrated circuit device that can be manufactured with high dimensional accuracy and high efficiency, and is inexpensive.

問題点を解決するための手段 この目的を達成するために、本発明は所定のパターンに
加工した、リードフレームの一方の面を外部機器との接
続のための端子面、他方の面を集積回路素子の固定面と
し、リードフレームの固定面側に、集積回路素子の近傍
、あるいは、集積回路素子と端子面とをワイヤポンディ
ング方式等によシ結線する金属線の接合部の近傍に、微
小溝を形成、上記リードフレームと集積回路素子とを接
着、固定して、端子面を除いて、上記の各部材をエポキ
シ樹脂等で封止した構成の半導体集積回路装置としてい
る。Means for Solving the Problems In order to achieve this object, the present invention has a lead frame processed into a predetermined pattern, one side of which is a terminal surface for connection with external equipment, and the other side is a terminal surface for connection with an external device. The fixed surface of the lead frame, which serves as the fixed surface of the element, is placed near the integrated circuit element, or near the joint of the metal wire that connects the integrated circuit element and the terminal surface by the wire bonding method, etc. A semiconductor integrated circuit device has a structure in which a groove is formed, the lead frame and the integrated circuit element are bonded and fixed, and each of the above members except the terminal surface is sealed with epoxy resin or the like.

−作用 このような構成にすれば、集積回路素子とリードフレー
ムを接着、固定する時に、一定の厚みの接着層が形成さ
れた後、不要な接着剤は微小溝に吸収され、この溝の外
側には流出することがない。- Effect With this configuration, when an integrated circuit element and a lead frame are bonded and fixed, after an adhesive layer of a certain thickness is formed, unnecessary adhesive is absorbed into the micro grooves, and the adhesive is removed from the outside of the grooves. There will be no leakage.

従って、接着剤がリードフレームの端子面側に流出する
ことがなく、外部機器との良好な接続が可能となる。ま
た、リードフレームの金属線の接合部にも接着剤が流出
せず、この接合部と集積回路素子とが良好に結線される
。このようにリードフレームに微小溝を形成することに
よって、初めて本発明の半導体集積回路装置を具現化す
ることができる。Therefore, the adhesive does not flow out to the terminal surface side of the lead frame, allowing good connection with external equipment. Moreover, the adhesive does not flow out to the joint of the metal wires of the lead frame, and the joint and the integrated circuit element are well connected. By forming microgrooves in the lead frame in this manner, the semiconductor integrated circuit device of the present invention can be realized for the first time.

実施例 第１図に本発明の半導体集積回路装置の一実施例として
、その断面図を示す。第１図において、１は金属材料か
らなるリードフレーム、２はリードフレーム１に形成し
た微小溝、３はリードフレーム１と集積回路素子とを接
着、固定する接着剤、４は集積回路素子、５は金属線、
６は封止樹脂である。外部機器との接続のため所定の端
子パターンに加工したリードフレーム１の一方の面に、
金属線６の接合部の近傍で、微小溝２を形成、集積回路
素子４を接着剤３を介して接着、固定し、金属線６によ
シリードフレーム１と結線して、上記の各部材を、リー
ドフレーム１の他方の面を露出して、封止樹脂６で封止
した構成としている。Embodiment FIG. 1 shows a sectional view of an embodiment of the semiconductor integrated circuit device of the present invention. In FIG. 1, 1 is a lead frame made of a metal material, 2 is a micro groove formed in the lead frame 1, 3 is an adhesive for bonding and fixing the lead frame 1 and an integrated circuit element, 4 is an integrated circuit element, and 5 is an adhesive. is metal wire,
6 is a sealing resin. On one side of the lead frame 1 processed into a predetermined terminal pattern for connection with external equipment,
A micro groove 2 is formed near the joint of the metal wire 6, the integrated circuit element 4 is bonded and fixed via the adhesive 3, and the metal wire 6 is connected to the series lead frame 1 to connect each of the above members. The other surface of the lead frame 1 is exposed and sealed with a sealing resin 6.

また、第２図に別の実施例として、本発明の半導体集積
回路装置の断面図を示す。第２図の各番号は第１図に示
すものと同じである。この場合。Further, FIG. 2 shows a cross-sectional view of a semiconductor integrated circuit device of the present invention as another embodiment. Each number in FIG. 2 is the same as that shown in FIG. in this case.

集積回路素子４の近傍で、リードフレーム１に微小溝２
を形成した構成であシ、この微小溝２は、集積回路素子
４の裏面に形成しても良い。A micro groove 2 is formed in the lead frame 1 near the integrated circuit element 4.
However, the micro grooves 2 may be formed on the back surface of the integrated circuit element 4.

さらに、このような微小溝２は、リードフレーム１の金
属線５の接合部の近傍（第１図）と同時に、集積回路素
子４の近傍（第２図）に形成する構造であっても良い。Further, such micro grooves 2 may be formed in the vicinity of the joints of the metal wires 5 of the lead frame 1 (FIG. 1) and at the same time in the vicinity of the integrated circuit elements 4 (FIG. 2). .

このような構成にすれば、いずれの場合も、接着剤３の
不要に量は微小溝２に吸収されて、リードフレーム１の
端子面に露出したり、金属線５の接合部に流出したシす
ることがない。With such a configuration, in any case, the unnecessary amount of adhesive 3 will be absorbed by the minute grooves 2, and the adhesive 3 will be exposed to the terminal surface of the lead frame 1 or leaked to the joint of the metal wire 5. There's nothing to do.

発明の効果 以上のように、本発明の構成は、集積回路素子とリード
フレームを接着、固定する接着剤を不要な部分、即ち、
外部機器との接続のための端子面やワイヤポンド方式等
による金属線の接合部等に流出させることがなく、良好
な電気的接続を可能にするものである。このことによシ
初めて、安価なリードフレームを使用し、しかも、一般
に知られている樹脂成形法を本発明の半導体集積回路装
置に適用することができる。従って、本発明はその材料
費が低減し、また、その製造能率及び寸法精度が向上す
るという工業価値の高い効果をもたらすものである。む
ろん、ＩＣカード等に本発明の半導体集積回路装置を使
用すれば、ＩＣカード自身の価格を低減し、その寸法精
度を向上できることは言うまでもない。Effects of the Invention As described above, the configuration of the present invention eliminates the need for adhesive for adhering and fixing the integrated circuit element and the lead frame to the unnecessary portions, that is,
This enables a good electrical connection without leaking to the terminal surface for connection with external equipment or the joints of metal wires using the wire pond method or the like. This makes it possible to use an inexpensive lead frame and to apply a generally known resin molding method to the semiconductor integrated circuit device of the present invention. Therefore, the present invention brings about effects of high industrial value in that the material cost is reduced and the manufacturing efficiency and dimensional accuracy are improved. Of course, if the semiconductor integrated circuit device of the present invention is used in an IC card or the like, it goes without saying that the price of the IC card itself can be reduced and its dimensional accuracy can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例を示す半導体集積回路装置の
断面図、第２図は本発明の別の実施例を示す半導体集積
回路装置の断面図、第３図は従来例の半導体集積回路装
置の断面図である。 １・・・・・・リードフレーム、２・・・・・・微小溝
、３・・・・・・接着剤、４・・・・・・集積回路素子
、５・・・・・・金属線、６・・・・・・封止樹脂。 代理人の氏名　弁理士　中　尾　敏　男　ほか１名１−
−−　ソード７しｉム Ｃ−−＃　　　　庸 第２図 第　３　図 １σ　　　ＩＩ　　１０　　　ゾ　θFIG. 1 is a sectional view of a semiconductor integrated circuit device showing one embodiment of the present invention, FIG. 2 is a sectional view of a semiconductor integrated circuit device showing another embodiment of the invention, and FIG. 3 is a sectional view of a conventional semiconductor integrated circuit device. FIG. 3 is a cross-sectional view of the circuit device. DESCRIPTION OF SYMBOLS 1...Lead frame, 2...Minute groove, 3...Adhesive, 4...Integrated circuit element, 5...Metal wire , 6...Sealing resin. Name of agent: Patent attorney Toshio Nakao and 1 other person1-
--Sword 7 Sim C--# Yen Figure 2 Figure 3 Figure 1 σ II 10 Zo θ

Claims (1)

【特許請求の範囲】[Claims] 　リードフレームの一方の面を外部機器との接続のため
の端子面、他方の面を集積回路素子の固定面とし、上記
リードフレームの固定面側に、集積回路素子の近傍、あ
るいは、集積回路素子と端子面とを結線する金属線の接
合部の近傍に、微小溝を形成し、上記リードフレームと
集積回路素子とを接着、固定して、端子面を除いて、上
記各部材を封止樹脂で封止した半導体集積回路装置。One surface of the lead frame is used as a terminal surface for connection with external equipment, and the other surface is used as a fixing surface for the integrated circuit element. A micro groove is formed near the joint of the metal wire that connects the lead frame and the terminal surface, and the lead frame and the integrated circuit element are bonded and fixed, and each of the above components is sealed with resin except for the terminal surface. A semiconductor integrated circuit device sealed with
JP62263433A 1987-10-19 1987-10-19 Semiconductor integration circuit device Pending JPH01106455A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62263433A JPH01106455A (en) 1987-10-19 1987-10-19 Semiconductor integration circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62263433A JPH01106455A (en) 1987-10-19 1987-10-19 Semiconductor integration circuit device

Publications (1)

Publication Number Publication Date
JPH01106455A true JPH01106455A (en) 1989-04-24

Family

ID=17389436

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62263433A Pending JPH01106455A (en) 1987-10-19 1987-10-19 Semiconductor integration circuit device

Country Status (1)

Country Link
JP (1) JPH01106455A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0712159A2 (en) * 1994-11-08 1996-05-15 Oki Electric Industry Co., Ltd. Structure of resin molded type semiconductor
US5543363A (en) * 1992-04-28 1996-08-06 Mitsubishi Denki Kabushiki Kaisha Process for adhesively attaching a semiconductor device to an electrode plate
JPH1154551A (en) * 1997-08-04 1999-02-26 Matsushita Electron Corp Resin-sealed semiconductor device and method of manufacturing the same
WO1999000826A3 (en) * 1997-06-27 1999-05-27 Matsushita Electronics Corp Resin molded type semiconductor device and a method of manufacturing the same
EP1032037A3 (en) * 1999-02-24 2001-04-25 Matsushita Electronics Corporation Resin-moulded semiconductor device, method for manufacturing the same, and leadframe
US6831372B2 (en) * 2001-09-28 2004-12-14 Infineon Technologies Ag Electronic devices with semiconductor chips and a leadframe with device positions and methods for producing the same
US6861735B2 (en) 1997-06-27 2005-03-01 Matsushita Electric Industrial Co., Ltd. Resin molded type semiconductor device and a method of manufacturing the same
IT202200022416A1 (en) * 2022-11-02 2024-05-02 St Microelectronics Srl Process for manufacturing semiconductor devices and corresponding semiconductor device

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5543363A (en) * 1992-04-28 1996-08-06 Mitsubishi Denki Kabushiki Kaisha Process for adhesively attaching a semiconductor device to an electrode plate
EP0712159A2 (en) * 1994-11-08 1996-05-15 Oki Electric Industry Co., Ltd. Structure of resin molded type semiconductor
US6861735B2 (en) 1997-06-27 2005-03-01 Matsushita Electric Industrial Co., Ltd. Resin molded type semiconductor device and a method of manufacturing the same
WO1999000826A3 (en) * 1997-06-27 1999-05-27 Matsushita Electronics Corp Resin molded type semiconductor device and a method of manufacturing the same
KR100397539B1 (en) * 1997-06-27 2003-09-13 마츠시타 덴끼 산교 가부시키가이샤 Resin molded type semiconductor device and a method of manufacturing the same
US6900524B1 (en) 1997-06-27 2005-05-31 Matsushita Electric Industrial Co., Ltd. Resin molded semiconductor device on a lead frame and method of manufacturing the same
CN100423253C (en) * 1997-06-27 2008-10-01 松下电器产业株式会社 Resin-sealed semiconductor device and method for manufacturing the same
US7538416B2 (en) 1997-06-27 2009-05-26 Panasonic Corporation Resin molded type semiconductor device and a method of manufacturing the same
JPH1154551A (en) * 1997-08-04 1999-02-26 Matsushita Electron Corp Resin-sealed semiconductor device and method of manufacturing the same
EP1032037A3 (en) * 1999-02-24 2001-04-25 Matsushita Electronics Corporation Resin-moulded semiconductor device, method for manufacturing the same, and leadframe
EP1335428A3 (en) * 1999-02-24 2003-10-08 Matsushita Electric Industrial Co., Ltd. Resin-moulded semiconductor device and method for manufacturing the same
EP1335427A3 (en) * 1999-02-24 2003-10-08 Matsushita Electric Industrial Co., Ltd. Resin-moulded semiconductor device
US6831372B2 (en) * 2001-09-28 2004-12-14 Infineon Technologies Ag Electronic devices with semiconductor chips and a leadframe with device positions and methods for producing the same
IT202200022416A1 (en) * 2022-11-02 2024-05-02 St Microelectronics Srl Process for manufacturing semiconductor devices and corresponding semiconductor device

Similar Documents

Publication Publication Date Title
KR100280170B1 (en) Substrate for semiconductor device and manufacturing method thereof, semiconductor device, card type module and information storage device
US4539472A (en) Data processing card system and method of forming same
US4910582A (en) Semiconductor device and method of manufacturing thereof
JPH01106455A (en) Semiconductor integration circuit device
JPS58138057A (en) Integrated circuit card
JPH10199930A (en) Connection structure and connection method for electronic components
JPH05151424A (en) Integrated circuit token
JPH0262297A (en) Integrated circuit device and ic card using same
JPH01208847A (en) Integrated circuit device
JP2001344587A (en) Printed wiring board, IC card module using the same, and method of manufacturing the same
EP0212020B1 (en) Data processing card system and method of forming same
JP3351711B2 (en) Semiconductor device substrate and method of manufacturing the same, and semiconductor device, card type module, and information storage device
JP3485736B2 (en) Semiconductor device and manufacturing method thereof
JPH05275838A (en) Modules for electronic devices
USRE35385E (en) Method for fixing an electronic component and its contacts to a support
JPS6283196A (en) IC card
JP2661101B2 (en) IC card
JPH01210393A (en) Integrated circuit device
JPH01210394A (en) Integrated circuit device
JPH0262294A (en) Integrated circuit device and ic card using same
JPH0276798A (en) Manufacture of integrated circuit device
JPH0262065A (en) Integrated circuit device and ic card using same
JPS60142488A (en) Ic card
JPH0268983A (en) Semiconductor device
JPS63209897A (en) Memory card