JPH01106943U - - Google Patents
Info
- Publication number
- JPH01106943U JPH01106943U JP117788U JP117788U JPH01106943U JP H01106943 U JPH01106943 U JP H01106943U JP 117788 U JP117788 U JP 117788U JP 117788 U JP117788 U JP 117788U JP H01106943 U JPH01106943 U JP H01106943U
- Authority
- JP
- Japan
- Prior art keywords
- address
- signal
- program
- address signal
- port
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004590 computer program Methods 0.000 claims description 4
- 238000001514 detection method Methods 0.000 claims 1
- 230000004044 response Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
Landscapes
- Tests Of Electronic Circuits (AREA)
- Debugging And Monitoring (AREA)
Description
第１図はこの考案に係るコンピユータプログラ
ムトレース装置の一実施例を示すブロツク図、第
２図は同実施例におけるアドレスマツプ、第３図
はＩＯポートアドレスとメモリアドレス領域の一
部とが重複するタイプのＭＰＵのアドレスマツプ
、である。
１０……コンピユータプログラムトレース装置
、１１，１２……レジスタ、１３……デコーダ、
１４……記憶及び評価部、２０……被測定コンピ
ユータ装置、３０……ライン。
Fig. 1 is a block diagram showing an embodiment of a computer program tracing device according to this invention, Fig. 2 is an address map in the same embodiment, and Fig. 3 shows an overlap between an IO port address and a part of the memory address area. The address map of the type MPU is . 10... Computer program tracing device, 11, 12... Register, 13... Decoder,
14... Storage and evaluation unit, 20... Computer device to be measured, 30... Line.
Claims (1)
ドレスであるＩＯポートアドレスのアドレス信号
割当てがメモリアドレス領域の一部のアドレス信
号割当てに重複している被測定コンピユータ装置
において、実行中のプログラムの通過アドレス情
報を記録するためのコンピユータプログラムトレ
ース装置であつて、 前記被測定コンピユータ装置における実行中の
プログラムのアドレス信号を取り込む第１の取り
込み手段と、 前記被測定コンピユータ装置から実行中のプロ
グラムに対応して出力されるステイタス信号を取
り込む第２の取り込み手段と、 前記第２の取り込み手段から与えられるステイ
タス信号に基づき前記被測定コンピユータ装置が
前記ＩＯポートアドレスをアクセス中であること
を示す信号を出力する検出手段と、 前記検出手段から与えられる信号に基づき該Ｉ
Ｏポートアドレスのアドレス信号が前記メモリア
ドレス領域のアドレス信号に重複しないように前
記第１の取り込み手段から出力されるアドレス信
号を修正する手段と を具え、修正されたアドレス信号を記録するこ
とにより前記ＩＯポートアドレスと前記メモリア
ドレス領域のアドレス情報を区別して記録するよ
うにしたことを特徴とするコンピユータプログラ
ムトレース装置。[Claim for Utility Model Registration] In a computer device under test where the address signal assignment of an IO port address, which is a dedicated address for accessing an external input/output device, overlaps with the address signal assignment of a part of the memory address area. , a computer program tracing device for recording passage address information of a program being executed, comprising: a first capturing means for capturing an address signal of a program being executed in the computer device under test; a second capture unit that captures a status signal output in response to a program being executed; and the computer device under test is accessing the IO port address based on the status signal provided from the second capture unit. a detection means for outputting a signal indicating that the I
and means for modifying the address signal output from the first capturing means so that the address signal of the O port address does not overlap with the address signal of the memory address area, and recording the modified address signal. A computer program tracing device characterized in that an IO port address and address information of the memory address area are recorded separately.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP117788U JPH01106943U (en) | 1988-01-11 | 1988-01-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP117788U JPH01106943U (en) | 1988-01-11 | 1988-01-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01106943U true JPH01106943U (en) | 1989-07-19 |
Family
ID=31200840
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP117788U Pending JPH01106943U (en) | 1988-01-11 | 1988-01-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01106943U (en) |
-
1988
- 1988-01-11 JP JP117788U patent/JPH01106943U/ja active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH01106943U (en) | ||
| JPH01102936U (en) | ||
| JPS60640U (en) | Parallel processing system for DMA processing and program measurement mode | |
| JPS59180300U (en) | memory test equipment | |
| JPH01102935U (en) | ||
| JPS59182757U (en) | Microcomputer malfunction analysis circuit | |
| JPH0326416B2 (en) | ||
| JPS59138961U (en) | Trace memory control circuit | |
| JPH0227229U (en) | ||
| JPS617000U (en) | Built-in memory LSI | |
| JPS59135412U (en) | Car remaining mileage display device | |
| JPS5894036U (en) | Microcomputer abnormality warning device | |
| JPH02123631U (en) | ||
| JPH04120644A (en) | Storage device | |
| JPH026344U (en) | ||
| JPS5888487U (en) | Input circuit for remote monitoring and control equipment | |
| JPS61143251U (en) | ||
| JPH0239366U (en) | ||
| JPS58186439U (en) | Engine failure diagnosis device | |
| JPS6262214U (en) | ||
| JPH0221567U (en) | ||
| JPS6358360U (en) | ||
| JPH01120254U (en) | ||
| JPH0382440U (en) | ||
| JPS6020019U (en) | Floppy disk inspection device |