JPH01106949U - - Google Patents
Info
- Publication number
- JPH01106949U JPH01106949U JP19924387U JP19924387U JPH01106949U JP H01106949 U JPH01106949 U JP H01106949U JP 19924387 U JP19924387 U JP 19924387U JP 19924387 U JP19924387 U JP 19924387U JP H01106949 U JPH01106949 U JP H01106949U
- Authority
- JP
- Japan
- Prior art keywords
- dual port
- serial bus
- memory
- memories
- utility
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000009977 dual effect Effects 0.000 claims description 6
- 230000015654 memory Effects 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 2
Description
第１図は本考案の実施例を示すブロツク線図、
第２図は従来例を示すブロツク線図である。
６はＣＰＵ、７はＣＰＵバス、８はシリアルバ
ス、９，１０，１１はデユアルポートメモリであ
る。
FIG. 1 is a block diagram showing an embodiment of the present invention;
FIG. 2 is a block diagram showing a conventional example. 6 is a CPU, 7 is a CPU bus, 8 is a serial bus, and 9, 10, and 11 are dual port memories.
Claims (1)
ートが共通のシリアルバスに接続されて成り、 上記複数のデユアルポートメモリの内の一のデ
ユアルポートメモリのデータが、上記シリアルバ
スを通じて他のデユアルポートメモリに転送され
るようにして成るメモリ装置。[Claims for Utility Model Registration] A utility model comprising a plurality of dual port memories, each serial port of the plurality of dual port memories is connected to a common serial bus, and one dual port of the plurality of dual port memories is connected to a common serial bus. A memory device in which data in the memory is transferred to another dual port memory through the serial bus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19924387U JPH01106949U (en) | 1987-12-29 | 1987-12-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19924387U JPH01106949U (en) | 1987-12-29 | 1987-12-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01106949U true JPH01106949U (en) | 1989-07-19 |
Family
ID=31489704
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19924387U Pending JPH01106949U (en) | 1987-12-29 | 1987-12-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01106949U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5619102A (en) * | 1979-07-24 | 1981-02-23 | Toshiba Corp | Computer system for process control |
| JPS6298430A (en) * | 1985-10-24 | 1987-05-07 | Nec Corp | Microprocessor |
-
1987
- 1987-12-29 JP JP19924387U patent/JPH01106949U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5619102A (en) * | 1979-07-24 | 1981-02-23 | Toshiba Corp | Computer system for process control |
| JPS6298430A (en) * | 1985-10-24 | 1987-05-07 | Nec Corp | Microprocessor |
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