JPH01108716A - Laminated ceramic capacitor - Google Patents

Laminated ceramic capacitor

Info

Publication number
JPH01108716A
JPH01108716A JP62267300A JP26730087A JPH01108716A JP H01108716 A JPH01108716 A JP H01108716A JP 62267300 A JP62267300 A JP 62267300A JP 26730087 A JP26730087 A JP 26730087A JP H01108716 A JPH01108716 A JP H01108716A
Authority
JP
Japan
Prior art keywords
ceramic
capacitor
materials
ceramic layer
ceramic capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62267300A
Other languages
Japanese (ja)
Other versions
JPH0515294B2 (en
Inventor
Susumu Saito
晋 齊藤
Kazuaki Uchiumi
和明 内海
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62267300A priority Critical patent/JPH01108716A/en
Publication of JPH01108716A publication Critical patent/JPH01108716A/en
Publication of JPH0515294B2 publication Critical patent/JPH0515294B2/ja
Granted legal-status Critical Current

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  • Ceramic Capacitors (AREA)

Abstract

PURPOSE:To obtain a capacitor of high dielectric constant having a small temperature coefficient and excellent electric characteristics by a method wherein a ceramic layer of specific thickness is interposed between high permeability materials using a plurality of high dielectric constant materials having different Curie points. CONSTITUTION:On a laminated ceramic capacitor, ceramic dielectric layers having different Curie points are formed at least using two kinds of porcelain composition materials, and a porcelain composition material of 3-30mum and a ceramic layer, which is hardly formed into a solid solution, are formed between a plurality of ceramic dielectric layers. The diffuse reaction generating in a sintering process can be prevented by interposing a ceramic layer of 3-10mum between the porcelain composition materials having different Curie points. As a result, the capacitor can be brought into a composite without changing the Curie point of each material, and by combiningly laminating the material having optical Curie point, the capacitor having a high permeability and a small temperature coefficient of capacitance with temperature can be accomplished.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、積層セラミック・コンデンサに関し、特に誘
電率の温度変化が少なく、かつ高誘電率のコンデンサに
関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multilayer ceramic capacitor, and particularly to a capacitor having a high dielectric constant and a small change in dielectric constant due to temperature.

〔従来の技術〕[Conventional technology]

電子部品の基板上への実装密度が高まるにつれ、コンデ
ンサ等の電子部品のチップ化が盛んになってきているが
、コンデンサチップ市場では温度特性変化の小さなX7
R特性が大半を占めている。従来の高誘電率磁器組成物
材料としてはチタン酸バリウム(BaTiO3)系が知
られており、添加や置換によってキュリー点を移動させ
て温度特性改善をはかっている。
As the mounting density of electronic components on substrates increases, the use of chips for electronic components such as capacitors has become popular, but in the capacitor chip market,
The R characteristic occupies the majority. Barium titanate (BaTiO3) is known as a conventional high dielectric constant ceramic composition material, and its Curie point is moved by addition or substitution to improve temperature characteristics.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

この従来の方法により、X7R特性を実現した場合、得
られる誘電率は高々2000程度に過ぎず、チップの軽
薄短小化の要求に適合しなかった。これを解決する手段
として、キュリー点が異なった高い誘電率を持つ磁器組
成物材料を組み合わせ、温度特性の優れた大容量コンデ
ンサを実現する製造方法が提案されたが、実際には組合
わせた異種磁器組成物材料間に拡散反応が起こりキュリ
ー点が一つとなり温度特性改善効果はあまり望めなかっ
た。
When X7R characteristics were achieved using this conventional method, the dielectric constant obtained was only about 2000 at most, which did not meet the requirements for making chips lighter, thinner, shorter and smaller. As a means to solve this problem, a manufacturing method has been proposed in which a large capacity capacitor with excellent temperature characteristics is created by combining ceramic composition materials with different Curie points and high dielectric constants. Diffusion reactions occurred between the materials of the ceramic composition, resulting in a single Curie point, and no significant improvement in temperature characteristics could be expected.

本発明の目的は、上述の要請に鑑み、誘電率が高く、か
つ温度変化率の小さい優れた電気特性を有することので
きる積層セラミック・コンデンサを提供することにある
In view of the above requirements, an object of the present invention is to provide a multilayer ceramic capacitor that has a high dielectric constant and excellent electrical characteristics with a small rate of temperature change.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の積層セラミック・コンデンサは、セラミック誘
電体層と内部電極が交互に積層して成る積層セラミック
・コンデンサにおいて、前記セラミック誘電体層がキュ
リー点の異る少くとも二種項の磁器組成物材料で形成さ
れ、かつ、複数の前記セラミック誘電体層°の間に3乃
至30μmの前記磁器組成物材料と固溶しにくいセラミ
ック層が形成されている。
The multilayer ceramic capacitor of the present invention is a multilayer ceramic capacitor in which ceramic dielectric layers and internal electrodes are alternately laminated, wherein the ceramic dielectric layers are made of at least two types of ceramic composition materials having different Curie points. A ceramic layer having a thickness of 3 to 30 μm that is difficult to form a solid solution with the ceramic composition material is formed between the plurality of ceramic dielectric layers.

〔作用〕[Effect]

キュリー点の異なる磁器組成物材料間に3乃至10μm
のセラミック層を介在させることにより、焼結過程にお
ける拡散反応を防止できる。そのため個々の材料のキュ
リー点を変えることなく複合化でき、任意のキュリー点
°を待った材料を組み合わせ積層することにより、誘電
率が高く、かつ、温度による容量変化の小さなコンデン
サを実現できる。
3 to 10 μm between porcelain composition materials with different Curie points
By interposing the ceramic layer, diffusion reactions during the sintering process can be prevented. Therefore, it is possible to combine individual materials without changing their Curie points, and by combining and laminating materials with arbitrary Curie points, it is possible to create capacitors with a high dielectric constant and a small change in capacitance due to temperature.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図(a)、(b)は本発明の積層セラミック・コン
デンサチップの内部電極の積層構造の第1の実施例を示
す斜視図及び積層セラミック・コデンサの斜視図、第2
図(a)、(b)は本実施例の内部電極及びセラミック
層形成材料をセラミックグリーンシートに被着したとき
の断面図、第3図(a)、(b)は本実施例の積層構造
を説明するための斜視図及び断面図、第4図は本実施例
の積層セラミック・コンデンサと従来の積層セラミック
・コンデンサの温度による容量変化率を示す特性図、第
5図は本発明の積層セラミック・コンデンサチップの内
部電極の積層構造の第2の実施例を示す斜視図である。
FIGS. 1(a) and 1(b) are a perspective view showing a first embodiment of the multilayer structure of the internal electrode of the multilayer ceramic capacitor chip of the present invention, a perspective view of the multilayer ceramic capacitor, and a second embodiment of the multilayer ceramic capacitor chip.
Figures (a) and (b) are cross-sectional views when the internal electrode and ceramic layer forming material of this example are adhered to a ceramic green sheet, and Figures 3 (a) and (b) are the laminated structure of this example. FIG. 4 is a characteristic diagram showing the rate of change in capacitance due to temperature of the multilayer ceramic capacitor of this embodiment and a conventional multilayer ceramic capacitor, and FIG. 5 is a perspective view and a cross-sectional view for explaining the multilayer ceramic capacitor of the present invention. - It is a perspective view showing a second example of a laminated structure of internal electrodes of a capacitor chip.

以下、実施例に従って本発明の詳細な説明を行う。マグ
ネシウム・タングステン酸鉛Pb(M g 1/2 W
l/2 ) O3とチタン酸鉛PbTi0□を所定のキ
ュリー点が得られるように所定の割合で混合した組成物
材料を複数用いて積層セラミック・コンデンサを製作し
た。
Hereinafter, the present invention will be explained in detail according to Examples. Magnesium lead tungstate Pb (M g 1/2 W
A multilayer ceramic capacitor was manufactured using a plurality of composition materials in which O3 and lead titanate (PbTi0□) were mixed at a predetermined ratio so as to obtain a predetermined Curie point.

第1の実施例は2種類の磁器組成物材料をセラミック層
を介して組合せた例である。
The first example is an example in which two types of ceramic composition materials are combined via a ceramic layer.

各組成物材料の予焼粉末と有機バインダー、有機溶媒と
を混合し、泥漿を作製した。この泥漿をドクターブレー
ド法でフィルム上に数10μmの厚さにキャスティング
しグリーンシートを作製した。このシートを乾燥し、フ
ィルムから剥離し、所定の形状に切断した後、第2図(
a)の如く銀・パラジウムペーストを片面に印刷した。
Prefired powder of each composition material, an organic binder, and an organic solvent were mixed to prepare a slurry. This slurry was cast onto a film to a thickness of several tens of micrometers using a doctor blade method to produce a green sheet. After drying this sheet, peeling it off from the film and cutting it into a predetermined shape, the sheet is shown in Figure 2 (
Silver/palladium paste was printed on one side as in a).

またセラミック層を形成するために、第2図(b)の如
く所定のセラミック層形成材料13をグリーンシート上
にスクリーン印刷法によって10μmの厚さに印刷した
。セラミック層形成材料はジルコニアの粉末を有機ビヒ
クルを混合したペーストを用いて印刷した。
In order to form a ceramic layer, a predetermined ceramic layer forming material 13 was printed on a green sheet to a thickness of 10 μm by screen printing as shown in FIG. 2(b). The ceramic layer forming material was printed using a paste containing zirconia powder mixed with an organic vehicle.

これらのシートを第3図(a)に示すように、保護層用
シート4a、電極形成用シート4b、セラミック層形成
材料用シート4c、4aとは異なる材料の電極形成用シ
ート5b、4aとは異なる材料の保護層用シー)5aの
順に所定の組合せに従って数10枚積層、圧着し、積層
体の断面を示す第3図(b)の切断位置6で所定の形状
に切断し、空気中にて950℃で焼成して第1図(a)
に示すような磁器組成物材料と反応しにくいセラミック
層のある積層セラミック・コンデンサチップを得た0次
に、外部電極を形成し、第1図(b)に示す積層セラミ
ック・コンデンサを得た。
As shown in FIG. 3(a), these sheets are a protective layer sheet 4a, an electrode forming sheet 4b, a ceramic layer forming material sheet 4c, and an electrode forming sheet 5b made of a material different from 4a. Several dozen sheets of protective layer sheet) 5a made of different materials are stacked and crimped according to a predetermined combination, cut into a predetermined shape at cutting position 6 in FIG. 3(b) showing the cross section of the laminate, and placed in air. Figure 1(a)
A multilayer ceramic capacitor chip having a ceramic layer that does not easily react with the ceramic composition material as shown in FIG. 1 was obtained. Next, external electrodes were formed to obtain a multilayer ceramic capacitor shown in FIG.

第4図は従来構造を用い異種磁器組成物材料を組合せた
積層コンデンサチップと本実施例の異種磁器組成物材料
を組合せた積層コンデンサチップの容量の温度変化率の
特性線C,Bを示した。また参考として各磁器組成物材
料単独の従来の構造のコンデンサチップの容量の温度変
化率の特性A、Dも示した。従来の構造によるコンデン
サは、組合せた組成1料間に拡散反応が起こり、単一組
成物となりキュリー点が−っになってしまっているのに
対し、本発明の構造によるものは、組合せた組成物材料
間で拡散反応が起こらないため各材料の特性によりコン
デンサチップの温度特性が改善されていることがわかる
Figure 4 shows characteristic lines C and B of the temperature change rate of capacitance of a multilayer capacitor chip with a conventional structure and a combination of different types of ceramic composition materials and a multilayer capacitor chip with a combination of different types of ceramic composition materials of this example. . For reference, characteristics A and D of the temperature change rate of capacitance of a capacitor chip of a conventional structure made of each ceramic composition material alone are also shown. In capacitors with the conventional structure, a diffusion reaction occurs between the combined compositions, resulting in a single composition with a Curie point of -, whereas in the capacitor with the structure of the present invention, the Curie point is - - It can be seen that the temperature characteristics of the capacitor chip are improved due to the characteristics of each material because no diffusion reaction occurs between the materials.

第5図は本発明の第2の実施例の4種類の磁器組成物材
料を磁器組成物材料と反応しにくいセラミック層を介し
て組合せた場合の斜視図である。
FIG. 5 is a perspective view of a second embodiment of the present invention in which four types of porcelain composition materials are combined via a ceramic layer that does not easily react with the porcelain composition material.

第1の実施例と同じ方法で異る4種類の電極形成セラミ
ックグリーンシートの間にセラミック層形成材料13を
被着させたセラミックグリーンシートを挟み、交互に積
層、圧着し、所定の形状に切断し、焼成して第5図に示
すような異種磁器組成物材料間にセラミック層を挟んだ
4層構造の積層セラミック・コンデンサチップを得た。
Ceramic green sheets coated with ceramic layer forming material 13 are sandwiched between four different types of electrode-forming ceramic green sheets using the same method as in the first embodiment, alternately laminated and crimped, and cut into a predetermined shape. Then, by firing, a multilayer ceramic capacitor chip having a four-layer structure in which a ceramic layer was sandwiched between different types of ceramic composition materials as shown in FIG. 5 was obtained.

この第2の実施例においても、第1の実施例と同様な効
果を得ることが出来る。
In this second embodiment as well, the same effects as in the first embodiment can be obtained.

また、本発明の実施例には誘電体材料と反応しにくいジ
ルコニアを用いたが、アルミナや窒化アルミニウムを用
いても同様の効果が得られる。
Furthermore, although zirconia, which does not easily react with dielectric materials, was used in the embodiments of the present invention, similar effects can be obtained by using alumina or aluminum nitride.

〔発明の効果〕〔Effect of the invention〕

第4図に示した例からも明らかなように、本発明の積層
セラミック・コンデンサは、キュリー点の異なる複数の
高誘電率−材料を用い、前記高誘電率材料間に3乃至3
0μmのセラミック層を介在させることによって温度特
性にすぐれ、かつ、小さな形状で高静電容量を簡単に実
現できる効果がある。
As is clear from the example shown in FIG. 4, the multilayer ceramic capacitor of the present invention uses a plurality of high permittivity materials having different Curie points, and has 3 to 3 points between the high permittivity materials.
By interposing the 0 μm ceramic layer, it has the effect of providing excellent temperature characteristics and easily realizing high capacitance with a small shape.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)、(b)は本発明の積層セラミック・コン
デンサチップの内部電極の積層構造の第1の実施例を示
す斜視図及び積層セラミック・コデンサの斜視図、第2
図(a)、(b)は本実施例の内部電極及びセラミック
層形成材料をセラミックグリーンシートに被着したとき
の断面図、第3図(a)、(b)は本実施例の積層構造
を説明するための斜視図及び断面図、第4図は本実施例
の積層セラミック・コンデンサと従来の積層セラミック
・コンデンサの温度による容量変化率を示す特性図、第
5図は本発明の積層セラミック・コンデンサチップの内
部電極の積層構造の第2の実施例を示す斜視図である。 1・・・セラミックグリーンシート、2・・・内部電極
、3・・・セラミック層、4a・・・保護膜用シート、
4b・・・電極形成用シート、4c・・・セラミック層
形成材料用シート、5a・・・保護膜用シート、5b・
・・電極形成用シート、6・・・切断位置、7.8・・
・積層セラミックコンデンサチップ、9・・・積層セラ
ミックコンデンサ、10・・・外部電極、13・・・セ
ラミック層形成材料。
FIGS. 1(a) and 1(b) are a perspective view showing a first embodiment of the multilayer structure of the internal electrode of the multilayer ceramic capacitor chip of the present invention, a perspective view of the multilayer ceramic capacitor, and a second embodiment of the multilayer ceramic capacitor chip.
Figures (a) and (b) are cross-sectional views when the internal electrode and ceramic layer forming material of this example are adhered to a ceramic green sheet, and Figures 3 (a) and (b) are the laminated structure of this example. FIG. 4 is a characteristic diagram showing the rate of change in capacitance due to temperature of the multilayer ceramic capacitor of this embodiment and a conventional multilayer ceramic capacitor, and FIG. 5 is a perspective view and a cross-sectional view for explaining the multilayer ceramic capacitor of the present invention. - It is a perspective view showing a second example of a laminated structure of internal electrodes of a capacitor chip. DESCRIPTION OF SYMBOLS 1... Ceramic green sheet, 2... Internal electrode, 3... Ceramic layer, 4a... Protective film sheet,
4b... Sheet for electrode formation, 4c... Sheet for ceramic layer forming material, 5a... Sheet for protective film, 5b...
... Sheet for electrode formation, 6... Cutting position, 7.8...
- Multilayer ceramic capacitor chip, 9... Multilayer ceramic capacitor, 10... External electrode, 13... Ceramic layer forming material.

Claims (1)

【特許請求の範囲】[Claims]  セラミック誘電体層と内部電極が交互に積層して成る
積層セラミック・コンデンサにおいて、前記セラミック
誘電体層がキュリー点の異る少くとも二種類の磁器組成
物材料で形成され、かつ、複数の前記セラミック誘電体
層の間に3乃至30μmの前記磁器組成物材料と固溶し
にくいセラミック層を形成したことを特徴とする積層セ
ラミック・コンデンサ。
In a multilayer ceramic capacitor in which ceramic dielectric layers and internal electrodes are alternately laminated, the ceramic dielectric layer is formed of at least two types of ceramic composition materials having different Curie points, and a plurality of the ceramic A multilayer ceramic capacitor characterized in that a ceramic layer having a thickness of 3 to 30 μm and which is difficult to form a solid solution with the ceramic composition material is formed between the dielectric layers.
JP62267300A 1987-10-21 1987-10-21 Laminated ceramic capacitor Granted JPH01108716A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62267300A JPH01108716A (en) 1987-10-21 1987-10-21 Laminated ceramic capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62267300A JPH01108716A (en) 1987-10-21 1987-10-21 Laminated ceramic capacitor

Publications (2)

Publication Number Publication Date
JPH01108716A true JPH01108716A (en) 1989-04-26
JPH0515294B2 JPH0515294B2 (en) 1993-03-01

Family

ID=17442913

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62267300A Granted JPH01108716A (en) 1987-10-21 1987-10-21 Laminated ceramic capacitor

Country Status (1)

Country Link
JP (1) JPH01108716A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117585988A (en) * 2023-11-17 2024-02-23 江苏师范大学 A multi-layer composite structure ceramic with high thermal conductivity and high mechanical properties and its preparation method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117585988A (en) * 2023-11-17 2024-02-23 江苏师范大学 A multi-layer composite structure ceramic with high thermal conductivity and high mechanical properties and its preparation method
CN117585988B (en) * 2023-11-17 2026-04-14 江苏师范大学 High-thermal-conductivity high-mechanical-property multilayer composite structural ceramic and preparation method thereof

Also Published As

Publication number Publication date
JPH0515294B2 (en) 1993-03-01

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