JPH01110577U - - Google Patents
Info
- Publication number
- JPH01110577U JPH01110577U JP505288U JP505288U JPH01110577U JP H01110577 U JPH01110577 U JP H01110577U JP 505288 U JP505288 U JP 505288U JP 505288 U JP505288 U JP 505288U JP H01110577 U JPH01110577 U JP H01110577U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- gain control
- output signal
- signals
- control circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Processing Of Color Television Signals (AREA)
Description
第１図は本考案の自動ホワイトバランス回路の
実施例のブロツク図、第２図は第１図の説明用波
形図である。
１……入力端子、２……利得制御回路、３……
制御端子、４……出力端子、５……サンプルホー
ルド回路、６……比較回路、７，８……アツプ・
ダウン・カウンタ、９，１０……ＤＡコンバータ
、１１……スイツチ、Ｔ１〜Ｔ３……タイミング
パルス、Ｔ１１〜Ｔ１３……切換パルス、ＶＢ，
ＶＲ……出力信号、ＶＧ……固定電圧源。
FIG. 1 is a block diagram of an embodiment of the automatic white balance circuit of the present invention, and FIG. 2 is a waveform diagram for explaining FIG. 1...Input terminal, 2...Gain control circuit, 3...
Control terminal, 4... Output terminal, 5... Sample hold circuit, 6... Comparison circuit, 7, 8... Up/down
Down counter, 9, 10...DA converter, 11...Switch, T1 to T3 ...timing pulse, T11 to T13 ...switching pulse, VB,
VR...output signal, VG...fixed voltage source.
Claims (1)
の映像信号を入力して、その制御端子に印加され
る制御電圧により利得制御を行なう利得制御回路
と、 前記利得制御回路の出力信号を前記第３の映像
信号に対応したタイミングパルスでサンプルホー
ルドするサンプルホールド回路と、 前記利得制御回路の出力信号と前記サンプルホ
ールド回路の出力信号を比較する比較回路と、 前記比較回路の出力信号をそれぞれ前記第１及
び第２の映像信号に対応したタイミングパルスで
入力する第１及び第２のアツプ・ダウン・カウン
タと、 前記第１及び第２のアツプ・ダウン・カウンタ
の出力信号をそれぞれ入力して、アナログ電圧に
変換する第１及び第２のＤＡコンバータと、 前記第１及び第２のＤＡコンバータの出力信号
と固定電圧源の３信号を入力して、それぞれ前記
第１、第２及び第３の映像信号にそれぞれ対応し
た切換パルスで順次切換えて前記利得制御回路の
制御端子へ出力するスイツチとを有して構成した
ことを特徴とする自動ホワイトバランス回路。[Claims for Utility Model Registration] The first, second and third claims sent sequentially in a time-sharing manner
a gain control circuit that inputs a video signal and performs gain control using a control voltage applied to its control terminal; and a gain control circuit that samples and holds an output signal of the gain control circuit at a timing pulse corresponding to the third video signal. a sample and hold circuit; a comparison circuit that compares the output signal of the gain control circuit with the output signal of the sample and hold circuit; and a comparison circuit that compares the output signal of the comparison circuit with timing pulses corresponding to the first and second video signals, respectively. first and second up-down counters to be input; and first and second DA converters to each input the output signals of the first and second up-down counters and convert them into analog voltages; , inputting the output signals of the first and second DA converters and three signals of the fixed voltage source, and sequentially switching them with switching pulses corresponding to the first, second, and third video signals, respectively, to adjust the gain. An automatic white balance circuit comprising: a switch for outputting to a control terminal of a control circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP505288U JPH01110577U (en) | 1988-01-19 | 1988-01-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP505288U JPH01110577U (en) | 1988-01-19 | 1988-01-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01110577U true JPH01110577U (en) | 1989-07-26 |
Family
ID=31208090
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP505288U Pending JPH01110577U (en) | 1988-01-19 | 1988-01-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01110577U (en) |
-
1988
- 1988-01-19 JP JP505288U patent/JPH01110577U/ja active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH01110577U (en) | ||
| JPS62105628U (en) | ||
| JPS63141467U (en) | ||
| JPH0211600U (en) | ||
| JPH0361727U (en) | ||
| JPS5926688Y2 (en) | signal converter | |
| JPS61119467U (en) | ||
| JPS59202724A (en) | Analog to digital converter | |
| JPS6138572U (en) | Analog voltage measuring device | |
| JPH01245622A (en) | D/a conversion method | |
| JPH01151627U (en) | ||
| JPH01105212U (en) | ||
| JPS6347693U (en) | ||
| JPS62134076U (en) | ||
| JPS6138570U (en) | Analog voltage measuring device | |
| JPS6167569U (en) | ||
| JPS61107236U (en) | ||
| JPH03109173U (en) | ||
| JPS6277929U (en) | ||
| JPH0373040U (en) | ||
| JPH0237596U (en) | ||
| JPS6217250U (en) | ||
| JPS6454428U (en) | ||
| JPS5814173U (en) | Peak hold circuit | |
| JPS6415168U (en) |