JPH01110599U - - Google Patents
Info
- Publication number
- JPH01110599U JPH01110599U JP606488U JP606488U JPH01110599U JP H01110599 U JPH01110599 U JP H01110599U JP 606488 U JP606488 U JP 606488U JP 606488 U JP606488 U JP 606488U JP H01110599 U JPH01110599 U JP H01110599U
- Authority
- JP
- Japan
- Prior art keywords
- output
- surround circuit
- signal
- audio
- delayed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Television Receiver Circuits (AREA)
Description
第１図はこの考案の一実施例の構成を示す回路
図、第２図は第１図の具体的構成の一例を示す回
路図、第３図はこの考案の第２の実施例の構成を
示す回路図、第４図は第３図の具体的構成の一例
を示す回路図、第５図は従来のサラウンド回路の
構成を示す回路図、第６図は第５図の動作を説明
するための図、第７図はサラウンド回路を使う場
合のスピーカ配置例を示す図、第８図はサラウン
ド回路を有するテレビジヨン受像機の外観構成の
一例を示す斜視図である。
１１，１２……入力端子、１３，１４……ミキ
シング回路、１５，１６……出力端子、１７……
和信号発生回路、１８……遅延回路、１９……信
号分離回路、２０，２１……出力端子、２２……
エコー量調整回路、２３……足込み量調整回路、
３１，３２……フロントスピーカ、３３……聴取
者、３４，３５……リアスピ―カ、４１……レベ
ル比較回路、４２……差信号発生回路、４３……
アンプ、４４……スイツチ回路、４５，４６……
結合コンデンサ、４７……減衰・バイパス回路、
４１１……ボロテージフオロア回路、４１２，４
１４……ダイオード、４１３，４１５……コンデ
ンサ、４１６，４１７……トランジスタ、４１８
〜４２０……抵抗、４２１……オペアンプ、４２
２〜４２５……抵抗、４４１，４４２……アナロ
グスイツチ、４７１，４７２……抵抗、４７３…
…アナログスイツチ。
Figure 1 is a circuit diagram showing the configuration of an embodiment of this invention, Figure 2 is a circuit diagram showing an example of the specific configuration of Figure 1, and Figure 3 is a circuit diagram showing the configuration of a second embodiment of this invention. 4 is a circuit diagram showing an example of the specific configuration of FIG. 3, FIG. 5 is a circuit diagram showing the configuration of a conventional surround circuit, and FIG. 6 is for explaining the operation of FIG. 5. FIG. 7 is a diagram showing an example of speaker arrangement when using a surround circuit, and FIG. 8 is a perspective view showing an example of the external configuration of a television receiver having a surround circuit. 11, 12... Input terminal, 13, 14... Mixing circuit, 15, 16... Output terminal, 17...
Sum signal generation circuit, 18... Delay circuit, 19... Signal separation circuit, 20, 21... Output terminal, 22...
Echo amount adjustment circuit, 23... Footing amount adjustment circuit,
31, 32...Front speaker, 33...Listener, 34, 35...Rear speaker, 41...Level comparison circuit, 42...Difference signal generation circuit, 43...
Amplifier, 44... Switch circuit, 45, 46...
Coupling capacitor, 47...attenuation/bypass circuit,
411... Voltage follower circuit, 412,4
14...Diode, 413,415...Capacitor, 416,417...Transistor, 418
~420... Resistor, 421... Operational amplifier, 42
2 to 425...Resistance, 441,442...Analog switch, 471,472...Resistance, 473...
...Analog switch.
Claims (1)
合せてフロント側音声出力とリア側音声出力を得
るサラウンド回路に於いて、 原音の左チヤンネル及び右チヤンネルの音声信
号の和をとる和信号発生手段と、 上記原音の左チヤンネル及び右チヤンネルの音
声信号の差をとる差信号発生手段と、 この差信号発生手段の出力を所定の利得で増幅す
る増幅手段と、 上記和信号発生手段の出力と上記増幅手段の出
力との振動レベルを比較するレベル比較手段と、 このレベル比較手段の比較結果に従つて、モノ
ラル信号入力時、上記遅延信号の出力を減衰する
減衰手段とを具備したことを特徴とするサラウン
ド回路。 (2) 上記減衰手段は、 上記レベル比較手段の比較結果に従つて上記和
信号発生手段と上記差信号発生手段の出力を択一
的に選択する選択手段と、 この選択手段の選択出力を遅延し、上記遅延信
号を得る遅延手段とを具備したことを特徴とする
請求項１記載のサラウンド回路。 (3) 上記減衰手段は、 上記和信号発生手段の出力を遅延する遅延手段
と、 上記レベル比較手段の比較結果に従つて、モノ
ラル信号入力時、上記遅延手段の遅延出力を減衰
する減衰手段とを具備したことを特徴とする請求
項１記載のサラウンド回路。 (4) 上記サラウンド回路は、上記フロント側音
声出力として上記原音の左チヤンネルと右チヤン
ネルの音声信号及び上記遅延信号を出力し、上記
リア側音声出力として上記遅延信号を出力するよ
うに構成されていることを特徴とする請求項１記
載のサラウンド回路。 (5) 上記サラウンド回路は、上記フロント側音
声出力として上記原音の左チヤンネルと右チヤン
ネルの音声信号を出力し、上記リア側音声出力と
して上記遅延信号を出力するように構成されてい
ることを特徴とする請求項１記載のサラウンド回
路。 (6) 上記サラウンド回路は、上記遅延信号にエ
コー信号を含むように構成されていることを特徴
とする請求項１記載のサラウンド回路。[Claims for Utility Model Registration] (1) In a surround circuit that appropriately combines the original audio signal and its delayed signal to obtain front audio output and rear audio output, audio signals of the left channel and right channel of the original audio. a difference signal generating means for taking the difference between the left channel and right channel audio signals of the original sound; and an amplifying means for amplifying the output of the difference signal generating means with a predetermined gain; Level comparison means for comparing the vibration levels of the output of the sum signal generation means and the output of the amplification means; and attenuation means for attenuating the output of the delayed signal when a monaural signal is input, according to the comparison result of the level comparison means. A surround circuit characterized by comprising: (2) The attenuation means includes a selection means for selectively selecting the output of the sum signal generation means and the difference signal generation means according to the comparison result of the level comparison means, and a selection means for delaying the selected output of the selection means. 2. The surround circuit according to claim 1, further comprising delay means for obtaining said delayed signal. (3) The attenuation means includes a delay means for delaying the output of the sum signal generation means, and an attenuation means for attenuating the delayed output of the delay means when a monaural signal is input, according to the comparison result of the level comparison means. The surround circuit according to claim 1, further comprising:. (4) The surround circuit is configured to output the audio signals of the left channel and right channel of the original sound and the delayed signal as the front audio output, and output the delayed signal as the rear audio output. 2. The surround circuit according to claim 1, further comprising a surround circuit. (5) The surround circuit is configured to output audio signals of the left channel and right channel of the original sound as the front audio output, and output the delayed signal as the rear audio output. The surround circuit according to claim 1. (6) The surround circuit according to claim 1, wherein the surround circuit is configured so that the delayed signal includes an echo signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP606488U JPH01110599U (en) | 1988-01-21 | 1988-01-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP606488U JPH01110599U (en) | 1988-01-21 | 1988-01-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01110599U true JPH01110599U (en) | 1989-07-26 |
Family
ID=31209980
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP606488U Pending JPH01110599U (en) | 1988-01-21 | 1988-01-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01110599U (en) |
-
1988
- 1988-01-21 JP JP606488U patent/JPH01110599U/ja active Pending
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