JPH01112294A - Average calculation device with hysteresis characteristics - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an average calculation device that calculates an average value of a continuously changing digital signal, particularly an average value having hysteresis characteristics.

[Prior art and its problems]

Conventionally, there has been a problem with digital signals that change continuously, such that the digital values fluctuate drastically due to causes such as errors during quantization and fluctuations in the digital signal itself. For example, if a signal near the threshold hold level is quantized, the digital signal will have values n and n+1 (n
, n+1 is a specific value) may be repeated randomly.

In order to suppress such undesirable changes in digital values, for example, it is possible to prepare two threshold levels and selectively switch between these two threshold levels depending on past digital values. It is being Specifically, if the value n was determined in the past, the value n
A higher threshold level is selected between +1 and the value n, and conversely, if the value n+1 was determined in the past, a lower threshold level is selected between the value n+1 and the value n. It is. In this way, the above-mentioned meaningless changes in the digital signal are reduced. However, in this case, a problem arises in that two threshold levels must be maintained between each level, for example, they must be stored in a ROM. Further, a circuit configuration is required to determine whether the value taken in the past is n or n+1 and to switch the threshold level.

[Purpose of the invention]

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide an average calculation device that can obtain a digital output having a hysteresis characteristic similar to that of the above-mentioned example with a simple configuration.

[Key points of the invention]

That is, in order to achieve the above object, the present invention records a predetermined number of digital signals output by the digital signal output means while rewriting them in order of newest, and averages the contents of the digital signals and the previously obtained calculation results. is calculated by the calculation means, and the supply means outputs the calculation result obtained by the calculation means as a new digital signal, and
The key point is that the previously obtained calculation result is supplied to the calculation means again.

Therefore, the new digital signal outputted by the supplying means is an average value having a hysteresis characteristic of 3- with respect to the digital signal outputted by the digital signal outputting means. Therefore, the above-mentioned situation in which the digital signal repeatedly takes (i:n and the value fi+l) is eliminated.

〔Example〕

Hereinafter, an example in which the present invention is applied to an electronic musical instrument having a pinch extraction function, specifically, an average value having a hysteresis characteristic is used as pitch data will be described in detail.

FIG. 1 is a circuit configuration diagram of an embodiment, showing the configuration of an electronic musical instrument that generates musical tones in response to audio input. The output of the microphone 1, which converts audio into electrical signals, is processed by the preprocessing unit 2.
join. The output of the preprocessing section 2 is connected to the pinch extraction section 3. The output of the pinch extractor 3 is applied to a processor (CPU) 5 via a latch 4. The output of the processor 5 is sent to the pinch extraction unit 3, described in 1. It is connected to the W section 6, the error removal section 7, the moving average calculation section 8, and the flag creation section 9. The output of the storage section 6 is applied to an error removal section 7 and a pitch data control section 10, and the output of the error removal section 7 is applied to a moving average calculation section 8 and a pitch data control section 10 for performing an average calculation, for example, a moving average calculation. The output of the moving average calculation section 8 is connected to a pitch data control section 10 and a code generator 11.

Further, the output of the pitch data control section 10 is also connected to the code generator 11. The output of the code generator 11 is connected to a musical tone generator 12, and the output of the musical tone generator 12 is connected to a speaker 13 that converts an electrical signal into sound.

The audio signal converted into an electrical signal by the microphone 1 is applied to a preprocessing section 2, where it is preprocessed. This pretreatment is the first
For example, a low-pass filter (1,.

PF) etc. to remove out-of-band signals.

This out-of-band removal is done to prevent malfunctions in the pinch extraction performed by the next stage.

Furthermore, the second step of the preprocessing is to amplify the input audio signal from which out-of-band components have been removed by an automatic gain control circuit to a specific amplitude value.

Third, the input audio signal having the above-mentioned specific amplitude value is converted into digital data by an analog/digital conversion circuit. The aforementioned amplification to achieve the specific amplitude value is performed in order to make the number of output bits of this analog/digital conversion circuit effective.

The audio signal processed by the preprocessing section 2, that is, the digital audio signal, is applied to the pinch extraction section 3. The pinch extractor 3 extracts the pitch of the fundamental frequency of the input audio signal under the control of the processor (CPU) 5. The pinch extraction unit 3 includes an audio data quantization circuit, a scale extraction circuit, etc., details of which are described in, for example, Japanese Patent Application No. 58-31284, Japanese Patent Application No. 58-31285, and Japanese Patent Application No. 58-31286. It has a ternary correlation processing circuit and performs pitch extraction using these circuits. The data quantization circuit sequentially obtains the maximum and minimum values of the audio digital data over a specific period of time, and uses the maximum and minimum values to determine respective threshold levels for ternarization, for example. Then, the input signal is ternarized using that threshold. The audio extraction circuit is a circuit that delays audio ternary data obtained by ternarizing audio data using the aforementioned audio digital data in correspondence with the scale to be extracted, and multiplies the delayed data by input data. This circuit provides time correlation. This data simply represents the temporal correlation between the delay data and the input data, and is further processed to perform pitch extraction. The above-mentioned ternary correlation processing circuit performs this extraction. The ternary correlation processing circuit is a circuit that performs window processing and the like for pitch extraction. That is, since a plurality of pieces of data are outputted from the above-mentioned scale extraction circuit corresponding to the scale to be extracted, the plurality of data are subjected to window processing in this ternary correlation processing circuit, in other words, they are weighted in relation to the scale. and then repeat it for a specific time (1 frame)
Accumulate. Then, the maximum value is determined from the accumulated values (accumulated values corresponding to the delay times), and the pinch is determined and output from the delay time corresponding to the maximum value. This output is data related to the pinch of the fundamental wave of the input audio (including tonic waves).

The pitch data output from the pinch extraction section 3 described above is stored in the storage section 6 via the latch 4 and the processor 5.

The error removal unit 7 uses the data stored in the storage unit 6 to detect a change in specific pitch data, especially a change of one octave or more in only one frame, and when the change is detected, the data is This is a circuit to restore the data to the state before it changed. Incidentally, there may be a sudden change in the scale, but in this case the data changes after one frame. The data from which errors have been removed in the error removal section 7 is averaged in a moving average calculation section 8. This average is, for example, a weighted average of the average up to now and data over six frames. To explain in more detail, this calculation unit 8 stores sequentially input pinch data in frame units in a shift register and shifts them in frame units, and the six stages of shift data and the average value are transferred to one frame by a selector. The average is performed by selecting and accumulating within a period and truncating the lower bits, for example.

The averaged data is output from the moving average calculation unit 8,
It is added to the pitch data control section 10 and performs processing for generating musical tones. In other words, the error removal unit 7 described above detects a malfunction in pinch extraction due to external noise, etc.
There are also circuits that remove large, step-like data changes resulting from pitch extraction malfunctions. The moving average calculation unit is a circuit that has a hysteresis effect and averages subtle changes in data due to pinch errors caused by subtle pinch changes in input audio, etc., to stabilize the data.

The human voice is not limited to singing; it also has consonants and vowels.

There are many pinches of the fundamental wave in vowels, but there are very few pinches in consonants. For this reason, while only consonants are being produced (for example, when producing "SA", "S"
”), the pitch of the fundamental wave may be extracted incorrectly.The pinch data control unit eliminates malfunctions of musical tones due to these incorrect extractions and ensures that the pitch corresponds to the pitch of the input voice. Then, this control section selects the data stored in the storage section 6, the output data of the error removal section 7, or the output data of the moving average calculation section 8, using data such as audio power and audio input detection. and output it.

The code generator 11 is the pinch control section 1 of the aforementioned pinch control 8'■
This circuit converts the output of 0 into the code of the musical tone to be generated by the musical tone generating section 12, that is, musical tone data.

The pitch extraction unit 3, storage unit 6, error removal unit 7,
The moving average calculation unit 8 is controlled by the processor 5. Further, the pitch data control section 10 and the code generator 11 are controlled by the processor 5 via the flag generation section 9. In other words, the processor 5 sets a flag in the flag generation section 9, and the pitch data control section 10 and code generator 11 described above operate according to the flag.

The output of the code generator 11, ie, the converted data, is applied to the musical tone generator 12, and specifies the musical tone to be output by the speaker 13. In other words, the musical tone generator 12
Then, a musical tone electrical signal (analog) specified by the conversion data of the code generator 11 is generated, and the signal is output from the speaker 1.
Add that to 3. As a result, the speaker 13 generates a musical tone corresponding to the input voice.

The circuit shown in FIG. 1 represents the configuration of an electronic musical instrument that generates musical tones in response to audio input, and the moving average calculation device of the present invention will be further detailed below.

FIG. 2 is a circuit diagram showing the moving average calculating section 8 of FIG. 1 in more detail.

The output of the error removing section 7 is applied to the shift register 15 via the latch 14. Schiff I register 15 and lunch 16
The output is applied to the selector 17. Also clock φ. The output of the octal counter 18 is also added to the selector 17.

The output of the selector 17 described above is applied to the first input of the adder 19, and the output of the adder 19 is applied to the second input via the latch 20. Further, the output of adder 19 is applied to latch 21 via latch 20. The upper 8-bit output of latch 21 is applied to the first input of the adder, and the output of latch 21 is
The output of the 9th bit of 1 is added to the carry power of the adder 22. The output of the adder is applied to the latch 16 via the latch 23 and is also output to the next stage counter, that is, the pitch data system '4NrJ section 10.

The pitch data, for example 8-bit data, from which errors have been removed by the error removing section 7 is stored in the latch 14 as data for one frame. This latch 14 takes in data at the frame clock φ in order to process the error removed result in units of frames.

The shift register 15 is a register for shifting 8-bit parallel data, and is shifted in response to a frame clock φ. That is, the data stored in the launch is sequentially stored in a shift register in units of frames and shifted. In other words, the shift register 15 is a circuit that records six data preceding the current data in order to obtain an average.

On the other hand, the launch 16 is two sets of launch circuits, and the same data as the output of the moving average calculating section 8 of the tobacco is applied to this latch 16. The same data is stored in the two lunches. The selector 17 sequentially selects and outputs the 6-byte data (8 bits per byte) stored in the shift register 15 and the 2-byte data stored in the latch 16 within one frame. Note that this selection instruction is given by the clock φ having 8 clocks during one frame.
. This is done by the counter value of the octal counter 18, which is incremented by .

Since the output of the adder 19 is applied to the second input via the launch 20, the output of this circuit, that is, the output of the launch 20, sequentially transfers the data applied to the first input of the adder 19 to φ. Configure a cumulative power counter that accumulates with . Furthermore, this latch 20
is generated at the end of one frame and is reset to 1- by the set clock φ□, so it is accumulated in units of frames.

The first input of the adder 19 is sequentially supplied with a clock φ by the selector 17 described above. Since the contents of the shift register 15 and latch 16 are selected and added in accordance with is the added value. That is, the data stored in the shift register 15 is read. + 1 ”' D, . 6, latch 23
If the data being outputted from the D9 is D9, the accumulated output DX of the above-mentioned accumulating circuit becomes DX - Σ Drl+ノ + 2 · Dsl=+.

With this adder, the value obtained by weighting the average value and the six data are accumulated, and an accumulated value for determining a new average value is obtained. The data that weights the previous average value is used as the data for calculating the average value corresponding to the new, ie, next frame clock. This is to keep adjacent data constant since data often fluctuates randomly due to errors in pinch extraction etc. Since the data added to the first input of the adder 19 is 8 bits, the above-mentioned The cumulative output becomes 11-bit data.The next latch 21 and adder 22 calculate the output, that is, D x /8.

Latch 21 stores the accumulated output and adds the upper 8 bits to the input of adder 22. Then add the 9th bit to Adder 22's carry power. The reason why the 9th bit is added to the adder 22 is to consider the 9th bit rather than simply truncating the lower three bits of the 11-bit data. That is, when the 9th bit is "1", 1 is added to the data of the upper 8 bits to obtain the average output, and at 00, no addition is made, and the lower 3 bits are discarded and output. This latch 21 and adder 2
As mentioned above, 2 is a circuit for outputting the average value with high precision, and is not required if high precision is not required.

The output of adder 22 is stored in latch 23.

This latch 23 is a circuit for keeping the interframe data constant, since its output is used in the next stage and accumulation during the next frame.

In summary, the circuit in Figure 2 uses the average value as part of the input data to create a hysteresis effect on the average operation, preventing it from responding too quickly to changes in the lower bits of the data. FIG. 3 is a timing diagram showing timing clocks of each circuit in the embodiment of the present invention. The operation shown in FIG. 2 will be further explained using this timing diagram. The frame clock φ is a clock that is generated at the beginning of one frame and is used to store necessary data and shift data.

In Figure 2, latch 14,16, shift register 1
5 runs on that clock. By generating this clock, stored data such as lunch is fixed for one frame. And then clock φ. is sequentially output eight times between I frames. This clock increments the octal counter 18 and converts the 8 data manually input by the selector 17 into 1.
This is for sequential selection within a frame. moreover,
It is also a clock for accumulating. That is, the clock ψ.

At the rising edge of , the octal counter 18 increments and selects data. Then, the selected data is added to the adder 19.

At this time, the selected data and the added data up to now are input to the adder 19, and are added, that is, accumulated, by this adder. and clock φ. Latch φ at the falling edge of . stores that data. This operation is performed eight times per frame and accumulated. Note that, as described above, this accumulation is an addition of twice the average value of the past six data and the previous data. After generation of the 8th clock, the clock φ
5 is generated and the accumulated value is stored in latch 21. Almost at the same time as this storage, the accumulated value is added to the adder 22, so the adder performs addition with the carry mentioned above and outputs it. This output becomes the average value. This process is performed by the next clock φ. Done before 5T, clock φ. The latch 23 stores and outputs the average value by ul. and clock φ
, resets the storage of the latch 20. This clock ψ1 is a clock for performing accumulation in units of one frame.

One embodiment of the present invention has been described above in detail.

The above-described embodiment has a circuit that calculates a new average value by accumulating the above-mentioned 6 data and twice the average value, but this is not limited to 6 data and is not necessarily twice the average value. Note that when the number of data or the multiple of the average value is changed other than in the embodiment, a corresponding division circuit is required.

〔Effect of the invention〕

As described above, in the present invention, the storage means stores a predetermined number of digital signals output by the digital signal output means while rewriting them in chronological order, and averages the stored contents of the storage means and previously obtained calculation results. Calculate with arithmetic means,
The supply means outputs the calculation result obtained by the calculation means as a new digital signal, and also supplies the calculation result to the calculation means again as the previously obtained calculation result, thereby producing an average value having hysteresis characteristics. It is possible to obtain a digital signal with a simple configuration.

Therefore, it is possible to suppress the phenomenon in which the digital signal takes undesirable changes due to errors during quantization or fluctuations in the digital signal itself, in other words, it randomly changes alternately between the values n and n+1. effective.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of an embodiment of the present invention, FIG. 2 is a more detailed circuit diagram of the moving average calculation section of FIG. 1, and FIG. 3 is a timing clock diagram of the embodiment of the present invention. 8...Moving average calculation unit, 14.16.20.21.23...Latch, 15...
・Shift register, 17...Selector, 18...Counter, 19.22...Adder. Patent applicant Casio Computer Co., Ltd.

Claims (2)

[Claims] (1) Digital signal output means for outputting a continuously changing digital signal; storage means for storing a predetermined number of digital signals outputted from the digital signal output means while rewriting them in order of newest; a calculation means for calculating the average of a predetermined number of digital signals and a previously calculated calculation result; and outputting the calculation result obtained by this calculation means as a new digital signal, and outputting the calculation result obtained by the calculation means again to the calculation means from the previous calculation. supply means for supplying the calculated result, and the new digital signal outputted by the supply means is an average value having a hysteresis characteristic with respect to the digital signal outputted by the digital signal output means. An averaging device with hysteresis characteristics. (2) The storage means stores a plurality of the digital signals output from the digital signal output means while rewriting them in order of newest, and the calculation means stores the plurality of digital signals and the previously calculated calculation results. 2. The average calculation device having hysteresis characteristics according to claim 1, wherein a moving average value having hysteresis characteristics is calculated by calculating the average.