JPH01120980A - Video signal multiplex transmission system - Google Patents

Abstract

PURPOSE:To cope flexibly with a change in channel number of an input television signal while improving the transmission efficiency by providing a threshold value corresponding to a horizontal synchronizing portion of a television signal to a digital parallel signal of a separated television signal so as to attain the stabilization of hunting and synchronization detection for establishing synchronization thereby detecting a true horizontal synchronizing signal and establishing the frame synchronization of a transmission line. CONSTITUTION:A horizontal synchronizing detection section 29 compares a digital television signal inputted to a D/A conversion section 30 with a threshold level L over one line period and when a television signal lower than threshold level L exists for a prescribed number or over, the horizontal synchronizing signal is detected, and when not, the horizontal synchronizing signal is not detected and a signal is outputted to a separation counter control section 31. The separation counter control section 31 uses a synchronizing protection circuit 32 based on an output signal of a horizontal synchronizing detection section 29 to apply the signal processing of synchronization protection protecting mis-synchronism of the horizontal synchronizing signal and erroneous out of synchronism due to an error in the transmission line, and in case of out of synchrnism, a simplified separator section 27 shifts the phase of a counter applying serial/parallel conversion to replace the output channel of (N+M) bits so as to detect a correct head position.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video signal multiplex transmission system, and more particularly to establishing synchronization when digitally encoding and transmitting television signals.

(Prior art) This type of conventional method is described in the "Journal of Television Society" (vol.
, 39. No. 9.1985. P, 822. P, 829
), the paper ``Transmission of digital signals'' will be explained.

Figures 4 and 5 are described in the above paper, and in Figure 4, (1) is an A/D converter that converts an analog signal, such as a television signal, into a digital signal; (2) is a synchronization unit that generates sampling pulses and multiplexed pulse synchronization bits, etc. of the A/D conversion unit (1); (
3) is a multiplexing unit that converts various parallel signals into serial signals using this multiplexed pulse, (4) is a code conversion unit that converts the output of multiplexing unit (3) into a transmission line code, and (5) is a transmission unit. Error correction circuit for improving path error rate, (6), (7
) is a pulse shaping unit and modulation unit that converts into a transmission signal, (8
) is the transmission path, (9) is the equalization unit that equalizes the transmission path, (10
) is a demodulation unit that extracts the original signal from the modulated wave, (11) is a code identification unit that restores the digital waveform at the time of transmission, and (12) is a synchronous reproduction that reproduces the synchronization of the transmission path from the output of the code identification unit (11). (13) is a code recovery unit that reproduces the original multiplexed serial signal, (14) is a separation unit that returns the output of the code recovery unit (13) to the original parallel 43, and (15) is a separation unit. (1
4) is a D/A converter that returns the output to an analog signal.

Fig. 5 is an example of a frame synchronization circuit, and in the figure,
(16) is a bit synchronization circuit that has functions such as timing reproduction to synchronize the bit phase of the PCM signal reproduced from the transmission path, and (17) is a frame pattern generator that is inserted on the transmitting side and generates a frame pattern. , (18)
is an AND gate that calculates the sum of the frame gate generated by the frame pattern generator (17) and the received PCM signal, (
19) is an AND gate that takes the sum of a frame gate and a frame pattern, (20) is an AND gate (18),
(19) This is a matching circuit that detects matching or non-matching of the outputs.

Next, to explain the operation, when the analog signal is converted into a digital signal by the A/D converter (1), the digital signal is combined with the signals of other channels by the multiplex pulse and frame synchronization signal generated in the synchronizer (2). After time division multiplexing in the multiplexing unit (3), the code conversion unit (4)
Output to. The code conversion unit (4) converts the multiplexed signal into a code suitable for transmission and outputs it as a transmission pulse train. In order to ensure the necessary code error rate at this time, an error correction code may be used by the error correction unit (5). The transmission pulse train generated by the code conversion section (4) is transmitted as is by the pulse shaping section (6) and modulation section (7) in baseband transmission such as wired transmission, while in wireless transmission it is transmitted as it is by the pulse shaping section (6) and modulation section (7). After waveform shaping is performed to limit the spectrum so as not to cause any interference, the carrier wave is modulated and transmitted. Next, after passing through the transmission path (8), on the receiving side, an equalizer (9) equalizes the transmission path characteristics and shapes the waveform, and then, in carrier wave transmission, a demodulator (10) processes the baseband signal. After the signal is demodulated, the pulse amplitude is determined by the clock timing in the code identification section (11), and the code is identified and reproduced. Based on this identification data, a synchronization reproducing section (12) performs clock regeneration in order to achieve bit synchronization. The bit-synchronized output of the code identifying section (11) is regenerated into a serial code output from the multiplexing section (3) in a code restoring circuit (13) and output to the separating section (14). The separator (14) converts the serial code into the original parallel code and outputs it to the D/A converter (15), which converts it back to the analog signal on the input side and outputs it.

However, it is necessary to establish frame synchronization in the separating section (14) in order to make the separating order the same as the transmitting side order. FIG. 5 shows a means for establishing this frame synchronization. In the figure, the bit synchronizer (16) regenerates the transmission line clock for the received PCM signal, and the frame pattern generator (17) transmits it. A frame pattern of the same pattern as the one inserted at the side is generated and verified by the minus number circuit (20), and in case of mismatch, the frame counter in the frame pattern generator (17) is reset or shifted by 1 bit. This detects the synchronization position and establishes frame synchronization.

(Problems to be Solved by the Invention) Conventional video signal multiplex transmission systems were configured as described above, and as the transmission path bit rate increases to insert a frame synchronization pattern, the transmission efficiency decreases.
In addition, because the frame format is specified, it is not possible to respond flexibly to changes in the number of channels of input analog signals, and when the number of channels of input analog signals increases, the bit rate of the transmission path increases. There were problems such as making it difficult to operate the frame synchronization circuit on the side at high speed.

The present invention has been made to solve the above-mentioned problems, and it is possible to realize a circuit configuration that can increase transmission efficiency and flexibly respond to changes in the number of channels of input television signals. The object of the present invention is to obtain a video signal multiplex transmission system that can establish synchronization between transmission and reception of transmission line signals using a circuit that operates at a lower bit rate than the transmission line clock.

[Means for solving problems]

The video signal multiplex transmission system according to the present invention has an A/
When converting a television signal into a digital signal in the D conversion section, a multiplex pulse/sampling clock generation section that generates a sampling clock and a multiplexed pulse; A parallel/serial converter (hereinafter referred to as "rP/S converter") converts the signal from the /D converter from parallel to serial and multiplexes the signal, and the receiving side is equipped with a an S/P converter that converts a serial signal into a parallel digital signal;
a threshold setting section that sets a horizontal synchronization signal threshold for each of the parallelized signals; a horizontal synchronization detection section that compares the threshold setting section and the horizontal synchronization signal to detect a horizontal synchronization signal; and the horizontal synchronization detection section. a separation counter control section that counts and controls each demultiplexed phase based on a detection signal from the section; and a protection circuit that protects the synchronization of the parallel digital signals by transmitting and receiving signals to and from the separation counter control section. It is composed of

[Effect]

According to the present invention, synchronization verification and hunting for establishing synchronization are performed on digital parallel signals of separated television signals.
A threshold corresponding to the horizontal synchronization part of the television signal is set, and if the threshold value is satisfied for a certain number or more consecutively in one line of the television signal, it is considered that synchronization has been established and synchronized operation is performed, but if not, synchronization is performed. After protection is performed, a true horizontal synchronization signal is detected and frame synchronization of the transmission line is established by shifting the transmission line clock phase or shifting the phase of the separation counter.

〔Example〕

The present invention will be explained below based on the embodiments shown in FIGS. 1 to 3. FIG. 1 is a diagram showing the circuit configuration of this embodiment system. In the figure, (21) is an A/D conversion unit that A/D converts one channel of a composite television signal into an N-bit parallel signal, and (22) (23) is the sampling clock used in the A/D converter (21) and a multiplexed pulse/sampling clock generator that generates multiplexed pulses for converting parallel signals into serial signals; (23) is the A/D converter (21);
3) Output N bits and digital signal M of audio data etc.
(24) is a transmission line interface, (25) is a transmission line, (26) is a transmission line interface, (27) is a time A simple separation unit converts the divided and multiplexed serial signal (N+M) bits into a parallel signal, (28) is a threshold setting unit that applies a threshold in accordance with the horizontal synchronization signal, and (29) is a D/A conversion unit (30).
), the horizontal synchronization detection section detects horizontal synchronization by comparing the digital television signal input manually with the N bits output from the horizontal synchronization signal threshold setting section (28), and the horizontal synchronization detection section (31) does not detect horizontal synchronization. The separation counter control unit (32) changes the output channel of the parallel (N+M) bits of the serial/parallel conversion of the simple separation unit in case of a false horizontal synchronization signal, or if there is a transmission line error or This is a synchronization protection circuit to prevent synchronization loss due to detection of the end of horizontal synchronization in the vertical blanking section of the signal.

Next, to explain the operation, in Fig. 1, the NTS
The C-scheme television composite signal is converted into a parallel N-bit digital signal in an A/D converter (21) in synchronization with a sampling clock provided from a multiplexed pulse/sampling clock generator (22). When other information such as voice, data, etc., digital signals (
(synchronized with the sampling clock) is also converted from parallel to serial by the simple multiplexer (23) together with the digital signal of the television signal. television signal N bits,
The order in which M bits such as audio data are multiplexed may be arbitrary, and when demultiplexing on the receiving side, it is performed in the same order as on the transmitting side. The simple multiplexer (23) does not particularly insert a frame synchronization pattern, but simply multiplexes the signals into the vehicle. The signal string converted into a serial signal by the simple multiplexing section (23) is converted into a code suitable for the transmission path at the transmission path interface section (24), and then sent to the receiving side via the transmission path (25). .

On the receiving side, the transmission line interface unit (26) regenerates the same serial signal as the original output of the simple multiplexer (23), and the simple separator (27) converts the appropriate position iif into (N+
This is regarded as the first position of M) bits and is decomposed in parallel into (N+M) bits, but this decomposition does not necessarily match the first position of (N+M) bits before parallel-to-serial conversion on the transmitting side. Therefore, in this embodiment, in order to match the leading positions, the horizontal synchronization signal of the television signal is detected as described below. One line of a television signal can be shown in a simplified manner, for example, as shown in FIG. In the figure, (A) shows a horizontal synchronization signal. In addition, the simplified television signal in the vertical retrace interval can be expressed as shown in Figure 3, in which (a), (
D) is equalization pulse, (C) is vertical synchronization signal, (E),
(F) shows a horizontal synchronization signal. However, in order to detect the horizontal synchronization signal, the horizontal synchronization signal threshold setting section (28) must set a value slightly larger than the horizontal synchronization signal (A) or (E) in FIGS. 2 and 3. It is set in advance as a value converted into a digital signal.

In an NTSC television signal, digital video signal values that fall below the threshold level L in one line (horizontal synchronization frequency interval) continue in a horizontal synchronization interval, equalization pulse interval, or vertical synchronization interval, and the horizontal The synchronization signal detection means utilizes this, and the horizontal synchronization detection section (29) compares the digital television signal input to the D/A conversion section (30) with the threshold L over one line period or more. If there is a certain number of television signals or more and less than the threshold L, a horizontal synchronizing signal is detected, and if not, a signal is output to the separation counter control section (31) with the horizontal synchronizing signal not being detected. In the separation counter control section (31), this horizontal synchronization detection section (29)
Based on the output signal of the synchronization protection circuit (32), the synchronization protection circuit (32) performs synchronization protection signal processing to protect against erroneous synchronization of the horizontal synchronization signal and erroneous synchronization loss due to a transmission path error. By shifting the phase of the counter that performs serial-to-parallel conversion in the column section (27), the correct starting position for multiplexing the same (N+M) bits as on the transmitting side is detected by changing the output channels of (N+M) bits, and the transmission path is This establishes synchronization between transmission and reception through the network.

Therefore, according to this embodiment, since synchronization between transmission and reception of multiplexed frames is performed using a horizontal synchronization signal after demultiplexing on the receiving side, it is possible to flexibly respond to changes in the number of channels of input analog signals on the transmitting side. It is also easy to synchronize with increases in transmission line bit rate.

In the above embodiment, the parallel outputs of the A/D converter (21) are input to the simple multiplexer (23), but for example, digital signal processing circuits such as band compression using predictive coding are used for A/D conversion. It may be inserted between the unit (21) and the simple multiplexing unit, and in this case, on the receiving side, it may be inserted immediately after the simple separation unit. In addition, in the above embodiment, the case where the television signal has one channel has been explained, but when the television signal has multiple channels, the output of the A/D converter of the second and subsequent channels is converted into digital data such as audio and data. In order to detect the horizontal synchronization of the first channel on the receiving side, the parallel bits of the A/D converter output of the second and subsequent channels are , by changing the order of multiplexing, interleaving with appropriate audio and data bits, and interleaving between television signal channels from the second channel onward, to perform A/D conversion of the first channel. If the order of multiplexing the parallel N bits output from the A/D converter section and the order of multiplexing the N bits output from the A/D converter section from the second channel onwards are made different, the same effects as in this embodiment can be obtained. can be played.

Furthermore, in the above embodiment, when the separation counter control unit (31) does not detect a horizontal synchronization signal, the serial-parallel counter is shifted, but instead of this, after separating the signals into parallel signals, the channel switching switch etc. Even if the control is performed using the following, the same effect as that of the embodiment can be obtained.

Furthermore, although the above embodiment describes a digital transmission system, it is also applicable to a device that digitizes signals including television signals and includes a signal processing system that performs serial-to-parallel conversion and parallel-to-serial conversion. , it goes without saying that the same effects as in the above embodiment can be achieved.

(Effects of the Invention) According to the present invention, in a digital transmission system including television signals, synchronization between transmission and reception of multiplexed frames is established using the horizontal synchronization signal of one channel of television signals after demultiplexing. This enables flexible response to changes in the number of channels of human-powered television signals, and also enables synchronization to be established through low bit rate operation to improve transmission efficiency, making it applicable to high-speed transmission line bit rates. can.

[Brief explanation of the drawing]

, FIG. 1 is a block diagram showing an embodiment of the video signal multiplex transmission system according to the present invention, FIG. 2 is a diagram showing one horizontal section of a television signal for explaining this embodiment, and FIG. FIG. 4 is a diagram corresponding to FIG. 1 showing a conventional system, and FIG. 5 is a diagram showing a conventional synchronization establishment circuit. In the figure, (21) is an A/D conversion section, (22) is a multiplexed pulse/sampling clock generation section, (23) is a simple multiplexing section (P/S conversion section), (24)
, (2B) is a transmission line interface, (25) is a transmission line, (27) is a simple separation unit (S/P conversion unit), (28) is a threshold setting unit, (29) is a horizontal synchronization detection unit,
(30) is a D/A conversion section, (31) is a separation counter control section, and (32) is a protection circuit. In each figure, the same reference numerals indicate the same or corresponding parts. Agent: Masuo Oiwa Figure 1 Figure 2 Figure 5 Procedural amendment (voluntary) Showa year, month, day 2, name of the invention: video signal multiplex transmission system 3, person making the amendment 5, subject of the amendment 1 +\- -+-16. The statement "horizontal synchronization end detected" on page 11, line 4 of the specification of amendment is corrected to "horizontal synchronization not detected."``2''

Claims (4)

[Claims] (1) Converting television signals to digital signals A
a multiplex pulse/sampling clock generator that generates a sampling clock and a multiplex pulse for synchronizing and multiplexing the signal generated in the A/D converter with a sampling clock, and the multiplex pulse/sampling unit; Based on the command from the clock generator, the A/D
a parallel/serial converter that converts parallel digital signals from the converter and others into serial digital signals; and a parallel/serial converter that receives digital signals from the parallel/serial converter via an interface, a transmission path, and an interface, and A serial/parallel converter that converts into parallel digital signals in the conversion order of the converter, and a threshold that sets a threshold corresponding to the horizontal synchronization portion of the television signal for each of the parallel digital signals from the serial/parallel converter. a hold setting section; a horizontal synchronization detection section that detects a horizontal synchronization signal by comparing a threshold from the threshold setting section with a horizontal synchronization signal from the parallel digital signal; and a detection signal from the horizontal synchronization detection section. a separation counter control section that counts and controls the phases to be demultiplexed based on the separation counter control section; a synchronization protection circuit that receives signals from the separation counter control section and protects the synchronization of the parallel digital signals; A video signal multiplex transmission system comprising: a D/A converter for converting into a television signal. (2) The video signal multiplex transmission system according to claim 1, wherein the television signal consists of at least one channel. (3) A video signal according to claim 2, which is a television signal of multiple channels, in which the television signals of the second and subsequent channels are converted in a different order from the parallel-to-serial conversion of the first channel signal. Multiplex transmission method. (4) The video signal multiplex transmission system according to any one of claims 1 to 3, wherein the threshold level is set higher than the horizontal synchronizing pulse level.