JPH01121960A - Data transfer device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention is directed to the communication between high-speed small-capacity memories such as semiconductor memories and low-speed large-capacity storage devices such as optical disk devices and magnetic disk devices. The present invention relates to a data transfer device for transferring large amounts of data at high speed.

(Prior Art) In recent years, optical disk devices suitable for storing large amounts of image data have been put into practical use. Furthermore, the capacity of magnetic disk devices, which have been widely used for information storage, is increasing. With the practical application of such large-capacity storage devices,
Information retrieval systems such as document image databases, medical image databases, and map databases have been developed. Although these disk memory devices such as optical disk devices and magnetic disk devices have a large capacity, the access speed is lower than that of DR used for computer main storage devices and image memory.
It is slower than semiconductor memory such as AM, and data cannot be transferred to and from semiconductor memory at high speed.

Therefore, disk memory devices are multi-channeled to speed up access, but there is a problem in that the devices become extremely expensive. In other words, in a multi-channel disk memory device, the rotational speed and read/write operations of multiple disks must be synchronized in order to function as a single high-speed, large-capacity storage device as a whole. The circuit scale required for this synchronization increases.

In addition, in a multi-channel disk memory device, the hardware for synchronization is designed according to the number of channels (number of disks), so the number of channels can be increased or decreased according to system specification requirements. I can't do it,
The problem is that it lacks flexibility.

(Problems to be Solved by the Invention) As described above, with conventional technology, it is difficult to transfer a large amount of data at high speed between a high-speed small-capacity memory such as a semiconductor memory and a low-speed large-capacity storage device such as a disk memory device. In this case, the hardware for synchronizing the rotation of multiple disks and the read/write operations is complicated and expensive, and there are also problems in that it is difficult to increase or decrease the number of channels in a low-speed mass storage device.

This invention was made to solve the above problems, and uses a single high-speed small capacity memory such as a semiconductor memory,
Data can be transferred between n low-speed large-capacity storage devices that have slower access speeds and larger capacities than this high-speed small-capacity memory at a speed commensurate with the access speed of the high-speed small-capacity memory. It is an object of the present invention to provide a data transfer device that does not require synchronization between n low-speed large-capacity storage devices and can easily increase or decrease the number of channels of the low-speed large-capacity storage devices.

[Structure of the Invention] (Means for Solving the Problems) A data transfer device according to the present invention has a device that controls data transfer between n low-speed large-capacity storage devices and a high-speed small-capacity memory. In addition to providing n interfaces, n address generation circuits that generate addresses of high-speed small capacity memory used for data exchange in synchronization with the data transfer timing are provided within these n interfaces, and The system is equipped with a selection means for sequentially and selectively activating the interfaces.

(Function) In this invention, by performing data transfer in parallel between a single high-speed small-capacity memory and n low-speed large-capacity storage devices, the access speed of the low-speed large-capacity storage device is effectively n.
Therefore, by appropriately selecting the number n of channels of the low-speed large-capacity storage device, it becomes possible to access the low-speed large-capacity storage device at a speed commensurate with the access speed of the high-speed small-capacity memory.

In addition, in this invention, n interfaces each having an address generation circuit corresponding to the n low-speed large-capacity storage devices are provided, and data transfer between the high-speed small-capacity memory and the low-speed large-capacity storage device is performed from these interfaces. Since the address of the high-speed small-capacity memory is supplied in synchronization with the data being stored, the multi-channel disk memory device is treated as one high-speed large-capacity storage device, and the host side can access the high-speed large-capacity memory. Unlike conventional devices that supply addresses, the n low-speed mass storage devices do not need to be synchronized; they only need to be able to read and write data in response to commands from an interface. Therefore, complicated hardware for synchronization is not required, and the number n of channels of the low-speed large-capacity storage device can be easily increased or decreased in accordance with the access speed of the high-speed small-capacity memory.

(Example) The present invention will be described in detail below. FIG. 1 shows a schematic configuration of a data transfer device according to an embodiment of the present invention. In the figure, n-4 optical disk devices 1 to 4 are low-speed large-capacity storage devices, and are connected to a parallel optical disk interface 5. The parallel optical disk interface 5 is a parallel optical disk interface that corresponds to each of the optical disk devices 1 to 4, and is connected to the control processor 7 via the system bus 6 and also connected to the image memory controller 8. has been done. The image memory controller 8 is a device that controls the dual-port image memory 9 as a high-speed small-capacity memory according to commands from the control processor 7, and performs buffering of data exchanged between the parallel optical disk interface 5 and the image memory 9, address processing, etc. Perform the conversion.

CRT display 10 displays the contents of image memory 9.

Next, the configuration of each part shown in FIG. 1 will be explained. Figures 2 and 2 are the first
This is a detailed view of the parallel optical disk interface 5 shown in the figure, in which optical disk interfaces 11-14 are provided corresponding to four optical disk devices 1-4. Communication between these optical disk interfaces 11 to 14 and optical disk devices 1 to 4 is performed using standard SC8I (Sa+all Computer System).
em Inter'f'ace). SCS
Optical disk interface 11 based on I protocol
14 and the optical disk devices 1-4 is performed by the control processor 7 passing through the bus interface 15 and sending commands to the optical disk interfaces 11-14.

Communication between the parallel optical disk interface 5 and the image memory controller 8 is such that one of the four optical disk interfaces 11 to 14 is selected by the selection circuit 16, and communication between the selected optical disk interface and the image memory controller 8 is performed. This is done by sending and receiving data, addresses and control signals. Selection circuit 16
The method for selecting one of the four optical disk interfaces 11 to 14 is a so-called round-tropin method in which these are selected cyclically in a predetermined order. Note that in the data transfer phase of communication between the selected optical disk interface and the image memory controller 8, data is transferred to DMA (D
direct Mea + ory Access) will be transferred. The DMA is activated by the control processor 7 setting the command register 17 via the bus interface 15.

FIG. 3 shows the optical disk interface 11 in FIG.
-14 is shown in detail.

Data transfer control using the SC3I protocol between this optical disk interface and the optical disk device is performed by the SCS.
This is done by the I controller 21.

Commands supplied from the control processor 7 via the bus interface 15 are sent to the SC9I controller 21.
given to. Data sent from the optical disk device to the image memory controller 8 via the SCSI controller 21, or data sent from the image memory controller 8 to the SCSI controller 8
The data sent to the optical disk device via the S-I controller 21 is processed as F I F O (First In F O).
irst 0ut) to the buffer 22 with the control function'
- Stored in time.

On the other hand, the address (x-y address) on the image memory 9 corresponding to this data is
3.24 and sent to the image memory controller 8. This address generation instruction is given by the control processor 7 via the bus interface 15 to
This is done by setting generation parameters in the address generation circuits 23 and 24. Further, data transfer control between the optical disk interface and the optical disk device and data and address transfer control between the optical disk interface and the image memory controller 8 are performed by a timing generation circuit based on a selection signal from the selection circuit 16. This is done by a control signal generated by 25', and its activation is based on the GO multiplication signal from command register 1'7'. The end of the data transfer is performed by the address generation end signal in the X and Y address generation circuits 23 and 24, and the control processor 7 can know this by reading the status via the bus interface 15.

FIG. 4 shows the image memory controller 8 in FIG. 1 in detail. In FIG. 4, the X address, Y address, and data from the parallel optical disk interface 5 are temporarily stored in buffers 31, 32, and 33 each having a FIFO control function, and are controlled by a control signal generated from the timing generation circuit 34. The image is transferred to the image memory 9. At this time, the addresses output from the X and Y address buffers 31 and 32 are latched into the X and Y address registers 35 and 36, respectively, and then converted by the decoder 37 from a two-dimensional address to a one-dimensional address, and the image memory 9.

On the other hand, data read from the image memory 9 is sent to the parallel optical disk interface 5 while being buffered under similar control. However, at this time, the address is sent from the parallel optical disk interface 5 side to the image memory 9. Instructions for reading and writing the image memory 9 are issued by setting control parameters in the control register 39 from the control processor 7 via the bus interface 38.

In FIGS. 2 to 4, the status register, gate buffer control system, etc. are omitted.

FIG. 5 is a flowchart showing the flow of control executed by the control processor 7. That is, first, the X and Y address generation circuits 23 and 24 in the optical disk interface in FIG. 3 are instructed to generate addresses by setting generation parameters (step 41). Next, by setting control parameters for the three control registers in the image memory controller 8 shown in FIG. 4, the image memory 9 is placed in a write mode or a read mode (step 42).

Next, as a preprocess to the SCSI controller 21 in FIG. 3, a command is sent to the optical disk device instructing it to prepare for data transfer, thereby making it possible to transfer data between the optical disk device and the image memory 9 ( Step 43).

Then, by issuing a data transfer start command to the command register 17 in the parallel optical disk interface 5 in FIG. 2 (step 44), and then checking the status of the X and Y address generation circuits 23 and 24 in FIG. Wait until data transfer is complete (
Step 45). Next, as post-processing to the SC5I controller 21 in FIG. 3, a command is sent to the controller 21, and after checking for completion of data transfer with the optical disk device, the 5C3I bus is released (step 46).

Next, the X and Y address generation circuit 23 in FIG.
A specific example of the address generation method in 24 will be explained with reference to FIGS. 6 to 8.

FIG. 6 shows that the image memory 9 is divided into four parts corresponding to the four partial screens ■~■ which are obtained by dividing the display screen of the CRT display 10 into four parts vertically and horizontally, and the addresses corresponding to each partial screen ■~■ are divided into four parts. The X and Y address generation circuits 23 and 24 in the optical disk interfaces 11 to 14 generate the addresses.

The images displayed on each of the partial screens ■ to ■ may be one meaningful image as a whole, or may be separate images.

In this case, each partial screen of the CRT display 10
The addresses corresponding to are generated in the order along the rask scan of the CRT display 10. That is, for example, the X and Y address generation circuit in the optical interface 11 generates an address corresponding to the first scanning line of the partial screen (2) in FIG.
An address corresponding to the first scanning line of the partial screen ■ is generated from the X and Y address generating circuit in the optical disk interface 13, and then an address corresponding to the first scanning line of the partial screen ■ is generated from the X and Y address generating circuit in the optical disk interface 13. An address is generated, and then an address corresponding to the first scan line of the partial screen (2) is generated from the X and Y address generation circuits in the optical disk interface 14. Thereafter, addresses corresponding to the scanning lines of each partial screen (1) to (2) are sequentially generated in the same manner.

In FIG. 7, the image memory 9 is divided into n parts corresponding to n partial screens (■, ■) obtained by dividing the display screen of the CRT display 10 into n parts in the vertical direction, and each partial screen (■) is created.

(2) Addresses corresponding to . . . are generated from X and Y address generation circuits in each optical disk interface.

In addition, in Fig. 7, it is assumed that the sizes of the partial screens ■, ■, etc. (the amount of corresponding image data) are not equal, and the By allocating small partial screens to the image memory 9, image data transfer for each partial screen is completed at the same time. For example, in the example shown in the figure, a wide partial screen (2) is assigned to the magnetic disk device 101 with a relatively high transfer speed, and a narrow partial screen is assigned to the optical disk device 102 with a relatively slow transfer speed.

When using low-speed mass storage devices with different data transfer speeds, the selection circuit 16 in FIG. 2 uses the round-robin method that sequentially selects n disk interfaces in a predetermined order as described above. without, n
A suitable method is to sequentially select disk interfaces on a first-come, first-served basis for data to be transferred between the corresponding low-speed large-capacity storage device and high-speed small-capacity memory. The selection pattern of the selection circuit 16 can be changed by the control processor 7 via the bus interface 15.

FIG. 8 shows a case where data transferred from each of the low-speed mass storage devices is sequentially displayed code by code on the CRT display 10. In this case, the address generation circuit sequentially increments addresses corresponding to the rask scan of the image memory. It suffices to have one set that generates .

[Effects of the Invention] According to the present invention, n low-speed large-capacity storage devices and n high-speed small-capacity memory devices are provided to generate addresses for the high-speed small-capacity memories in synchronization with data transfer timing between the two devices. The access speed of the low-speed mass storage device can be effectively increased by n times by providing n interfaces each having an address generation circuit of Not only can the low-speed large-capacity storage device be accessed at a speed commensurate with the access speed of the high-speed small-capacity memory, but also there is no need for n low-speed large-capacity storage devices to operate in synchronization with each other.
No complicated hardware is required for synchronization, making the system inexpensive.

In addition, in this invention, the number of channels n of the low-speed mass storage device
can be easily increased or decreased in response to the access speed of high-speed, small-capacity memory, increasing the flexibility of the system.Furthermore, by simply changing the address generation pattern of each address generation circuit, high-speed, small-capacity memory can be created using various patterns. Memory access becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a data transfer device according to an embodiment of the present invention, FIG. 2 is a diagram showing a detailed configuration of the parallel optical disk interface in FIG. 1, and FIG. 3 is a diagram showing the detailed configuration of the parallel optical disk interface in FIG. 2. 4 is a diagram showing a detailed configuration of the image memory controller in FIG. 1, FIG. 5 is a flowchart showing the control flow of the control processor in FIG. 1, and FIG. 6 is a diagram showing the detailed configuration of the image memory controller in FIG. FIGS. 7 and 8 are diagrams for explaining the address generation method for the image memory in the same embodiment, and FIGS. 7 and 8 are diagrams for explaining the address generation method for the image memory in another embodiment of the present invention. 1 to 4... Optical disk device (low-speed large-capacity storage device),
9... Image memory (high speed small capacity memory), 11 to 14
... Optical disk interface, 16... Selection circuit, 23.24... X and Y address generation circuit, 25.
...Timing generation circuit. Applicant's representative Patent attorney Takehiko Suzue 1 Nis Raki Memo, No. 80

Claims (4)

[Claims] (1) A single high-speed small-capacity memory, n low-speed large-capacity storage devices with slower access speeds and larger capacities than this high-speed small-capacity memory, and these n low-speed large-capacity storage devices and the high-speed small-capacity storage devices. n number of memory devices, each of which is provided between the low-speed large-capacity storage device and the high-speed small-capacity memory, controls data transfer between the low-speed large-capacity storage device and the high-speed small-capacity memory, and generates an address for the high-speed small-capacity memory in synchronization with this data transfer. A data transfer device comprising: n interfaces each having an address generation circuit; and selection means for sequentially and selectively activating these n interfaces. (2) The high-speed small-capacity memory stores image data to be displayed on the image display device, and the n address generation circuits correspond to each partial screen obtained by dividing the display screen of the image display device. 2. The data transfer device according to claim 1, wherein the data transfer device generates an address. (3) The data transfer device according to claim 1, wherein the selection means sequentially selects n interfaces in a predetermined order. (4) The scope of the claim characterized in that the selection means sequentially selects the n interfaces on a first-come, first-served basis for data to be transferred between the corresponding low-speed large-capacity storage device and high-speed small-capacity memory. The data transfer device according to item 1.