JPH01124554U - - Google Patents
Info
- Publication number
- JPH01124554U JPH01124554U JP1877488U JP1877488U JPH01124554U JP H01124554 U JPH01124554 U JP H01124554U JP 1877488 U JP1877488 U JP 1877488U JP 1877488 U JP1877488 U JP 1877488U JP H01124554 U JPH01124554 U JP H01124554U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- load drive
- output terminal
- drive transistor
- timing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Investigating Or Analyzing Materials By The Use Of Electric Means (AREA)
Description
第１図は本考案に係るセンサ回路の一実施例を
示すブロツク構成図、第２図はセンサ回路の具体
例を示すブロツク図、第３図は容量性負荷の充電
特性を示す図、第４図は従来のセンサ回路を示す
ブロツク図である。
１…出力端子、２…出力駆動回路、３…センサ
回路、４…容量性負荷、５…制御回路、３１…駆
動トランジスタ、３２…インバータ、３３，３４
…ラツチ、３５，３６…タイミング信号端子、３
７…オアゲート、３８…エクスクルーシブオアゲ
ート、３９…判定出力端子、４１…負荷抵抗、６
１…抵抗、６２…スイツチ。
FIG. 1 is a block diagram showing an embodiment of the sensor circuit according to the present invention, FIG. 2 is a block diagram showing a specific example of the sensor circuit, FIG. 3 is a diagram showing charging characteristics of a capacitive load, and FIG. The figure is a block diagram showing a conventional sensor circuit. DESCRIPTION OF SYMBOLS 1... Output terminal, 2... Output drive circuit, 3... Sensor circuit, 4... Capacitive load, 5... Control circuit, 31... Drive transistor, 32... Inverter, 33, 34
...Latch, 35, 36...Timing signal terminal, 3
7...OR gate, 38...Exclusive OR gate, 39...Judgment output terminal, 41...Load resistance, 6
1...Resistance, 62...Switch.
Claims (1)
、出力端子に接続された負荷駆動トランジスタと
、該出力端子を入力とする比較器と、前記負荷駆
動トランジスタを制御する１以上のタイミングパ
ルス入力端子と、各タイミングでの判定結果を論
理合成する論理回路とを含むことを特徴とするセ
ンサ回路。 In a load detection circuit of a capacitive load drive circuit, a load drive transistor connected to an output terminal, a comparator that receives the output terminal as an input, and one or more timing pulse input terminals that control the load drive transistor; A sensor circuit comprising: a logic circuit that logically synthesizes determination results at each timing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1877488U JPH01124554U (en) | 1988-02-16 | 1988-02-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1877488U JPH01124554U (en) | 1988-02-16 | 1988-02-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01124554U true JPH01124554U (en) | 1989-08-24 |
Family
ID=31233712
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1877488U Pending JPH01124554U (en) | 1988-02-16 | 1988-02-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01124554U (en) |
-
1988
- 1988-02-16 JP JP1877488U patent/JPH01124554U/ja active Pending
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